OXFORD OXmPCI952 DATA SHEET
FEATURES
OXmPCI952 DATA SHEET
Integrated High Performance Dual UARTs,
8-bit Local Bus/Parallel Port.
3.3v PCI/miniPCI interface.
• Dual 16C950 High performance UART channels
• 8-bit Pass-through Local Bus (PCI Bridge)
• IEEE1284 Compliant SPP/EPP/ECP parallel port (with
external transceiver)
• Efficient 32-bit, 33MHz, Multi-function target-only PCI
controller, fully compliant to PCI Local Bus specification 3.0,
and PCI Power Management Specification 1.1
• PCI and miniPCI Modes (with CLKRUN# and PME#
generation in the D3cold state, in miniPCI mode)
• UARTs fully software compatible with 16C550-type devices.
• UART operation up to 60 MHz via external clock source. Up
to 20MHz with the crystal oscillator.
• Baud rates up to 60Mbps in external 1x clock mode and
15Mbps in asynchronous mode.
• 128-byte deep FIFO per transmitter and receiver
• Flexible clock prescaler, from 1 to 31.875
• Automated in-band flow control using programmable
Xon/Xoff in both directions
• Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
DESCRIPTION
The OXmPCI952 is a single chip solution for PCI and miniPCI based serial and parallel expansion add-in cards. It is
a dual function PCI device, where function 0 offers two
ultra-high performance OX16C950 UARTs, and function 1
is configurable either as an 8-bit Local Bus or a bidirectional parallel port.
Each UART channel in the OXmPCI952 is the fastest
available PC-compatible UART, offering data rates up to
15Mbps and 128-byte deep transmitter and receiver FIFOs.
The deep FIFOs reduce CPU overhead and allow
utilisation of higher data rates. Each UART channel is
software compatible with the widely used industry-standard
16C550 devices (and compatibles), as well as the
OX16C95x family of high performance UARTs. In addition
to increased performance and FIFO size, the UARTs also
provide the full set of OX16C95x enhanced features
including automated in-band flow control, readable FIFO
levels etc.
To enhance device driver efficiency and reduce interrupt
latency, internal UARTs have multi-port features such as
shadowed FIFO fill levels, a global interrupt source register
and Good-Data Status, readable in four adjacent DWORD
• Arbitrary trigger levels for receiver and transmitter FIFO
interrupts and automatic in-band and out-of-band flow
control
• Infra-red (IrDA) receiver and transmitter operation
• 9-bit data framing, as well as 5,6,7 and 8 bits
• Detection of bad data in the receiver FIFO
• Global Interrupt Status and readable FIFO levels to facilitate
implementation of efficient device drivers.
• Local registers to provide status/control of device functions.
• 11 multi-purpose I/O pins, which can be configured as input
interrupt pins or ‘wake-up’.
• Auto-detection of a wide range of Microwire
EEPROMs, to configure device parameters.
• Function access, to pre-configure each function prior to
handover to generic device drivers.
• Operation via IO or memory mapping.
• 3.3V operation (5v tolerance on selected I/Os)
• Extended Operating Temp. Range : -40C to 105C
• 160-pin LQFP/176-pin BGA package
TM
compatible
registers visible to logical functions in I/O space and
memory space.
Expansion of serial cards beyond two channels is possible
using the 8-bit pass-through Local Bus function. The
addressable space can be increased up to 256 bytes, and
divided into four chip-select regions. This flexible
expansion scheme caters for cards with up to 18 serial
ports using external 16C950, 16C952, 16C954 or
compatible devices, or composite applications such as
combined serial and parallel port expansion cards.
The parallel port is an IEEE 1284 compliant SPP/EPP/
ECP parallel port that fully supports the existing Centronics
interface. The parallel port can be enabled in place of the
Local Bus. An external bus transceiver is required for 5V
parallel port operation.
The configuration register values are programmed using an
TM
external Microwire
compatible serial EEPROM. This
EEPROM can also be used to provide function access, to
pre-configure each UART into enhanced modes or preconfigure devices on the local bus/parallel port, prior to any
PCI configuration accesses and before control is handed to
(generic) device drivers.
Oxford Semiconductor Ltd.
External—Free Release
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 2005
OXmPCI952 DataSheet DS-0020 – June 2005
OXFORD SEMICONDUCTOR LTD.
REVISION HISTORY
REV DATE REASON FOR CHANGE / SUMMARY OF CHANGE
1.0 05/09/2003 Initial DataSheet
Jan 2005 25/1/2005 Revisions for additional 176-pin BGA layout
Jun 2005 8/6/2005 Revision for additional green order code for 160-pin LQFP layout
OXmPCI952
DS-0020 Jun 05 Page 2
OXFORD SEMICONDUCTOR LTD.
OXmPCI952
TABLE OF CONTENTS
1 BLOCK DIAGRAM ................................................................................................................................8
2 PIN INFORMATION—160-PIN LQFP....................................................................................................9
2.1 PINOUTS.............................................................................................................................................................................9
2.2 PIN DESCRIPTIONS.........................................................................................................................................................10
3 PIN INFORMATION—176-PIN BGA....................................................................................................16
3.1 PINOUTS...........................................................................................................................................................................16
3.2 PIN DESCRIPTIONS.........................................................................................................................................................17
4 CONFIGURATION & OPERATION.....................................................................................................22
5 PCI TARGET CONTROLLER..............................................................................................................23
5.1 OPERATION.....................................................................................................................................................................23
5.2 CONFIGURATION SPACE...............................................................................................................................................23
5.2.1 PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................24
5.3 ACCESSING LOGICAL FUNCTIONS..............................................................................................................................26
5.3.1 PCI ACCESS TO INTERNAL UARTS...........................................................................................................................26
5.3.2 PCI ACCESS TO 8-BIT LOCAL BUS............................................................................................................................27
5.3.3 PCI ACCESS TO PARALLEL PORT............................................................................................................................28
5.4 ACCESSING LOCAL CONFIGURATION REGISTERS...................................................................................................29
5.4.1 LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00)........................................................29
5.4.2 MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04)............................................................30
5.4.3 LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08):..................................................................32
5.4.4 LOCAL BUS TIMING PARAMETER REGISTER 2 ‘LT2’ (OFFSET 0X0C):.................................................................33
5.4.5 UART RECEIVER FIFO LEVELS ‘URL’ (OFFSET 0X10).............................................................................................35
5.4.6 UART TRANSMITTER FIFO LEVELS ‘UTL’ (OFFSET 0X14)......................................................................................35
5.4.7 UART INTERRUPT SOURCE REGISTER ‘UIS’ (OFFSET 0X18)...............................................................................35
5.4.8 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X1C)................................................36
5.5 PCI INTERRUPTS.............................................................................................................................................................38
5.6 POWER MANAGEMENT.................................................................................................................................................. 39
5.6.1 POWER MANAGEMENT OF FUNCTION 0.................................................................................................................39
5.6.2 POWER MANAGEMENT OF FUNCTION 1.................................................................................................................40
5.7 MINIPCI SUPPORT...........................................................................................................................................................42
5.8 DEVICE DRIVERS............................................................................................................................................................46
6 INTERNAL OX16C950 UARTS...........................................................................................................47
6.1 OPERATION – MODE SELECTION................................................................................................................................. 47
6.1.1 450 MODE.....................................................................................................................................................................47
6.1.2 550 MODE.....................................................................................................................................................................47
6.1.3 EXTENDED 550 MODE................................................................................................................................................47
6.1.4 750 MODE.....................................................................................................................................................................47
6.1.5 650 MODE.....................................................................................................................................................................47
6.1.6 950 MODE.....................................................................................................................................................................48
6.2 REGISTER DESCRIPTION TABLES...............................................................................................................................49
6.3 RESET CONFIGURATION...............................................................................................................................................53
6.3.1 HARDWARE RESET....................................................................................................................................................53
6.3.2 SOFTWARE RESET.....................................................................................................................................................53
6.4 TRANSMITTER AND RECEIVER FIFOS.........................................................................................................................54
6.4.1 FIFO CONTROL REGISTER ‘FCR’..............................................................................................................................54
6.5 LINE CONTROL & STATUS.............................................................................................................................................55
6.5.1 FALSE START BIT DETECTION..................................................................................................................................55
6.5.2 LINE CONTROL REGISTER ‘LCR’...............................................................................................................................55
6.5.3 LINE STATUS REGISTER ‘LSR’..................................................................................................................................56
DS-0020 Jun 05 Page 3
OXFORD SEMICONDUCTOR LTD.
6.6 INTERRUPTS & SLEEP MODE........................................................................................................................................57
6.6.1 INTERRUPT ENABLE REGISTER ‘IER’.......................................................................................................................57
6.6.2 INTERRUPT STATUS REGISTER ‘ISR’.......................................................................................................................58
6.6.3 INTERRUPT DESCRIPTION........................................................................................................................................58
6.6.4 SLEEP MODE...............................................................................................................................................................59
6.7 MODEM INTERFACE.......................................................................................................................................................59
6.7.1 MODEM CONTROL REGISTER ‘MCR’........................................................................................................................59
6.7.2 MODEM STATUS REGISTER ‘MSR’...........................................................................................................................60
6.8 OTHER STANDARD REGISTERS...................................................................................................................................60
6.8.1 DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................60
6.8.2 SCRATCH PAD REGISTER ‘SPR’...............................................................................................................................60
6.9 AUTOMATIC FLOW CONTROL.......................................................................................................................................61
6.9.1 ENHANCED FEATURES REGISTER ‘EFR’.................................................................................................................61
6.9.2 SPECIAL CHARACTER DETECTION..........................................................................................................................62
6.9.3 AUTOMATIC IN-BAND FLOW CONTROL...................................................................................................................62
6.9.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL.........................................................................................................62
6.10 BAUD RATE GENERATION.............................................................................................................................................63
6.10.1 GENERAL OPERATION...............................................................................................................................................63
6.10.2 CLOCK PRESCALER REGISTER ‘CPR’......................................................................................................................63
6.10.3 TIMES CLOCK REGISTER ‘TCR’.................................................................................................................................63
6.10.4 EXTERNAL 1X CLOCK MODE.....................................................................................................................................65
6.10.5 CRYSTAL OSCILLATOR CIRCUIT..............................................................................................................................65
6.11 ADDITIONAL FEATURES................................................................................................................................................65
6.11.1 ADDITIONAL STATUS REGISTER ‘ASR’....................................................................................................................65
6.11.2 FIFO FILL LEVELS ‘TFL & RFL’...................................................................................................................................66
6.11.3 ADDITIONAL CONTROL REGISTER ‘ACR’.................................................................................................................66
6.11.4 TRANSMITTER TRIGGER LEVEL ‘TTL’......................................................................................................................67
6.11.5 RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’......................................................................................................67
6.11.6 FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’....................................................................................................................67
6.11.7 DEVICE IDENTIFICATION REGISTERS......................................................................................................................67
6.11.8 CLOCK SELECT REGISTER ‘CKS’..............................................................................................................................68
6.11.9 NINE-BIT MODE REGISTER ‘NMR’.............................................................................................................................68
6.11.10 MODEM DISABLE MASK ‘MDM’..................................................................................................................................69
6.11.11 READABLE FCR ‘RFC’.................................................................................................................................................69
6.11.12 GOOD-DATA STATUS REGISTER ‘GDS’....................................................................................................................69
6.11.13 PORT INDEX REGISTER ‘PIX’.....................................................................................................................................69
6.11.14 CLOCK ALTERATION REGISTER ‘CKA’.....................................................................................................................70
OXmPCI952
7 LOCAL BUS ........................................................................................................................................71
7.1 OVERVIEW.......................................................................................................................................................................71
7.2 OPERATION.....................................................................................................................................................................71
7.3 CONFIGURATION & PROGRAMMING............................................................................................................................72
8 BIDIRECTIONAL PARALLEL PORT ..................................................................................................73
8.1 OPERATION AND MODE SELECTION...........................................................................................................................73
8.1.1 SPP MODE...................................................................................................................................................................73
8.1.2 PS2 MODE....................................................................................................................................................................73
8.1.3 EPP MODE...................................................................................................................................................................73
8.1.4 ECP MODE...................................................................................................................................................................73
8.2 PARALLEL PORT INTERRUPT.......................................................................................................................................74
8.3 REGISTER DESCRIPTION...............................................................................................................................................75
8.3.1 PARALLEL PORT DATA REGISTER ‘PDR’.................................................................................................................75
8.3.2 ECP FIFO ADDRESS / RLE.........................................................................................................................................75
8.3.3 DEVICE STATUS REGISTER ‘DSR’............................................................................................................................75
8.3.4 DEVICE CONTROL REGISTER ‘DCR’.........................................................................................................................76
8.3.5 EPP ADDRESS REGISTER ‘EPPA’.............................................................................................................................76
8.3.6 EPP DATA REGISTERS ‘EPPD1-4’.............................................................................................................................76
DS-0020 Jun 05 Page 4
OXFORD SEMICONDUCTOR LTD.
8.3.7 ECP DATA FIFO...........................................................................................................................................................76
8.3.8 TEST FIFO....................................................................................................................................................................76
8.3.9 CONFIGURATION A REGISTER.................................................................................................................................76
8.3.10 CONFIGURATION B REGISTER.................................................................................................................................76
8.3.11 EXTENDED CONTROL REGISTER ‘ECR’...................................................................................................................77
OXmPCI952
9 SERIAL EEPROM................................................................................................................................78
9.1 SPECIFICATION............................................................................................................................................................... 78
9.1.1 ZONE 0: HEADER........................................................................................................................................................79
9.1.2 ZONE 1: LOCAL CONFIGURATION REGISTERS.......................................................................................................80
9.1.3 ZONE 2: IDENTIFICATION REGISTERS.....................................................................................................................81
9.1.4 ZONE 3: PCI CONFIGURATION REGISTERS............................................................................................................81
9.1.5 ZONE 4 : POWER MANAGEMENT DATA (AND DATA_SCALE ZONE).............................................................82
9.1.6 ZONE 5 : FUNCTION ACCESS....................................................................................................................................82
9.1.7 MINIMUM PROGRAMMING REQUIREMENTS...........................................................................................................83
10 OPERATING CONDITIONS.............................................................................................................84
10.1 DC ELECTRICAL CHARACTERISTICS..........................................................................................................................84
11 AC ELECTRICAL CHARACTERISTICS..........................................................................................86
11.1 PCI BUS............................................................................................................................................................................86
11.2 LOCAL BUS......................................................................................................................................................................86
11.3 SERIAL PORTS................................................................................................................................................................88
12 TIMING WAVEFORMS.....................................................................................................................89
13 PACKAGE INFORMATION............................................................................................................104
13.1 160-PIN LQFP PACKAGE..............................................................................................................................................104
13.2 176-PIN BGA PACKAGE................................................................................................................................................105
14 ORDERING INFORMATION..........................................................................................................106
DS-0020 Jun 05 Page 5
OXFORD SEMICONDUCTOR LTD.
PERFORMANCE COMPARISON
Feature
Internal serial channels 2 0 0
Integral IEEE 1284 EPP/ECP parallel port yes no no
Multi-function PCI device yes no no
Support for PCI Power Management yes no no
Zero wait-state write operation yes1 no no
No. of available Local Bus interrupt pins 11 2 2
DWORD access to UART Interrupt Source
Registers & FIFO Levels
Good-Data status yes no no
Full Plug and Play with external EEPROM yes yes yes
External 1x baud rate clock yes no no
Max baud rate in normal mode 15 Mbps 115 Kbps 1.5 Mbps
Max baud rate in 1x clock mode 60 Mbps n/a n/a
FIFO depth 128 16 64
Sleep mode yes no yes
Auto Xon/Xoff flow yes no yes
Auto CTS#/RTS# flow yes no yes
Auto DSR#/DTR# flow yes no no
No. of Rx interrupt thresholds 128 4 4
No. of Tx interrupt thresholds 128 1 4
No. of flow control thresholds 128 n/a 4
Transmitter empty interrupt yes no no
Readable status of flow control yes no no
Readable FIFO levels yes no no
Clock prescaler options 248 n/a 2
Rx/Tx disable yes no no
Software reset yes no no
Device ID yes no no
9-bit data frames yes no no
RS485 buffer enable yes no no
Infra-red (IrDA) yes no yes
OXmPCI952
16C552 +
PCI Bridge
16C652 +
PCI Bridge
OXmPCI952
yes no no
Table 1: OXmPCI952 performance compared with PCI Bridge + generic UART combinations
Note 1: Zero wait-state applies only to the internal UARTs (after the assertion of DEVSEL#).
Read operation incurs 1 wait state.
DS-0020 Jun 05 Page 6
OXFORD SEMICONDUCTOR LTD.
Improvements of the OXmPCI952 over discrete solutions
OXmPCI952
Higher degree of integration:
The OXmPCI952 device offers two internal 16C950 highperformance UARTs and an 8-bit Local Bus or a
Bi-directional parallel port.
Multi-function device:
The OXmPCI952 is a multi-function device to enable users
to load individual device drivers for the internal serial ports,
drivers for the peripheral devices connected to the Local
Bus or drivers for the internal parallel port.
Dual Internal OX16C950 UARTs
The OXmPCI952 device contains two ultra-high
performance UARTs, which can increase driver efficiency
by using features such as the 128-byte deep transmitter &
receiver FIFOs, flexible clock options, automatic flow
control, programmable interrupt and flow control trigger
levels and readable FIFO levels. Data rates are up to
60Mbps.
Improved access timing:
Access to the internal UARTs, require zero or one PCI wait
states. A PCI read transaction from an internal UART can
complete within five PCI clock cycles and a write
transaction to an internal UART can complete within four
PCI clock cycles.
Reduces interrupt latency:
The OXmPCI952 device offers shadowed FIFO levels and
Interrupt status registers of the internal UARTs, and the
MIO pins. This reduces the device driver interrupt latency.
Power management:
The OXmPCI952 device complies with the PCI Power
Management Specification 1.1 and the Microsoft
Communications Device-class Power Management
Specification 2.0 (2000). Both functions offer the extended
capabilities for Power Management. This achieves
significant power savings by enabling device drivers to
power down the PCI functions. For function 0, this is
through switching off the channel clock, in power state D3.
Wake-up (PME# generation) can be requested by either
functions. For function 0, this is via the RI# inputs of the
UARTs in the power-state D3 or any modem line and SIN
inputs of the UARTs in power-state D2. For function 1, this
is via the MIO[2] input.
External EEPROM:
The OXmPCI952 device is configured from an external
EEPROM, to meet the end-user’s requirements. An
overrun detection mechanism built into the eeprom
controller prevents the PCI system from ‘hanging’ due to an
incorrectly programmed eeprom.
An eeprom is required for this device to meet the minimum
programming requirements. See Section 10.1.7
DS-0020 Jun 05 Page 7
OXFORD SEMICONDUCTOR LTD.
1 BLOCK DIAGRAM
OXmPCI952
MODE
FIFOSEL
PCI/miniPCI
AD[31:0]
C/BE[3:0]#
PCI_CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RESET#
INTA#
INTB#/CLKRUN#
PME#
XTLI
XTLO
UART_Clk_Out
Local_Bus Clk
Config.
Interface
PCI
(miniPCI)
Interface
Clock &
Baud Rate
Generator
SOUT{1:0]
SIN[1:0]
Function 0
s
u
B
l
o
r
t
n
o
C
/
a
t
a
D
e
c
a
f
r
e
t
n
I
Interrupt
Logic
Function 1
Dual
UARTs
MIO Pins
Parallel Port
RTS[1:0]
DTR{1:0]
CTS{1:0]
DSR{1:0]
DCD{1:0]
RI{1:0]
MIO[10:0]
PD[7:0]
ACK#
PE
BUSY
SLCT
ERR#
SLIN#
INIT#
AFD#
STB#
LBA7:0]
LBCS[3:0]
LBD[7:0]
EE_DI
EE_CS
EE_CK
EE_DO
EEPROM
Interface
OXmPCI952 Block Diagram
Local Bus
LBWR#
LBRD#
LBRST
DATA_DIR
DS-0020 Jun 05 Page 8
OXFORD SEMICONDUCTOR LTD.
2 PIN INFORMATION—160-PIN LQFP
2.1 Pinouts
OXmPCI952
Dual UARTs + 8-BIT Local Bus (Mode = 0)
INTB#/CLKRUN#
LBRST
LBRST#
INTA#
PME#
C/BE3#
IDSEL
121
LBA1
122
LBA0
123
124
125
MIO7
126
MIO6
127
MIO5
128
MIO4
129
MIO3
130
MIO2
131
MIO1
132
MIO0
133
134
135
RST#
136
GND
137
CLK
138
AD31
139
AD30
140
AD29
141
GND
142
AD28
143
AD27
144
AD26
145
GND
146
147
AD25
148
AD24
149
150
151
AD23
152
AD22
153
GND
154
VDD
155
AD21
156
AD20
157
AD19
158
VDD
159
GND
160
AD18
LBA2
120
1234567891011121314151617
AD17
LBWR#
VDD
GND
LBA4
LBA5
LBA6
LBDOUT
LBD0
LBA3
LBCS0#
LBCS1#
LBCS2#
LBCS3#
LBRD#
VDD
GND
119
118
117
116
115
114
113
112
111
110
109
LBD1
LBCLK
LBA7
GND
108
107
106
105
104
102
101
100
103
OXmPCI952-LQ-A
1920212223242526272829303132333435
18
PAR
VDD
GND
GND
AD16
IRDY#
TRDY#
STOP#
PERR#
SERR#
C/BE2#
FRAME#
DEVSEL#
GND
AD15
AD14
AD13
AD12
AD11
C/BE1#
LBD2
LBD3
VDD
GND
LBD4
LBD5
LBD6
LBD7
MIO8
MIO9
MIO10
99989796959493929190898887
AD9
AD8
AD7
AD6
VDD
AD10
AD5
VDD
GND
GND
C/BE0#
VDD
VDD
VDDNCNC
VDD
PCI/mini-PCI
VDD
8584838281
86
3637383940
AD3
AD2
AD1
AD0
AD4
GND
EE_CS
EE_DO
Dual UARTs + Parallel Port (Mode = 1)
SLCT
NCNCNCNCNCNCVDD
VDD
GND
ERR#
120
119
118
117
116
115
121
BUSY
122
80
NC
79
NC
78
NC
77
NC
76
VDD
75
VDD
74
VDD
73
VDD
72
VDD
71
UART_Ck_Out
70
GND
69
VDD
68
SIN1
67
RI1#
66
DCD1#
65
VDD
64
XTLO
63
XTLI
62
GND
61
DSR1#
60
CTS1#
59
DTR1#
58
RTS1#
57
VDD
56
GND
55
SOUT1
54
SOUT0
53
RTS0#
52
DTR0#
51
CTS0#
50
DSR0#
49
DCD0#
48
RI0#
47
SIN0
46
FIFOSEL
45
Mode
44
GND
43
VDD
42
EE_DI
41
EE_CK
ACK#
INTA#
INTB#/CLKRUN#
PME#
C/BE3#
IDSEL
MIO7
MIO6
MIO5
MIO4
MIO3
MIO2
MIO1
RST#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
PE
123
124
NC
125
126
127
128
129
130
131
132
NC
133
134
135
136
GND
137
CLK
138
139
140
141
GND
142
143
144
145
GND
146
147
148
149
150
151
152
153
GND
154
VDD
155
156
157
158
VDD
159
GND
160
OXmPCI952-LQ-A
1234567891011121314151617
AD17
AD16
IRDY#
TRDY#
C/BE2#
FRAME#
INIT#
PD0
PD1
PD2
PD3
VDD
GND
GNDNCSLIN#
AFD#
STB#
114
113
112
111
110
109
108
107
106
105
104
PAR
GND
DEVSEL#
VDD
GND
AD15
AD14
STOP#
PERR#
SERR#
C/BE1#
PD4
PDOUT
GND
99989796959493929190898887
102
101
100
103
1920212223242526272829303132333435
18
AD9
AD8
VDD
GND
GND
AD13
AD12
AD11
AD10
VDD
VDD
VDDNCNC
PD5
PD6
AD7
C/BE0#
VDD
PD7
MIO8
MIO9
MIO10
PCI/mini-PCI
VDD
8584838281
86
80
NC
79
NC
78
NC
77
NC
76
VDD
75
VDD
74
VDD
73
VDD
72
VDD
71
NC
70
GND
69
VDD
68
SIN1
67
RI1#
66
DCD1#
65
VDD
64
XTLO
63
XTLI
62
GND
61
DSR1#
60
CTS1#
59
DTR1#
58
RTS1#
57
VDD
56
GND
55
SOUT1
54
SOUT0
53
RTS0#
52
DTR0#
51
CTS0#
50
DSR0#
49
DCD0#
48
RI0#
47
SIN0
46
FIFOSEL
45
Mode
44
GND
43
VDD
42
EE_DI
41
3637383940
AD2
AD1
AD6
AD5
AD4
AD3
VDD
GND
GND
EE_CK
AD0
EE_CS
EE_DO
DS-0020 Jun 05 Page 9
OXFORD SEMICONDUCTOR LTD.
2.2 Pin Descriptions
For the actual pinouts of the OXmPCI952 device for this package type, please refer to section 2.1 Pinouts.
PCI / mini-PCI Interface
Mode 0, Mode 1 Dir1 Name Description
139, 140, 141, 143, 144,
145, 147, 148, 151, 152,
155, 156, 157, 160, 1, 2,
14, 15, 18, 19, 20, 23, 24,
26, 28, 29, 32, 33, 34, 36,
37, 38
149, 3, 13, 27 P_I C/BE[3:0]# PCI Command/Byte enable
137 P_I CLK PCI system clock
4 P_I FRAME# Cycle Frame
7 P_O DEVSEL# Device Select
5 P_I IRDY# Initiator ready
6 P_O TRDY# Target ready
9 P_O STOP# Target Stop request
12 P_I/O PAR Parity
11 P_O SERR# System error
10 P_I/O PERR# Parity error
150 P_I IDSEL Initialisation device select
135 P_I RST# PCI system reset
133 P_OD INTA# Default PCI Interrupt Line. For Function 0 and Function 1
134
134
138 P_OD PME# Power management event
Serial port pins
Mode 0, Mode 1 Dir1 Name Description
46 I FIFOSEL FIFO select. For backward compatibility with 16C550,
55, 54 O(h) SOUT[1:0]
68, 47 I(h)
66, 49 I(h) DCD[1:0]# Active-low modem data-carrier-detect input
P_I/O AD[31:0] Multiplexed PCI Address/Data bus
P_OD
P_I/O
I(h)
INTB#
CLKRUN#
IrDA_Out[1:0]
SIN[1:0]
IrDA_In[1:0]
Optional PCI interrupt Line (PCI Mode)
ClockRun# Line (mini-PCI mode)
16C650 and 16C750 devices the UARTs’ FIFO depth is 16
when FIFOSEL is low. The FIFO size is increased to 128
when FIFOSEL is high. The unlatched state of this pin is
readable by software. The FIFO size may also be set to 128
by setting FCR[5] when LCR[7] is set, or by putting the
device into enhanced mode.
UART serial data outputs
UART IrDA data output when MCR[6] of the corresponding
channel is set in enhanced mode
UART serial data inputs
UART IrDA data input when IrDA mode is enabled (see
above)
OXmPCI952
DS-0020 Jun 05 Page 10
OXFORD SEMICONDUCTOR LTD.
Serial port pins
Mode 0, Mode 1 Dir1 Name Description
59, 52 O(h)
58, 53 O(h) RTS[1:0]# Active-low modem request-to-send output. If automated
60, 51 I(h) CTS[1:0]# Active-low modem clear-to-send input. If automated CTS#
61, 50 I(h)
67, 48 I(h)
64 O XTLO Crystal oscillator output
63 I XTLI Crystal oscillator input up to 20MHz. External clock pin up to
O(h)
O(h)
I(h)
I(h)
DTR[1:0]#
485_En[1:0]
Tx_Clk_Out[1:0]
DSR[1:0]#
Rx_Clk_In[1:0]
RI[1:0]#
Tx_Clk_In[1:0]
OXmPCI952
Active-low modem data-terminal-ready output. If automated
DTR# flow control is enabled, the DTR# pin is asserted and
deasserted if the receiver FIFO reaches or falls below the
programmed thresholds, respectively.
In RS485 half-duplex mode, the DTR# pin may be
programmed to reflect the state of the transmitter empty bit to
automatically control the direction of the RS485 transceiver
buffer (see register ACR[4:3])
Transmitter 1x clock (baud rate generator output). For
isochronous applications, the 1x (or Nx) transmitter clock
may be asserted on the DTR# pins (see register CKS[5:4])
RTS# flow control is enabled, the RTS# pin is deasserted
and reasserted whenever the receiver FIFO reaches or falls
below the programmed thresholds, respectively.
flow control is enabled, upon deassertion of the CTS# pin,
the transmitter will complete the current character and enter
the idle mode until the CTS# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the CTS# pin.
Active-low modem data-set-ready input. If automated DSR#
flow control is enabled, upon deassertion of the DSR# pin,
the transmitter will complete the current character and enter
the idle mode until the DSR# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the DSR# pin
External receiver clock for isochronous applications. The
Rx_Clk_In is selected when CKS[1:0] = ‘01’.
Active-low modem Ring-Indicator input
External transmitter clock. This clock can be used by the
transmitter (and indirectly by the receiver) when CKS[6]=’1’.
60MHz.
DS-0020 Jun 05 Page 11
OXFORD SEMICONDUCTOR LTD.
8-bit local bus
Mode 0 Dir1 Name Description
71
123 O(h) LBRST Local bus active-high reset
124 O LBRST# Local bus active-low reset
102 O LBDOUT Local bus data out enable. This pin can be used by external
108 O LBCLK Buffered PCI clock. Can be enabled / disabled by software
113, 114, 115, 116 O(h)
111 O
112 O
104, 105, 106, 107
119, 120, 121, 122
92, 93, 94, 95
98, 99, 100, 101
Parallel port
Mode 1 Dir1 Name Description
123 I(h)
122 I(h) PE Paper Empty. Activated by printer when it runs out of paper.
121 I(h)
107 OD(h)
120 I(h) SLCT Peripheral selected. Asserted by peripheral when selected.
119 I(h) ERR# Error. Held low by the peripheral during an error condition.
106 OD(h)
105 OD(h)
O UART_Clk_Out Buffered crystal output. This clock can drive external UARTs
connected to the local bus. Can be enabled / disabled by
software.
transceivers; it is high when LBD[7:0] are in output mode and
low when they are in input mode.
LBCS[3:0]#
O(h)
O(h) LBA[7:0] Local bus address signals
I/O(h) LBD[7:0] Local bus data signals
O(h)
O(h)
O(h)
O
Z
I(h)
I(h)
LBDS[3:0]#
LBWR#
LBRDWR#
LBRD#
Hi-Z
ACK#
INTR#
BUSY
WAIT#
SLIN#
ADDRSTB#
INIT#
INIT#
AFD#
DATASTB#
Local bus active-low Chip-Select (Intel mode)
Local bus active-low Data-Strobe (Motorola mode)
Local Bus active-low write-strobe (Intel mode)
Local Bus Read-not-Write control (Motorola mode)
Local Bus active-low read-strobe (Intel mode)
Permanent high impedance (Motorola mode)
Acknowledge (SPP mode). ACK# is asserted (low) by the
peripheral to indicate that a successful data transfer has
taken place.
Identical function to ACK# (EPP mode).
Busy (SPP mode). BUSY is asserted (high) by the peripheral
when it is not ready to accept data
Wait (EPP mode). Handshake signal for interlocked IEEE
1284 compliant EPP cycles.
Select (SPP mode). Asserted by host to select the peripheral
Address strobe (EPP mode) provides address read and write
strobe
Initialise (SPP mode). Commands the peripheral to initialise.
Initialise (EPP mode). Identical function to SPP mode.
Auto Feed (SPP mode, open-drain)
Data strobe (EPP mode) provides data read and write strobe
OXmPCI952
DS-0020 Jun 05 Page 12
OXFORD SEMICONDUCTOR LTD.
Parallel port
Mode 1 Dir1 Name Description
104 OD(h)
92, 93, 94, 95
98, 99, 100, 101
102 O PDOUT Parallel Port data out enable. This pin should be used by
Multi-purpose & External interrupt pins
Dir1 Name Description
Mode 0 Mode 1
132
-
131
131
130
130
89, 90, 91
125, 126, 127, 128, 129
EEPROM pins
Mode 0, Mode 1 Dir1 Name Description
41 O EE_CK EEPROM clock
39 O EE_CS EEPROM active-high Chip Select
42
40 O EE_DO EEPROM data out.
-
132
131
131
130
130
STB#
O(h)
I/O(h) PD[7:0] Parallel data bus
I/O(h)
O
I/O(h)
I/O(h)
I/O(h) MIO[10:3] Multi-purpose I/O pins. Can drive high or low, or assert a PCI
IU(h)
WRITE#
MIO0
NC
MIO1
0
NC
MIO2
I
PME_In
EE_DI EEPROM data in, with internal pull-up.
OXmPCI952
Strobe (SPP mode). Used by peripheral to latch data
currently available on PD[7:0]
Write (EPP mode). Indicates a write cycle when low and a
read cycle when high
external transceivers for 5V signalling; it is high when PD[7:0]
are in output mode and low when they are in input mode.
Multi-purpose I/O 0. Can drive high or low, or assert a PCI
interrupt
Output Driving ‘0’. Can be left as a No-connect.
Multi-purpose I/O 1. Can drive high or low, or assert a PCI
interrupt (as long as LCC[6:5] = “00”).
Output Driving ‘0’ (when LCC[6:5] ≠ ‘00’)
Can be left as a No-Connect.
Multi-purpose I/O 2. When LCC[7] = 0, this pin can drive high
or low, or assert a PCI interrupt.
Input power management event. When LCC[7] is set this
input pin can assert a function 1 PME#.
interrupt
When the serial EEPROM is connected, this pin should be
pulled up using a 1-10k resistor. Pin to be connected to the
external EEPROM’s EE_DO pin
Pin to be connected to the external EEPROM’s EE_DI pin.
DS-0020 Jun 05 Page 13
OXFORD SEMICONDUCTOR LTD.
Miscellaneous pins
Dir1 Name Description
45 I
88 I(h) PCI/miniPCI PCI/miniPCI selection Pin.
Power and ground
17, 22, 31, 43, 57, 65, 69, 72, 73,
74, 75, 76, 83, 84, 85, 86, 87, 97,
110, 118, 154, 158
8, 16, 21, 25, 30, 35, 44, 56, 62,
70, 96, 103, 109, 117, 136, 142,
146, 153, 159
MODE Mode selection Pin
V VDD Power Supply (3.3V)
G GND Power Supply Ground (0V)
0
: Function 0 : Dual UART.
Function 1 : 8-bit Local Bus
1
: Function 0 : Dual UART.
Function 1 : Parallel Port.
Tied Low for PCI mode. Tied High for miniPCI mode.
OXmPCI952
Table 2: Pin Descriptions
DS-0020 Jun 05 Page 14
OXFORD SEMICONDUCTOR LTD.
Note 1: I/O Direction key:
P_I PCI input 3.3v Only
P_O PCI output / PCITristates 3.3v Only
P_I/O PCI bi-directional 3.3v Only
P_OD PCI open drain 3.3v Only
I Input LVTTL level
I(h) Input LVTTL level, 5v tolerant
IU(h) Input with internal pull-up LVTTL level, 5v tolerant
I/O(h) Bi-Directional LVTTL level, 5v tolerant
O Output Standard Output
O(h) Output 5v tolerant (High Voltage BI-Direct in output mode)
OD Open drain Standard Open-drain Output
OD(h) Open drain 5v tolerant (High Voltage BI-Direct in open-drain mode)
NC No connect
G Ground
V 3.3V power
OXmPCI952
DS-0020 Jun 05 Page 15
OXFORD SEMICONDUCTOR LTD.
3 PIN INFORMATION—176-PIN BGA
3.1 Pinouts
Dual UARTs + 8-BIT Local Bus (Mode = 0)
1234567
GND AD19 AD21 AD22 C/BE3# AD26
A
C/BE2# AD18 VDD AD20 VDD IDSEL GND AD29 GND
B
FRAME# AD16
C
TRDY# IRDY# AD17 AD23 AD25 GND PME# INTA# MIO3
D
STOP# PERR#
E
C/BE1# AD15 PAR SERR#
F
VDD AD13
G
GND AD11 AD12 VDD
H
AD9 AD8
J
AD7 GND AD6 C/BE0#
K
VDD GND AD4 AD5
L
AD3 AD0
M
AD2
AD1
EE_CK
EE_DO
VDD Mode0 RI0# DSR0# RTS0# VDD
N
P
R
NC
NC
GND
GND
GND
NC
NC
EE_DI FIFOSEL
NC
NC
DEVSEL#
AD14
AD10
EE_CS
GND
GND
NC
SIN0
DCD0#
AD24 AD27 AD28 AD31 RST#
CTS0#
DTR0#
SOUT0
NC
NC
SOUT1
GND
RTS1# DSR1# DCD1#
22 NC—Do not connect these pins:
C3,D4,P2,M3,N3,M5,M12,N12,N13,P14,B14,D13,A7,B8,D7,C4,N11,L12,N14,P12,P13,R15
8 9 10 11 12 13 14 15
AD30 CLK
NC
DTR1#
CTS1# VDD
XTLI
GND
XTLO
INTB#/
CLKRUN#
RI1#
VDD
UART_Ck
_Out
SIN1
MIO1 MIO4 MIO7 LBRST
MIO0
MIO2
VDD
NC
VDD
GND
LBRST#
MIO5
MIO6
LBA0
LBCS3#
LBCLK
LBA7
LBD2
LBD4
MIO9
VDD VDD VDD
LBA1
NC
LBCS2#
VDD
LBA6
LBD0 LBDOUT
GND
LBD7
VDD MIO10 MIO8
NC
VDD VDD
NC
NC NC
NC
NC
OXmPCI952
LBA3
NC
LBCS0#
LBA2
LBCS1#
GND
LBRD#
GND
VDD
LBWR# LBA5
GND
LBA4
LBD1
LBD3
LBD6
VDD
LBD5
PCI/
miniPCI
NC
VDD
VDD
NC
NC
Dual UARTs + Parallel Port (Mode = 1)
1234567
GND AD19 AD21 AD22 C/BE3# AD26 AD30 CLK
A
C/BE2# AD18 VDD AD20 VDD IDSEL GND AD29 GND
B
FRAME# AD16
C
TRDY# IRDY# AD17 AD23 AD25
D
STOP# PERR#
E
C/BE1# AD15 PAR SERR#
F
VDD AD13
G
GND AD11 AD12 VDD
H
AD9 AD8
J
AD7 GND AD6 C/BE0#
K
VDD GND AD4 AD5 NC
L
AD3 AD0
M
AD2
AD1
EE_CK
EE_DO
VDD Mode0 RI0# DSR0# RTS0# VDD
N
P
R
NC
NC
GND
GND
GND
NC
NC
EE_DI FIFOSEL
NC
NC
DEVSEL#
AD14
AD10
EE_CS
GND
GND
NC
SIN0
DCD0#
AD24 AD27 AD28 AD31 RST#
CTS0#
DTR0#
SOUT0
NC
NC
SOUT1
GND
RTS1# DSR1# DCD1#
31 NC—Do not connect these pins:
C3,D4,P2,M3,N3,M5,M12,N12,N13,P14,B14,D13,A7,B8,D7,C4,N11,L12,N14,P12,B13,P13,R15,B11,E12,F12,E13,F14,B15,
C15,D15
8 9 10 11 12 13 14 15
NC
GND
DTR1#
CTS1# VDD
XTLI
INTB#/
CLKRUN#
PME# INTA#
GND
XTLO
RI1#
VDD
Uart_Ck
_Out
SIN1
MIO1
MIO2
MIO3
VDD
VDD
GND
MIO4
MIO5
NC
MIO6
NC
STB#
PD2
PD4
MIO9
NC
NC
NC NC
NC
VDD VDD VDD
PE
NC
MIO7
NC
BUSY
NC
NC
VDD
AFD#
PD0
PDOUT
GND
PD7
VDD
VDD VDD
NC
ACK#
NC
SLCT
GND
VDD
NC
SLIN#
PD3
PD6
MIO10
NC
NC
ERR#
NC
NC
NC
GND
INIT#
GND
PD1
VDD
PD5
MIO8
PCI/
miniPCI
VDD
VDD
NC
DS-0020 Jun 05 Page 16
OXFORD SEMICONDUCTOR LTD.
3.2 Pin Descriptions
For the actual pinouts of the OXmPCI952 device for this package type, please refer to section 3.1 Pinouts.
PCI / mini-PCI Interface
Mode 0, Mode 1 Dir1 Name Description
C9,A8,B9,C8,C7,A6,D6,C6,
D5,A4,A3,B4,A2,B2,D3,C2,
F2,G4,G2,H3,H2,J4,J1,J2,
K1,K3,L4,L3,M1,N1,P1,M2
A5,B1,F1,K4 P_I C/BE[3:0]# PCI Command/Byte enable
A9 P_I CLK PCI system clock
C1 P_I FRAME# Cycle Frame
E4 P_O DEVSEL# Device Select
D2 P_I IRDY# Initiator ready
D1 P_O TRDY# Target ready
E1 P_O STOP# Target Stop request
F3 P_I/O PAR Parity
F4 P_O SERR# System error
E2 P_I/O PERR# Parity error
B6 P_I IDSEL Initialisation device select
C10 P_I RST# PCI system reset
D10 P_OD INTA# Default PCI Interrupt Line. For Function 0 and Function 1
A10
A10
D9 P_OD PME# Power management event
Serial port pins
Mode 0, Mode 1 Dir1 Name Description
P4 I FIFOSEL FIFO select. For backward compatibility with 16C550,
M7,P6 O(h) SOUT[1:0]
R10,N5 I(h)
P9,P5 I(h) DCD[1:0]# Active-low modem data-carrier-detect input
P_I/O AD[31:0] Multiplexed PCI Address/Data bus
P_OD
P_I/O
I(h)
INTB#
CLKRUN#
IrDA_Out[1:0]
SIN[1:0]
IrDA_In[1:0]
Optional PCI interrupt Line (PCI Mode)
ClockRun# Line (mini-PCI mode)
16C650 and 16C750 devices the UARTs’ FIFO depth is 16
when FIFOSEL is low. The FIFO size is increased to 128
when FIFOSEL is high. The unlatched state of this pin is
readable by software. The FIFO size may also be set to 128
by setting FCR[5] when LCR[7] is set, or by putting the
device into enhanced mode.
UART serial data outputs
UART IrDA data output when MCR[6] of the corresponding
channel is set in enhanced mode
UART serial data inputs
UART IrDA data input when IrDA mode is enabled (see
above)
OXmPCI952
DS-0020 Jun 05 Page 17
OXFORD SEMICONDUCTOR LTD.
Serial port pins
Mode 0, Mode 1 Dir1 Name Description
M8,N6 O(h)
P7,R6 O(h) RTS[1:0]# Active-low modem request-to-send output. If automated
N8,M6 I(h) CTS[1:0]# Active-low modem clear-to-send input. If automated CTS#
P8,R5 I(h)
M10,R4 I(h)
R9 O XTLO Crystal oscillator output
R8 I XTLI Crystal oscillator input up to 20MHz. External clock pin up to
O(h)
O(h)
I(h)
I(h)
DTR[1:0]#
485_En[1:0]
Tx_Clk_Out[1:0]
DSR[1:0]#
Rx_Clk_In[1:0]
RI[1:0]#
Tx_Clk_In[1:0]
OXmPCI952
Active-low modem data-terminal-ready output. If automated
DTR# flow control is enabled, the DTR# pin is asserted and
deasserted if the receiver FIFO reaches or falls below the
programmed thresholds, respectively.
In RS485 half-duplex mode, the DTR# pin may be
programmed to reflect the state of the transmitter empty bit to
automatically control the direction of the RS485 transceiver
buffer (see register ACR[4:3])
Transmitter 1x clock (baud rate generator output). For
isochronous applications, the 1x (or Nx) transmitter clock
may be asserted on the DTR# pins (see register CKS[5:4])
RTS# flow control is enabled, the RTS# pin is deasserted
and reasserted whenever the receiver FIFO reaches or falls
below the programmed thresholds, respectively.
flow control is enabled, upon deassertion of the CTS# pin,
the transmitter will complete the current character and enter
the idle mode until the CTS# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the CTS# pin.
Active-low modem data-set-ready input. If automated DSR#
flow control is enabled, upon deassertion of the DSR# pin,
the transmitter will complete the current character and enter
the idle mode until the DSR# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the DSR# pin
External receiver clock for isochronous applications. The
Rx_Clk_In is selected when CKS[1:0] = ‘01’.
Active-low modem Ring-Indicator input
External transmitter clock. This clock can be used by the
transmitter (and indirectly by the receiver) when CKS[6]=’1’.
60MHz.
DS-0020 Jun 05 Page 18
OXFORD SEMICONDUCTOR LTD.
8-bit local bus
Mode 0 Dir1 Name Description
P10 O UART_Clk_Out Buffered crystal output. This clock can drive external UARTs
A14 O(h) LBRST Local bus active-high reset
B13 O LBRST# Local bus active-low reset
H14 O LBDOUT Local bus data out enable. This pin can be used by external
F12 O LBCLK Buffered PCI clock. Can be enabled / disabled by software
E12,E13,C15,B15 O(h)
F14 O
D15 O
G12,G13,F15,G14,A15,C14,
C13,D12
K13,K14,K15,J12,J14,H12,
H15,H13
Parallel port
Mode 1 Dir1 Name Description
A14 I(h)
D12 I(h) PE Paper Empty. Activated by printer when it runs out of paper.
C13 I(h)
G14 OD(h)
C14 I(h) SLCT Peripheral selected. Asserted by peripheral when selected.
A15 I(h) ERR# Error. Held low by the peripheral during an error condition.
F15 OD(h)
G13 OD(h)
connected to the local bus. Can be enabled / disabled by
software.
transceivers; it is high when LBD[7:0] are in output mode and
low when they are in input mode.
LBCS[3:0]#
O(h)
O(h) LBA[7:0] Local bus address signals
I/O(h) LBD[7:0] Local bus data signals
O(h)
O(h)
O(h)
O
Z
I(h)
I(h)
LBDS[3:0]#
LBWR#
LBRDWR#
LBRD#
Hi-Z
ACK#
INTR#
BUSY
WAIT#
SLIN#
ADDRSTB#
INIT#
INIT#
AFD#
DATASTB#
Local bus active-low Chip-Select (Intel mode)
Local bus active-low Data-Strobe (Motorola mode)
Local Bus active-low write-strobe (Intel mode)
Local Bus Read-not-Write control (Motorola mode)
Local Bus active-low read-strobe (Intel mode)
Permanent high impedance (Motorola mode)
Acknowledge (SPP mode). ACK# is asserted (low) by the
peripheral to indicate that a successful data transfer has
taken place.
Identical function to ACK# (EPP mode).
Busy (SPP mode). BUSY is asserted (high) by the peripheral
when it is not ready to accept data
Wait (EPP mode). Handshake signal for interlocked IEEE
1284 compliant EPP cycles.
Select (SPP mode). Asserted by host to select the peripheral
Address strobe (EPP mode) provides address read and write
strobe
Initialise (SPP mode). Commands the peripheral to initialise.
Initialise (EPP mode). Identical function to SPP mode.
Auto Feed (SPP mode, open-drain)
Data strobe (EPP mode) provides data read and write strobe
OXmPCI952
DS-0020 Jun 05 Page 19
OXFORD SEMICONDUCTOR LTD.
Parallel port
Mode 1 Dir1 Name Description
G12 OD(h)
K13,K14,K15,J12,J14,H12,
H15,H13
H14 O PDOUT Parallel Port data out enable. This pin should be used by
Multi-purpose & External interrupt pins
Dir1 Name Description
Mode 0 Mode 1
B11
-
A11
A11
C11
C11
L14,K12,L15,A13,C12,B12,
A12,D11
EEPROM pins
Mode 0, Mode 1 Dir1 Name Description
R1 O EE_CK EEPROM clock
M4 O EE_CS EEPROM active-high Chip Select
P3
N2 O EE_DO EEPROM data out.
-
B11
A11
A11
C11
C11
STB#
O(h)
I/O(h) PD[7:0] Parallel data bus
I/O(h)
O
I/O(h)
I/O(h)
I/O(h) MIO[10:3] Multi-purpose I/O pins. Can drive high or low, or assert a PCI
IU(h)
WRITE#
MIO0
NC
MIO1
0
NC
MIO2
I
PME_In
EE_DI EEPROM data in, with internal pull-up.
OXmPCI952
Strobe (SPP mode). Used by peripheral to latch data
currently available on PD[7:0]
Write (EPP mode). Indicates a write cycle when low and a
read cycle when high
external transceivers for 5V signalling; it is high when PD[7:0]
are in output mode and low when they are in input mode.
Multi-purpose I/O 0. Can drive high or low, or assert a PCI
interrupt
Output Driving ‘0’. Can be left as a No-connect.
Multi-purpose I/O 1. Can drive high or low, or assert a PCI
interrupt (as long as LCC[6:5] = “00”).
Output Driving ‘0’ (when LCC[6:5] ≠ ‘00’)
Can be left as a No-Connect.
Multi-purpose I/O 2. When LCC[7] = 0, this pin can drive high
or low, or assert a PCI interrupt.
Input power management event. When LCC[7] is set this
input pin can assert a function 1 PME#.
interrupt
When the serial EEPROM is connected, this pin should be
pulled up using a 1-10k resistor. Pin to be connected to the
external EEPROM’s EE_DO pin
Pin to be connected to the external EEPROM’s EE_DI pin.
DS-0020 Jun 05 Page 20
OXFORD SEMICONDUCTOR LTD.
Miscellaneous pins
Dir1 Name Description
R3 I
M15 I(h) PCI/miniPCI PCI/miniPCI selection Pin.
Power and ground
G1,H4,L1,R2,R7,N9,N10,M11,R12,
P11,R13,R14,M13,P15,N15,M14,L
13,J15,F13,E14,B5,B3
H1,K2,L2,N4,R11,G15,E15,D14,
B10,B7,A1
MODE Mode selection Pin
V VDD Power Supply (3.3V)
G GND Power Supply Ground (0V)
0
: Function 0 : Dual UART.
Function 1 : 8-bit Local Bus
1
: Function 0 : Dual UART.
Function 1 : Parallel Port.
Tied Low for PCI mode. Tied High for miniPCI mode.
OXmPCI952
Table 3: Pin Descriptions
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OXFORD SEMICONDUCTOR LTD.
Note 1: I/O Direction key:
P_I PCI input 3.3v Only
P_O PCI output / PCITristates 3.3v Only
P_I/O PCI bi-directional 3.3v Only
P_OD PCI open drain 3.3v Only
I Input LVTTL level
I(h) Input LVTTL level, 5v tolerant
IU(h) Input with internal pull-up LVTTL level, 5v tolerant
I/O(h) Bi-Directional LVTTL level, 5v tolerant
O Output Standard Output
O(h) Output 5v tolerant (High Voltage BI-Direct in output mode)
OD Open drain Standard Open-drain Output
OD(h) Open drain 5v tolerant (High Voltage BI-Direct in open-drain mode)
NC No connect
G Ground
V 3.3V power
OXmPCI952
4 CONFIGURATION & OPERATION
The OXmPCI952 is a multi-function, target-only PCI
device, compliant with the PCI Local Bus Specification
Revision 3.0, and PCI Power Management Specification
Revision 1.1.
The OXmPCI952 affords maximum configuration flexibility
by treating the internal UART’s, the Local Bus and the
Parallel Port as separate logical functions. Each function
has its own configuration space and is therefore
recognised and configured by the PCI BIOS separately.
The functions used are configured by the Mode Selection
Pin (pin 45).
The OXmPCI952 is configured by system start-up software
during the bootstrap process that follows bus reset. The
system scans the bus and reads the vendor and device
identification codes from any devices it finds. It then loads
device-driver software according to this information and
configures the I/O, memory and interrupt resources. Device
drivers can then access the functions at the assigned
addresses in the usual fashion, with the improved data
throughput provided by PCI.
Each function operates as though it was a separate device.
However there are a set of Local Configuration Registers
that can be used to enable signals and interrupts, configure
timings, and improve the efficiency of multi-port drivers.
This architecture enables separate drivers to be installed
for each function. Generic port drivers can be hooked to
use the functions individually, or more efficient multi-port
drivers can hook both functions, accessing the Local
Configuration Registers from either.
All registers default after reset to suitable values for typical
applications such a 2/6 port serial, or combo 2-port serial/1port parallel add-in cards. However, all identification,
control and timing registers can be redefined using the
external serial EEPROM.
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OXFORD SEMICONDUCTOR LTD.
5 PCI TARGET CONTROLLER
OXmPCI952
5.1 Operation
The OXmPCI952 responds to the following PCI
transactions:-
• Configuration access: The OXmPCI952 responds to
type 0 configuration reads and writes if the IDSEL
signal is asserted and the bus address is selecting the
configuration registers for function 0 or 1. The device
will respond to the configuration transaction by
asserting DEVSEL#. Data transfer then follows. Any
other configuration transaction will be ignored by the
OXmPCI952.
• IO reads/writes: The address is compared with the
addresses reserved in the I/O Base Address Registers
(BARs). If the address falls within one of the assigned
ranges, the device will respond to the IO transaction
by asserting DEVSEL#. Data transfer follows this
address phase. For the UARTs and 8-bit Local Bus
controller, only byte accesses are possible. For IO
accesses to these regions, the controller compares
AD[1:0] with the byte-enable signals as defined in the
PCI specification. The access is always completed;
however if the correct BE signal is not present the
transaction will have no effect.
• Memory reads/writes: These are treated in the same
way as I/O transactions, except that the memory
ranges are used. Memory access to single-byte
regions is always expanded to DWORDs in the
OXmPCI952. In other words, OXmPCI952 reserves a
DWORD per byte in single-byte regions. The device
allows the user to define the active byte lane using
LCC[4:3] so that in Big-Endian systems the hardware
can swap the byte lane automatically. For Memory
mapped access in single-byte regions, the
OXmPCI952 compares the asserted byte-enable with
the selected byte-lane in LCC[4:3] and completes the
operation if a match occurs, otherwise the access will
complete normally on the PCI bus, but it will have no
effect on either the internal UARTs or the local bus
controller.
• All other cycles (64-bit, special cycles, reserved
encoding etc.) are ignored.
The OXmPCI952 will complete all transactions as
disconnect-with-data, i.e. the device will assert the STOP#
signal alongside TRDY#, to ensure that the Bus Master
does not continue with a burst access. The exception to
this is Retry, which will be signalled in response to any
access while the OXmPCI952 is reading from the serial
EEPROM.
The OXmPCI952 performs medium-speed address
decoding as defined by the PCI specification. It asserts the
DEVSEL# bus signal two clocks after FRAME# is first
sampled low on all bus transaction frames which address
the chip. The internal UARTs are accessed with zero wait
states inserted. Fast back-to-back transactions are
supported by the OXmPCI952 as a target, so a bus master
can perform faster sequences of write transactions to the
UARTs or local bus when an inter-frame turn-around cycle
is not required.
The device supports any combination of byte-enables to
the PCI Configuration Registers and the Local
Configuration Registers. If a byte-enable is not asserted,
that byte is unaffected by a write operation and undefined
data is returned upon a read.
The OXmPCI952 performs parity generation and checking
on all PCI bus transactions as defined by the standard.
Note this is entirely unrelated to serial data parity which is
handled within the UART functional modules themselves. If
a parity error occurs during the PCI bus address phase, the
device will report the error in the standard way by asserting
the SERR# bus signal. However if that address/command
combination is decoded as a valid access, it will still
complete the transaction as though the parity check was
correct.
The OXmPCI952 does not support any kind of caching or
data buffering in addition to that already provided within the
UARTs by the transmit and receive data FIFOs. In general,
registers in the UARTs and on the local bus can not be prefetched because there may be side-effects on read.
5.2 Configuration space
The OXmPCI952 is a dual-function device, where each
logical function has its own configuration space. All
required fields in the standard header are implemented,
plus the Power Management Extended Capability register
set. The format of the configuration space is shown in the
following tables.
In general, writes to any registers that are not implemented
are ignored, and all reads from unimplemented registers
return 0.
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OXFORD SEMICONDUCTOR LTD.
5.2.1 PCI Configuration Space Register map
Predefined PCI Region
31 16 15 0
Device ID Vendor ID 00h
Status Command 04h
BIST Header Type Reserved Reserved 0Ch
Subsystem ID Subsystem Vendor ID 2Ch
Reserved Reserved Interrupt Pin Interrupt Line 3Ch
Configuration Register Description Offset
Class Code Revision ID 08h
Base Address Register 0 (BAR 0) 10h
Base Address Register 1 (BAR 1) 14h
Base Address Register 2 (BAR 2) 18h
Base Address Register 3 (BAR 3) 1Ch
Base Address Register 4 (BAR 4) 20h
Base Address Register 5 (BAR 5) 24h
Reserved 28h
Reserved 30h
Reserved Cap_Ptr 34h
Reserved 38h
OXmPCI952
Address
User Defined Region
Power Management Capabilities (PMC) Next Ptr Cap_ID 40h
Data Reserved PMC Control/Status Register (PMCSR) 44h
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OXFORD SEMICONDUCTOR LTD.
OXmPCI952
PCI Configuration Space Default Values
Following use of the external eeprom. See “Minimum Programming Requirements”. Section 10.1.7
Register Name Mode 0 Mode 1
Function 0 Function 1 Function 0 Function 1 EEPROM PCI
DUAL UART
Vendor ID 0x1415 W R
Device ID 0x9505 0x9511 0x9505 0x9513 W R
Command 0x0000 - R/W
Status 0x0290 W(Bit 4) R/W
Revision ID 0x00 - R
Class Code 0x070006 0x068000 0x070006 0x070101 W R
Header 0x80 - R
BAR 0 0x00000001 0x00000001 0x00000001 0x00000001 - R
BAR 1 0x00000001 0x00000000 0x00000001 0x00000001 - R
BAR 2 Unused 0x00000001 Unused 0x00000001 - R
BAR 3 Unused 0x00000000 Unused 0x00000000 - R
BAR 4 0x00000001 Unused 0x00000001 Unused - R
BAR 5 0x00000000 Unused 0x00000000 Unused - R
Subsystem
Vendor ID
Subsystem ID 0x0000 W R
Cap. Ptr 0x40 - R
Interrupt Line 0x00 - R
Interrupt Pin 0x01 W R
Cap ID 0x01 - R
Next Ptr 0x00 - R
PM Capabilities 0x6C02 (PCI mode)
PMC
Control/Status
Register
PM Data Register 0x00 (Implemented) W R
8-Bit LOCAL BUS
0x1415 W R
0xEC02 (MiniPCI mode)
0x0000 W
DUAL UART PARALLEL
PORT
W R
(Data
Scale)
R/W
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OXFORD SEMICONDUCTOR LTD.
OXmPCI952
5.3 Accessing logical functions
Access to the two UARTs, the Local Bus and the Parallel Port is achieved via standard I/O and Memory mapping, at addresses
defined by the Base Address Registers (BARs) in the PCI configuration space. The BARs are configured by the system to
allocate blocks of I/O and Memory space to the logical functions, according to the size required by the funct ion. The addresses
allocated can then be used to access the functions. The mapping of these BARs, which is dependent upon the mode of the
device, is shown by the following tables.
BAR Function 0
Dual UARTs (Mode 0, Mode 1)
0 Internal UART0 (I/O Mapped)
1 Internal UART1 (I/O Mapped)
2 Unused
3 Unused
4 Local configuration registers (I/O mapped)
5 Internal UARTs/ Local configuration registers (Memory mapped)
BAR Function 1
Local bus (Mode 0) Parallel port (Mode 1)
0 Local bus (I/O mapped) Parallel port base registers
1 Local bus (Memory mapped) Parallel port extended registers
2 Local configuration registers (I/O mapped)
3 Local configuration registers (Memory mapped)
4 Unused
5 Unused
5.3.1 PCI access to internal UARTs
IO and Memory Space
BAR0 and BAR1 are used to address the two UARTs
individually in I/O space, and BAR5 is used to address the
UARTs in Memory Space. The function reserves an 8-byte
block of I/O space for BAR0 and BAR1, and a 4K byte
block of memory space for BAR5. Once the I/O access and
the Memory access enable bits in the Command register
(configuration space) are set, the UARTs can accessed
according to the following tables.
UART
Address
(hex) UART0
000 00 00
001 01 01
002 02 02
003 03 03
004 04 04
005 05 05
006 06 06
007 07 07
PCI Offset from UARTs Base Address
for Function0 in IO space (hex)
UART1
(BAR0)
(BAR1)
UART
Address
000 00 20
001 04 24
002 08 28
003 0C 2C
004 10 30
005 14 34
006 18 38
007 1C 3C
Note that the local registers in memory space occupy the same Base
Address Register (BAR5) as the internal Dual UARTs in Memory Space.
Bit 7 selects the region to be accessed. Access to addresses 00h to 3Ch
will be directed to the internal UARTs, and access to addresses 80h to
FCh will be directed to the local registers. When accessing the local
registers via BAR5 (bit 7 set) Fields 6:2 Define the BYTE offset for the
local registers. Eg 00000b for the LCC register, 00100b for the MIC
register)
In both cases, fields 1:0 are not utilised and are to be set to zeros. This is
because a DWORD is used to hold a single Byte, in Memory Space
PCI Offset from Base Address 5 for
Function0 in Memory space (hex)
UART0 UART1
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OXFORD SEMICONDUCTOR LTD.
5.3.2 PCI access to 8-bit local bus
When the local bus is enabled (mode = 0), access to the
bus works in a similar fashion to the internal UARTs. The
function reserves a block of I/O space and a block of
memory space. The I/O block size is user definable in the
range of 4 to 256 bytes, and the memory range is fixed at
4K bytes.
I/O space
In order to minimise the usage of IO space, the block size
for BAR0 of Function1 is user definable in the range of 4 to
256 bytes. Having assigned the address range, the user
can define two adjacent address bits to decode up to four
chip selects internally. This facility allows glueless
implementation of the local bus connecting to four external
peripheral chips. The address range and the lower address
bit for chip-select decoding (Lower-Address-CS-Decode)
are defined in the Local Bus Configuration register (see
LT2 [26:20] in section 5.4).
The 8-bit Local Bus has eight address lines (LBA[7:0]) that
correspond to the maximum I/O address space. If the
maximum allowable block size is allocated to the I/O space
(i.e. 256 bytes), then as access in I/O space is byte
aligned, LBA[7:0] equal PCI AD[7:0] respectively. When the
user selects an address range which is less than 256
bytes, the corresponding upper address lines will be set to
logic zero.
The region can be divided into four chip-select regions
when the user selects the second uppermost non-zero
address bit for chip-select decoding. For example if 32bytes of I/O space are reserved, the local bus address lines
A[4:0] are active and the remaining address lines are set to
zero. To generate four chip-selects the user should select
A3 as the Lower-Address-CS-Decode. In this case A[4:3]
will be used internally to decode chip-selects, asserting
LBCS0# when the address offset is 00-07h, LBCS1# when
the offset is 08-0Fh, LBCS2# when the offset is 10-17h,
and LBCS3# when the offset is 18-1Fh.
The region can be divided into two chip-select regions by
selecting the uppermost address bit to decode chip selects.
In the above example, the user can select A4 as the
Lower-Address-CS-Decode, thus using A[5:4] internally to
decode chip selects. As in this example LBA5 is always
zero, only chip-select lines LBCS0# and LBCS1# will be
decoded into, asserting LBCS0# when address offset is 000Fh and LBCS1# when offset is 10-1Fh.
The region can be allocated to a single chip-select region
by assigning an address bit beyond the selected range to
Lower-Address-CS-Decode (but not above A8). In the
OXmPCI952
above example, if the user selects A5 as the LowerAddress-CS-Decode, A[6:5] will be used to internally
decode chip-selects. As in this example LBA[7:5] are
always zero, only the chip select line LBCS0# may be
selected. In this case address offset 00-1Fh asserts
LBCS0# and the other chip-select lines remain inactive
permanently.
Memory Space:
The memory base address registers have an allocated
fixed size of 4K bytes in the address space. Since the
Local Bus has 8 address lines and the OXmPCI952 only
implements DWORD aligned accesses in memory space,
the 256 bytes of addressable space per chip select is
expanded to 1K. Unlike an I/O access, for a memory
access the upper address lines are always active and the
internal chip-select decoding logic ignores the user setting
for Lower-Address-CS-Decode (LT2[26:23]) and uses PCI
AD[11:10] to decode into 4 chip-select regions. When the
Local Bus is accessed in memory space, A[9:2] are
asserted on LBA[7:0]. The chip-select regions are defined
below.
Local Bus
Chip-Select
(Data-Strobe)
LBCS0# (LBDS0#) 000h 3FCh
LBCS1# (LBDS1#) 400h 7FCh
LBCS2# (LBDS2#) 800h BFCh
LBCS3# (LBDS3#) C00h FFCh
Table 4: PCI address map for local bus (memory)
Note: The description given for I/O and memory accesses is for an Inteltype configuration for the Local Bus. For Motorola-type configuration, the
chip select pins are redefined as data strobe pins. In this mode the Local
Bus offers up to 8 address lines and four data-strobe pins.
PCI Offset from BAR 1 in
Function1 (Memory space)
Lower Address Upper Limit
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OXFORD SEMICONDUCTOR LTD.
5.3.3 PCI access to parallel port
When the parallel port is enabled (mode = 1), access to the
Parallel Port works via BAR definitions as usual, except
that there are two I/O BARs corresponding to the two sets
of registers defined to operate an IEEE1284 EPP/ECP and
bi-directional Parallel Port.
The user can change the I/O space block size of BAR0 by
over-writing the default values in LT2[25:20] using the
serial EEPROM (see section 5.4). For example the user
can reduce the allocated space for BAR0 to 4 bytes by
setting LT2[22:20] to ‘001’. The I/O block size allocated to
BAR1 is fixed at 8 Bytes.
Legacy parallel ports expect the upper register set to be
mapped 0x400 above the base block, therefore if the BARs
are fixed with this relationship, generic parallel port drivers
can be used to operate the device in all modes.
Example: BAR0 = 0x00000379 (8 bytes at address 0x378)
BAR1 = 0x00000779 (8 bytes at address 0x778)
If this relationship is not used, custom drivers will be
needed.
OXmPCI952
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OXFORD SEMICONDUCTOR LTD.
OXmPCI952
5.4 Accessing Local configuration registers
The local configuration registers are a set of device specific registers which can be accessed from either function. The local
configuration registers exist behind BAR4 and BAR5 for function 0, and behind BAR2 and BAR3 for function 1. For I/O
transactions, access is limited to byte reads/writes. For Memory Transactions, accesses can be Word or Dword accesses,
however on little-endian systems such as Intel 80x86 the byte order will be reversed.
The following table lists the definitions of the local registers, with the offsets (from the Base Address Register) defined for each
local register.
5.4.1 Local Configuration and Control register ‘LCC’ (Offset 0x00)
This register defines control of ancillary functions such as Power Management, external clock reference signals and the serial
EEPROM. The individual bits are described below.
Bits Description Read/Write Reset
0 Mode Status. This bit returns the state of the Mode pin. - R X
1 Reserved. - R 0
2 Enable UART clock output. When this bit is set, a buffered version of
the UART clock is output on the pin “UART_Clk_Out”. When this bit is
low, the UART_Clk_Out is permanently low.
4:3 Endian Byte-Lane Select for memory access to 8-bit peripherals.
00 = Select Data[7:0] 10 = Select Data[23:16]
01 = Select Data[15:8] 11 = Select Data[31:24]
Memory access to OXmPCI952 is always DWORD aligned. When
accessing 8-bit regions like the internal UARTs, the 8-bit Local Bus and
the parallel port, this option selects the active byte lane. As both PCI and
PC architectures are little endian, the default value will be used by
systems, however, some non-PC architectures may need to select the
byte lane.
6:5 Power-down filter time. These bits define a value of an internal filter
time for a power-down interrupt request in power management circuitry
in Function0. Once Function0 is ready to go into power down mode,
OXmPCI952 will wait for the specified filter time and if Function0 is still in
power-down request mode, it can assert a PCI interrupt (see section
5.6).
00 = power-down request disabled
01 = 4 seconds
7 Function1 MIO2_PME Enable. A value of ‘1’ enables MIO2 pin to set
the PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO2 from setting the PME_Status bit
(see section 5.6).
23:8 Reserved. These bits are used for test purposes. The device driver must
write zeros to these bits.
24 EEPROM Clock. For PCI read or write to the EEPROM, toggle this bit to
generate an EEPROM clock (EE_CK pin).
25 EEPROM Chip Select. When 1 the EEPROM chip-select pin EE_CS is
activated (high). When 0 EE_CS is de-active (low).
26 EEPROM Data Out. For writes to the EEPROM, this output bit is the
input-data for the EEPROM. This bit is output on EE_DO and clocked
into the EEPROM by EE_CK.
27 EEPROM Data In. For reads from the EEPROM, this input bit is the
output-data of the EEPROM connected to EE_DI pin.
28 EEPROM Valid. A 1 indicates that a valid EEPROM program is present - R X
10 = 129 seconds
11 = 518 seconds
EEPROM
W RW 0
W RW 00
W RW 00
W RW 0
- R 0000h
- W 0
- W 0
- W 0
- R X
PCI
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OXFORD SEMICONDUCTOR LTD.
Bits Description Read/Write Reset
29 Reload configuration from EEPRO M. Writing a 1 to this bit re-loads the
configuration from EEPROM. This bit is self-clearing after EEPROM read
30 EEPROM Overrun Indication (when set).
In conjunction with Bit 28 (Valid EEPROM) this bit indicates whether a
successful eeprom download had taken place. Successful download will
have EEPROM_VALID = 1 and EEPROM OVERRUN = 0.
31 Reserved. - R 1
EEPROM
- W 0
- R 0
OXmPCI952
PCI
5.4.2 Multi-purpose I/O Configuration register ‘MIC’ (Offset 0x04)
This register configures the operation of the multi-purpose I/O pins ‘MIO[10:0], as well as providing further device controls and
status, as follows.
Bits Description Read/Write Reset
1:0
3:2 MIO1 Configuration Register (When LCC[6:5] = ‘00’).
5:4 MIO2 Configuration Register (When LCC[7]=’0’).
7:6 MIO3 Configuration Register.
9:8 MIO4 Configuration Register.
MIO0 Configuration Register (When Device Mode ≠ ‘001’/’101’).
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
When Parallel Port is enabled, (Device Mode = ‘001’/’101’), MIO[0] pin is
unused and will remain in forcing output mode.
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
When power-down mode in Function 0 is enabled (LCC[6:5] ≠‘00’), MIO1
pin is unused and will remain in forcing output mode.
00 -> MIO2 is a non-inverting input pin
01 -> MIO2 is an inverting input pin
10 -> MIO2 is output pin driving ‘0’
11 -> MIO2 is output pin driving ‘1’
When LCC[7] is set, the MIO2 pin is re-defined to a PME_Input. Its
polarity will be controlled by MIC[4]. It sets the sticky PME_Status bit in
Function1.
00 -> MIO3 is a non-inverting input pin
01 -> MIO3 is an inverting input pin
10 -> MIO3 is an output pin driving ‘0’
11 -> MIO3 is an output pin driving ‘1’
00 -> MIO4 is a non-inverting input pin
01 -> MIO4 is an inverting input pin
10 -> MIO4 is an output pin driving ‘0’
11 -> MIO4 is an output pin driving ‘1’
EEPROM
W RW 00
W RW 00
W RW 00
W RW 00
W RW 00
PCI
DS-0020 Jun 05 Page 30
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