OXFORD OX16C950-TQC60-B, OX16C950-PCC60-B Datasheet

F

EATURES

OX16C950 rev B

High Performance UART

with 128 byte FIFOs

• Single full-duplex asynchronous channel

•

128-byte deep transmitter / receiver FIFO

• Fully software compatible with industry standard
16C550 type UARTs

•

Pin compatible with TL16C550B/C, ST16C650 and
TL16C750

•

IBM PC/AT compatible

• Baud rates up to 15 Mbps in normal mode and
60Mbps in external 1x clock mode

•

Readable FIFO levels

•

Flexible clock prescaler from 1 to 31.875

•

Isochronous mode using external 1x baud rate clock
up to 60Mbps

•

9-bit data framing as well as 5,6,7 and 8

• Detection of bad data in the receiver FIFO

•

Automated in-band flow control using programmable

Xon/Xoff characters

• Transmitter and receiver can be disabled

R

EV

B E

NHANCEMENTS

• Automated out-of-band flow control using CTS# / RTS#
and DSR# / DTR#

•

Readable in-band and out-of-band flow control status

• Programmable special character detection

•

Arbitrary trigger levels for receiver and transmitter FIFO

interrupts and automatic in-band and out-of-band flow
control

•

Transmitter idle interrupt (shift register and FIFO both

empty)

•

Optional Infra-red (IrDA) receiver and transmitter

operation

• RS-485 buffer enable signals

•

Software channel reset

• Four byte device ID

•

Sleep mode (low operating current)

• System clock up to 60 MHz (at 5V), 50 MHz at 3.3V

•

44 PLCC and 48 TQFP packages

• 5 volts operation (PLCC), 3.3/ 5V operation TQFP

The OX16C950B is an enhanced, fully backward-compatible revision of the OX16C950 rev A. The chief enhancements are as
follows –

•

All known errata fixed

• Enhanced features first offered in OX16PCI954 added – these include controls for sleep-mode sensitivity, ability to
read FCR and Good Data Status

•

3V operation possible with 48 pin TQFP

•

Enhanced isochronous clocking options (optional inversions)

• Enhanced system clock selection options (use of CLKSEL as a clock input)

•

Readable TxRdy, RxRdy status and forcing TxRdy or RxRdy inactive

Hereafter OX16C950 rev B is simply referred to as OX16C950.

Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK OX16C950 rev B Datasheet R1.2 – May 2001
Tel: [phone] Fax: [phone] Part No. OX16C950-PCC60-B



Oxford Semiconductor 2001

ESCRIPTION

D

The OX16C950 is a single-channel ultra-high performance
UART offering data rates up to 15Mbps and 128-deep
transmitter and receiver FIFOs. Deep FIFOs reduce CPU
overhead and allow utilisation of higher data rates.

It is software compatible with the widely used industry­standard 16C550 type devices and compatibles, as well as
other OX16C95x family devices. It is pin-compatible with
the TL16C550, ST16C650 devices.

In addition to increased performance and FIFO size, the
OX16C950 also provides enhanced features including
improved flow control. Automated software flow control
using Xon/Xoff and automated hardware flow control using
CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow
control and interrupt thresholds are fully programmable and
readable, enabling programmers to fine-tune the

performance of their system. FIFO levels are readable to
facilitate fast driver applications.

The addition of software reset enables recovery from
unforeseen error condition allowing drivers to restart
gracefully. The OX16C950 supports 9-bit data frames
used in multi-drop industrial protocols. It also offers multiple
external clock options for isochronous applications, e.g.
ISDN, xDSL.

The OX16C950 is ideally suited to PC applications, such
as high-speed COM port add-in cards which enable PC
users to take advantage of the maximum performance of
analogue modems or ISDN terminal adapters. It is also
suitable for any equipment requiring high speed
RS232/RS422/RS485 interfaces. Fabricated in 0.6µm
process, OX16C950 also has a low operating current and
sleep mode for battery powered applications.

Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK OX16C950 rev B Datasheet R1.2 – May 2001
Tel: [phone] Fax: [phone] Part No. OX16C950-PCC60-B



Oxford Semiconductor 2001

OXFORD SEMICONDUCTOR LTD.

ONTENTS

C

OX16C950 rev B

FEATURES....................................................................................................................................................................................... 1

REV B ENHANCEMENTS................................................................................................................................................................ 1

DESCRIPTION ................................................................................................................................................................................. 2

CONTENTS ...................................................................................................................................................................................... 3

1 PERFORMANCE COMPARISON .............................................................................................................................................. 5

2 BLOCK DIAGRAM ..................................................................................................................................................................... 6

3 PIN INFORMATION.................................................................................................................................................................... 7

4 PIN DESCRIPTIONS .................................................................................................................................................................. 8

4.1 F

5 MODE SELECTION.................................................................................................................................................................. 13

5.1 450 M

5.2 550 MODE........................................................................................................................................................................... 13

5.3 E

5.4 750 M

5.5 650 M

5.6 950 M

6 REGISTER DESCRIPTION TABLES....................................................................................................................................... 15

7 RESET CONFIGURATION....................................................................................................................................................... 19

7.1 H

7.2 S

8 TRANSMITTER & RECEIVER FIFOS...................................................................................................................................... 20

8.1 FIFO C

9 LINE CONTROL & STATUS .................................................................................................................................................... 21

9.1 F

9.2 LINE CONTROL REGISTER ‘LCR’........................................................................................................................................... 21

9.3 L

10 INTERRUPTS & SLEEP MODE............................................................................................................................................... 23

10.1 INTERRUPT ENABLE REGISTER ‘IER’ ..................................................................................................................................... 23

10.2 I

10.3 I

10.4 S

11 MODEM INTERFACE............................................................................................................................................................... 25

11.1 M

11.2 MODEM STATUS REGISTER ‘MSR’........................................................................................................................................ 26

12 OTHER STANDARD REGISTERS .......................................................................................................................................... 27

12.1 DIVISOR LATCH REGISTERS ‘DLL & DLM’............................................................................................................................. 27

12.2 S

13 AUTOMATIC FLOW CONTROL .............................................................................................................................................. 28

13.1 ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................................ 28

13.2 S

13.3 A

13.4 A

14 BAUD RATE GENERATION.................................................................................................................................................... 30

14.1 G

14.2 CLOCK PRESCALER REGISTER ‘CPR’.................................................................................................................................... 31

14.3 T

14.4 I

14.5 TTL C

URTHER PIN INFORMATION

ODE

........................................................................................................................................................................... 13

XTENDED

ODE
ODE
ODE

ARDWARE RESET

OFTWARE RESET

ONTROL REGISTER

ALSE START BIT DETECTION

INE STATUS REGISTER

NTERRUPT STATUS REGISTER
NTERRUPT DESCRIPTION

LEEP MODE

ODEM CONTROL REGISTER

CRATCH PAD REGISTER

PECIAL CHARACTER DETECTION
UTOMATIC IN-BAND FLOW CONTROL
UTOMATIC OUT-OF-BAND FLOW CONTROL

ENERAL OPERATION

IMES CLOCK REGISTER

NPUT CLOCK OPTIONS

LOCK MODULE

ODE

550 M

........................................................................................................................................................................... 13

........................................................................................................................................................................... 13

........................................................................................................................................................................... 14

............................................................................................................................................................... 19

............................................................................................................................................................... 19

....................................................................................................................................................................... 25

................................................................................................................................................. 11

.......................................................................................................................................................... 13

‘FCR’ ......................................................................................................................................... 20

............................................................................................................................................... 21

‘LSR’.............................................................................................................................................. 22

‘ISR’ ..................................................................................................................................... 24

..................................................................................................................................................... 24

‘MCR’ ..................................................................................................................................... 25

‘SPR’ ........................................................................................................................................... 27

......................................................................................................................................... 29

................................................................................................................................... 29

........................................................................................................................... 29

.......................................................................................................................................................... 30

‘TCR’............................................................................................................................................. 31

........................................................................................................................................................ 33

........................................................................................................................................................... 33

Data Sheet Revision 1.2 Page 3

OXFORD SEMICONDUCTOR LTD.

OX16C950 rev B

14.6 E

14.7 C

15 ADDITIONAL FEATURES ....................................................................................................................................................... 34

15.1 A

15.2 FIFO F

15.3 A

15.4 TRANSMITTER TRIGGER LEVEL ‘TTL’..................................................................................................................................... 36

15.5 R

15.6 F

15.7 D

15.8 CLOCK SELECT REGISTER ‘CKS’ .......................................................................................................................................... 37

15.9 N

15.10 M

15.11 R

15.12 G

15.13 DMA S

15.14 P

15.15 C

16 OPERATING CONDITIONS ..................................................................................................................................................... 40

17 DC ELECTRICAL CHARACTERISTICS.................................................................................................................................. 40

17.1 5V O

17.2 3V O

18 AC ELECTRICAL CHARACTERISTICS.................................................................................................................................. 42

18.1 5V O

18.2 3V O

19 TIMING WAVEFORMS............................................................................................................................................................. 44

20 PACKAGE INFORMATION...................................................................................................................................................... 46

21 ORDERING INFORMATION .................................................................................................................................................... 47

NOTES............................................................................................................................................................................................ 48

CONTACT DETAILS...................................................................................................................................................................... 49

XTERNAL 1X CLOCK MODE

RYSTAL OSCILLATOR CIRCUIT

DDITIONAL STATUS REGISTER

ILL LEVELS

DDITIONAL CONTROL REGISTER

ECEIVER INTERRUPT

LOW CONTROL LEVELS

EVICE IDENTIFICATION REGISTERS

INE-BIT MODE REGISTER

ODEM DISABLE MASK
EADABLE
OOD-DATA STATUS REGISTER

ORT INDEX REGISTER
LOCK ALTERATION REGISTER

PERATION
PERATION

PERATION
PERATION

‘TFL & RFL’............................................................................................................................................ 34

FCR ‘RFC’ .................................................................................................................................................... 38

TATUS REGISTER

.................................................................................................................................................................... 40

.................................................................................................................................................................... 41

.................................................................................................................................................................... 42

.................................................................................................................................................................... 43

................................................................................................................................................. 33

............................................................................................................................................ 33

‘ASR’................................................................................................................................... 34

‘ACR’................................................................................................................................ 34

RIGGER LEVEL

. T

‘FCL & FCH’.................................................................................................................................. 36

‘NMR’ ......................................................................................................................................... 37

‘MDM’......................................................................................................................................... 38

‘DMS’ ....................................................................................................................................... 39

‘PIX’............................................................................................................................................ 39

‘RTL’ ....................................................................................................................... 36

...................................................................................................................................... 36

‘GDS’ .............................................................................................................................. 39

‘CKA’............................................................................................................................... 39

Data Sheet Revision 1.2 Page 4

OXFORD SEMICONDUCTOR LTD.

ERFORMANCE COMPARISON

P

1

Feature OX16C950 16C450 16C550 16C650 16C750

External 1x baud rate clock Yes No No No No

Max baud rate in normal mode 15 Mbps 115 kbps 115 kbps 1.5 Mbps 1 Mbps

Max baud rate in 1x clock mode 60 Mbps n/a n/a n/a n/a

FIFO depth 128 1 16 32 64

Sleep mode Yes No No Yes Yes

Auto Xon/Xoff flow Yes No No Yes No
Auto CTS#/RTS# flow Yes No No Yes Yes
Auto DSR#/DTR# flow Yes No No No No

No. of Rx interrupt thresholds 127 1 4 4 4
No. of Tx interrupt thresholds 128 1 1 4 1
No. of flow control thresholds 128 n/a n/a 4 n/a

Transmitter empty interrupt Yes No No No No

Readable status of flow control Yes n/a No No No

Readable FIFO levels Yes n/a No No No

Clock prescaler options 248 n/a n/a 2 n/a

Rx/Tx disable Yes No No No No

Software reset Yes No No No No

Device ID Yes No No No No

9-bit data frames Yes No No No No

RS485 buffer enable Yes No No No No

Infra-red (IrDA) Yes No No Yes No

OX16C950 rev B

Table 1 OX16C950 performance compared with 16C450, 16C550, 16C650 and 16C750 devices

Improvements of the OX16C950 over previous generations of PC UART:

Deeper FIFOs:
OX16C950 offers 128-byte deep FIFOs for the transmitter
and receiver.

Higher data rates:
Transmission and reception baud rates up to 15Mbps. A
flexible clock prescaler offers division ratios of 1 to 31 7/8
in steps of 1/8 using a divide-by-“M N/8” circuitry. The
flexible prescaler allows users to select from a wide variety
of input clock frequencies as well as access to higher baud
rates whilst maintaining compatibility with existing software
drivers (see section 14.2).

External clock options:
The receiver can accept an external 1x clock on the DSR#
input. The transmitter can accept a 1x clock on the RI#
input and/or assert its own (Nx) clock on the DTR# output.
In 1x mode, asynchronous data may be transmitted and
received at speeds up to 60Mbps (see section 14.6).

Automatic flow control:
The UART automatically handles either or both in-band
(software) flow control (transmitting and receiving Xon/Xoff
characters) and out-of-band (hardware) flow control using
the RTS#/CTS# or DSR#/DTR# modem control lines.

Special character detection:
The receiver can be programmed to generate an interrupt
upon reception of a particular character value.

Power-down:
The device can be placed in ‘sleep mode’ to conserve
power.

Readable FIFO levels:
Driver efficiency can be improved by using readable FIFO
levels.

Selectable trigger levels:
The receiver FIFO threshold can be arbitrarily
programmed. The transmitter FIFO threshold and
thresholds for automatic flow control can be programmed
to operate at a variety of trigger levels.

Additional control:
The transmitter and receiver can be independently
disabled.

Data Sheet Revision 1.2 Page 5

OXFORD SEMICONDUCTOR LTD.

OX16C950 rev B

Additional status:
Software drivers are able to read the status of in-band and
out-of-band automatic flow control, and distinguish
between Xoff and special character received interrupts.

Software reset:
The software driver may reset the device to recover from
unforeseen or unusual error conditions.

Transmitter empty interrupt:
The transmitter can generate an interrupt when the FIFO
and shift register are both empty.

RS485 buffer enable:
The DTR# pin may be re-assigned as a buffer-enable
signal for RS485 line driver in half-duplex mode (see
ACR[4:3] in section 15.3).

LOCK DIAGRAM

B

2

A[2:0]

D[7:0]

CS0

CS1

CS2#

IOR

IOR#

IOW

IOW#

ADS#

FIFOSEL

RESET

RXRDY#

TXRDY#

DDIS

XTLI

XTLO

CLKSEL

BDOUT#

RCLK

Bus

Interface

Control
and DMA
Interface

Clock &
Baud Rate
Generator

Internal Data Bus

Internal Control Bus

Figure 1: OX16C950 Block Diagram

Device ID:

Four bytes of device ID are available to identify the
OX16C950 device to software drivers.

Infra-red ‘IrDA’ interface:
The UART contains an IrDA compliant modulator and
demodulator.

9-bit data framing:
The OX16C950 may be configured to use in 9-bit character
framing for multi-drop protocols where a tag ID (9
differentiates address and data characters.

Control

and

Status

Registers

Transmitter

128 Byte

FIFO

Receiver

128 Byte

FIFO

Power
supply

Modem
Control

Interface

Interrupt

Control

Logic

SOUT

SIN

VDD

GND

RTS#

DTR#

OUT1

OUT2

CTS#

DSR#

DCD#

RI#

INTSEL

INT

th

bit)

Data Sheet Revision 1.2 Page 6

OXFORD SEMICONDUCTOR LTD.

OX16C950 rev B

P

3

IN INFORMATION

DB5

DB6

DB7

RCLK

SIN

NC

SOUT

CS0

CS1

CS2#

BDOUT#

44 Pin Plastic Leaded Chip Carrier

DB4

DB3

DB2

DB1

DB0

FIFOSEL

VDD

RI#

DCD#

DSR#

CTS#

6543214443424140

7 39

8 38

9 37

10 36

11 35

12 34

13 33

14 32

15 31

16 30

17 29

18 19 20 21 22 23 24 25 26 27 28

XTLI

OX16C950-PCC60-B

IOW

IOW#

XTLO

GND

IOR#

CLKSEL

IOR

DDIS

ADS#

TXRDY#

RESET

OUT1#

DTR#

RTS#

OUT2#

INTSEL#

INT

RXRDY#

A0

A1

A2

48 Pin Thin Quad Flat Pack

VSEL

DB4

DB3

DB2

DB1

DB0

VDD

RI#

DCD#

DSR#

CTS#

FIFOSEL

NC

DB5

DB6

DB7

RCLK

NC

SIN

SOUT

CS0

CS1

CS2#

BDOUT#

48 47 46 45 44 43 42 41 40 39 38 37

1 36

2 35

3 34

4 33

5 32

6 31

7 30

8 29

9 28

10 27

11 26

12 25

13 14 15 16 17 18 19 20 21 22 23 24

NC

OX16C950-TQC60-B

XTLI

XTLO

IOW#

IOW

GND

IOR#

IOR

CLKSEL

DDIS

ADS#

TXRDY#

INTSEL#

RESET

OUT1#

DTR#

RTS#

OUT2#

INT

RXRDY#

A0

A1

A2

NC

Data Sheet Revision 1.2 Page 7

OXFORD SEMICONDUCTOR LTD.

OX16C950 rev B

4

PIN DESCRIPTIONS

PLCC TQFP Dir1 Name Description
Clock

18 14 I XTLI Crystal oscillator input or external clock pin.

Maximum frequency 60 MHz @ 5V, 50 MHz @ 3.3V

19 15 O XTLO Crystal oscillator output. Not used when an alternative TTL level clock is

applied to XTLI and can be left unconnected.

23 21 IU CLKSEL The state of this pin on power up configures the internal clock prescaler. This

pin has an internal pull-up. When CLKSEL pin is high the pre-scalar is
bypassed. Connect this pin to GND to enable the internal clock prescaler
(see section 14.2). The complement of this pin is loaded in MCR[7] after a
hardware reset.

This pin can also be used as an alternative external clock pin under software
control (replacing XTLI and thus reducing noise/power due to XTLO) for
embedded applications

Processor Interface

39 35 I RESET Active-high hardware reset. Hardware reset is described in section 7.1. This

pin must be tied inactive when not in use.

14, 15 9,

10

I CS0,CS1 Active-high chip select. All chip select pins must be active for the device to

be selected.
16 11 I CS2# Active-low chip select.
29 -31 26 – 28 I A[2:0] Address lines to select channel registers.
28 24 I ADS# Active-low address strobe. When ADS# signal is low, the address (A[2:0])

and chip select signal (CS0, CS1, CS2#) drive the internal logic, otherwise

they are latched at the level they were when low-to-high transition of ADS#

signal occurred. This pin is used when address and chip selects are not

stable during read or write cycles. If this functionality is not required, this pin

can be permanently tied to GND.
9 - 2 4 – 2,

I/O DB[7:0] Eight-bit 3-state data bus.

47 – 43

26 22 O DDIS Drive Disable. This pin goes active (high) when CPU is not reading from

OX16C950. This signal can be used to disable an external transceiver.
20

21

16

17

I

IOW#

I

IOW

Active-low write strobe. When IOW# is used to write the chip, IOW should be

tied low (inactive).

Active-high write strobe. When IOW is used to write the chip, IOW# should be

tied high (inactive).
24

25

19

20

I

IOR#

I

IOR

Active-low read strobe. When IOR# is used to read from the chip, IOR should

be tied low (inactive).

Active-high read strobe. When IOR is used to read from the chip, IOR#

should be tied high (inactive).

Data Sheet Revision 1.2 Page 8

OXFORD SEMICONDUCTOR LTD.

OX16C950 rev B

PLCC TQFP Dir1 Name Description
Serial port pins

13 8 O

O

SOUT

IrDA_Out

Transmitter serial data output.

This pin is re-defined to IrDA output when IrDA mode is enabled, i.e. MCR[6]
set in Enhanced mode.

36 32 O RTS# Active-low Request-To-Send output. Whenever the automated RTS# flow

control is enabled, the RTS# pin is de-asserted and re-asserted if the receiver
FIFO reaches or falls below a pair of programmed flow control thresholds,
respectively. This pin’s state is controlled by bit 1 of the MCR. RTS may also
be used as a general-purpose output.

O

O

I

DTR#

485_EN

Tx_Clk_Out

SIN

IrDA_In

Active-low modem Data-Terminal-Ready output. Whenever the automated
DTR# flow control is enabled, the DTR# pin is asserted and de-asserted if the
receiver FIFO reaches or falls below a pair of programmed flow control
thresholds, respectively. The state is set by bit 0 of the MCR. DTR may also
be used as a general purpose output.

In RS485 half-duplex mode, the DTR# pin may be programmed to reflect the
state of the transmitter empty bit (or it’s inverse) to automatically control the
direction of the RS485 transceiver buffer (see ACR[4:3]).

Transmitter 1x (or baud rate generator output) clock. For isochronous
applications, the 1x (or Nx) transmitter clock may be asserted on the DTR#
pin (see CKS[5:4]).
Receiver serial data input.

This pin is re-defined to IrDA input when IrDA mode is enabled, i.e. MCR[6]

37 33 O

11 7 I

set in Enhanced mode.

40 38 I CTS# Active-low Clear-To-Send input. Whenever the automated CTS# flow control

is enabled and the CTS# pin is de-asserted, the transmitter will complete the
current character and enter the idle mode until the CTS# pin is re-asserted.
However, flow control characters are transmitted regardless of the state of the
CTS# pin. The state of this pin is reflected in bit 4 of the MSR. It can also be
used as a general-purpose input.

41 39 I

I

DSR#

Rx_Clk_In

Active-low modem Data-Set-Ready input. Whenever the automated DSR#
flow control is enabled and the DSR# pin is de-asserted, the transmitter will
complete the current character and enter the idle mode until the DSR# pin is
re-asserted. However, flow control characters are transmitted regardless of
the state of the DSR# pin. The state of this pin is reflected in bit 5 of the
MSR. It can also be used as a genera- purpose input.

External receiver clock for isochronous applications. The Rx_Clk_In is
selected when CKS[1:0] = ‘01’.

42 40 I DCD# Active-low modem Data-Carrier-Detect input. The state of this pin is reflected

in bit 7 of the MSR. It can also be used as a general-purpose input

43 41 I

I

RI#

Tx_Clk_In

Active-low modem Ring-Indicator input. The state of this pin is reflected in bit
6 of the MSR. It can also be used as a general-purpose input. RI can be
configured as tx and rx for a 1x clock in isochronous operation.

External transmitter clock. This clock can be used by the transmitter (and by
the receiver indirectly) when CKS[6]=’1’.

17 12 O BDOUT# Baud out. BDOUT# is a Nx (usually 16x, see TCR) clock signal for the

transmitter. It is the output of the baud generator module. The receiver can
use this clock by connecting BDOUT# to the RCLK pin or setting CKS[1:0] to
’10’ where BDOUT# will be connected to RCLK internally. In this case setting
CKS[2] to ‘1’ will disable the BDOUT# pin to conserve power.

10 5 I RCLK Receiver clock. RCLK is the Nx (usually 16x, see TCR) baud rate clock for

the receiver.

Data Sheet Revision 1.2 Page 9

OXFORD SEMICONDUCTOR LTD.

OX16C950 rev B

PLCC TQFP Dir1 Name Description
Interrupt & DMA Pins

33 30 O INT The serial channel has a three-state interrupt output. This signal goes active

(high) when an interrupt condition occurs. The three-state logic is controlled

by INTSEL# and MCR[3] as described below.

27

23 O TXRDY# Signal for DMA transfer of transmitter data. There are two modes of DMA

signalling described in section 8.1.

32 29 O RXRDY# Signal for DMA transfer of received data. There are two modes of DMA

signalling described in section 8.1.

34 36 IU INTSEL# Active-low interrupt select. This pin has an internal pull-up resistor. When

INTSEL# is high or unconnected, the INT pin is enabled and MCR[3] is

ignored. When INTSEL# is low, the tri-state control of INT is controlled by

MCR[3]. In this case INT is enabled when MCR[3] is set and is high-

impedance when MCR[3] is low.

This pin is used to save the external three-state buffer for the interrupt pin.

When using this facility, the INT output should be pulled down to GND using

a 1KΩ resistor.

Miscellaneous Pins
38 34 O OUT1# This user defined output pin reflects the complement of MCR[2]. It is inactive

(high) after a hardware reset or during loopback mode.

35 31 O OUT2# This user defined output pin reflects the complement of MCR[3]. It is inactive

(high) after a hardware reset or during loopback mode

1 37 ID FIFOSEL FIFO select. This pin has an internal pull-down. For backward compatibility

with 16C550, 16C650 and 16C750 devices the FIFO depth is 16 when

FIFOSEL is low or left open. The FIFO size is 128 when FIFOSEL is high.

The unlatched state of this pin is readable by software. The FIFO size may

be set to 128 by writing a 1 in FCR[5] when LCR[7] is set or by putting the

device into Enhanced mode, thus overriding the state of the FIFOSEL pin.

This pin is unconnected in 16C550 and 16C750 devices.

- 48 ID VSEL Voltage selector. This pin is used to control the voltage thresholds on all
input pins. When low (or unconnected), 5V biased TTL thresholds are used.
When high, 3V biased TTL thresholds are used. Generally should be tied
high when the OX16C950 is being powered off 3 Volts, and low (or
unconnected) when powered off 5 Volts. If tied high under 5V operation,
CMOS compatible input thresholds are obtained.

As this pin is not accessible in the PLCC, the PLCC is unsuitable for 3V
applications.

12 1, 13,

NC These pins are not connected.

25, 6

Power and Ground

22 18 GND Ground (0 Volts). The GND pin should be tied to ground.

44 42 VDD Power supply. The VDD pin should be tied to 5 Volts or 3.3 Volts

Table 2: Pin Descriptions

Note 1: Direction key:

I Input
IU Input with pull-up
ID Input with pull-down
O Output
I/O Bi-directional
Note: Attention should be given to high frequency decoupling of power and ground pins due to the high frequency internal switching that occurs

under normal operation

Data Sheet Revision 1.2 Page 10

OXFORD SEMICONDUCTOR LTD.

4.1

Further Pin Information

OX16C950 rev B

Pin Description Action when used Action when not used

Bus Interface Pins

CS0 Chip Select Connect to active high chip select generation

logic

CS1 Chip Select Connect to active high chip select generation

logic

CS2# Chip Select Connect to active low chip select generation

logic

IOR Additional I/O Read Control Connect to processors active high I/O read

line (and tie IOR# high)

IOW Additional I/O Write Control Connect to processors active high I/O write

line (and tie IOW# high)

Tie high – All chip selects must be
active in order to access the device
Tie high – All chip selects must be
active in order to access the device
Tie low – All chip selects must be active
in order to access the device
Tie low (IOR# will be used to control I/O
read operations)
Tie low (IOW# will be used to control
I/O read operations)

Control Pins

INTSEL# Interrupt Control Mode Tie low to allow software enable/disable of the

interrupt pin.

Leave unconnected (Pulled high
internally to leave the interrupt pin
permanently enabled).

DMA Pins

RXRDY# DMA Control signal output Connect direct to DMA control circuitry Leave unconnected
TXRDY# DMA Control signal output Connect direct to DMA control circuitry Leave unconnected

Clock Related Pins

BDOUT# Baud rate generator output Connect direct to the RCLK pin in order to run

Leave unconnected
the receiver with the same clock as the
transmitter

RCLK Receiver clock input Connect directly to a suitable receiver clock

n/a

source (Usually the BDOUT# pin)

XTLI Crystal circuit input Connect to suitable clock input n/a
XTLO Crystal circuit output Connect to crystal oscillator circuit

Leave unconnected

Miscellaneous Pins

DDIS Driver Disable output Connect to active high bus transceiver drive

Leave unconnected
disable (goes high when device is not being
read from)

ADS# Address Strobe In Connect direct to external control circuitry

Tie low
(Low-High transition on this pin latches CS0-2
and A0-2)

OUT1# User defined output Connect direct to TTL input of external circuit

Leave unconnected
to control

OUT2# User defined output Connect direct to TTL input of external circuit

Leave unconnected
to control

Common Channel Pins

SOUT Serial data output Connect to a suitable line driver

SIN Serial data input Connect to a suitable line receiver

RTS# Request-To-Send Modem

signal output

CTS# Clear-To-Send Modem signal

input

DTR# Data-Terminal-Ready

Modem signal output

DSR# Data-Set-Ready

Modem signal input

Connect to a suitable line driver

Connect to a suitable line receiver

Connect to a suitable line driver

Connect to a suitable line receiver

Leave unconnected

(Serial data can not be transmitted)

Leave unconnected

(Serial data can not be received)

Leave unconnected

Tie high

Leave unconnected

Tie high

Data Sheet Revision 1.2 Page 11

OXFORD SEMICONDUCTOR LTD.

Pin Description Action when used Action when not used

DCD# Data-Carrier-Detect

Modem signal input

RI# Ring-Indicator

Modem signal input

INT Interrupt Output Connect to an available processor interrupt

Connect to a suitable line receiver

Connect to a suitable line receiver

line

Tie high

Tie high

Leave unconnected

(Interrupts can not be used)

OX16C950 rev B

Data Sheet Revision 1.2 Page 12

OXFORD SEMICONDUCTOR LTD.

ODE SELECTION

M

5

The OX16C950 device is a single channel device software compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs.
The operation of the OX16C950 depends on a number of mode settings. These modes are referred to throughout this data
sheet. The FIFO depth and compatibility modes are tabulated below:

UART Mode FIFO

450 1 0 X X X

550 16 1 0 0 0

Extended 550 128 1 0 X 1

650 128 1 1 X X
750 128 1 0 1 0

950* 128 1 1 X X

450 Mode

5.1

After a hardware reset bit 0 of the FIFO Control Register
(‘FCR’) is cleared, hence OX16C950 is compatible with the
16C450. The transmitter and receiver FIFOs (referred to as
the ‘Transmit Holding Register’ and ‘Receiver Holding
Register’ respectively) have a depth of one. This is referred
to as ‘Byte mode’. When FCR[0] is cleared, all other mode
selection parameters are ignored.

size

FCR[0] Enhanced mode

(EFR[4]=1)

Table 3: UART Mode Configuration

* Note that 950 mode configuration is identical to 650 configuration

(guarded with LCR[7] = 1)

guard. Once FCR[5] is set, the software should clear
LCR[7] for normal operation.

The 16C750 additional features over the 16C550 are
available as long as the UART is not put into Enhanced
mode (i.e. EFR[4] should be ‘0’). These features are:

1. Deeper FIFOs

2. Automatic RTS/CTS out-of-band flow control

3. Sleep mode

FCR[5]

OX16C950 rev B

FIFOSEL

pin

5.2

550 Mode

Connect FIFOSEL to GND or leave it unconnected. After a
hardware reset, writing a 1 to FCR[0] will increase the FIFO
size to 16, providing compatibility with 16C550 devices.
Since this pin is a no-connect in 16C550 devices, replacing
a 16C550 with OX16C950 would result in a 550 compatible
device with 16 byte deep FIFOs.

5.3

Extended 550 Mode

Connect FIFOSEL to VDD. Writing a 1 to FCR[0] will now
increase the FIFO size to 128, thus providing a 550 device
with 128 deep FIFOs.

5.4

750 Mode

For compatibility with 16C750, leave FIFOSEL
unconnected.

Writing a 1 to FCR[0] will increase the FIFO size to 16. In a
similar fashion to 16C750, the FIFO size can be further
increased to 128 by writing a 1 to FCR[5]. Note that access
to FCR[5] is protected by LCR[7]. I.e., to set FCR[5],
software should first set LCR[7] to temporarily remove the

650 Mode

5.5

The OX16C950 is compatible with the 16C650 when
EFR[4] is set, i.e. the device is in Enhanced mode. As 650
software drivers usually put the device into Enhanced
mode, running 650 drivers on the OX16C950 device will
result in 650 compatibility with 128 deep FIFOs, as long as
FCR[0] is set. This is regardless of the state of the
FIFOSEL pin or package option. Note that the 650
emulation mode of the OX16C950 provides 128 byte deep
FIFOs whereas the standard 16C650 has only 32 byte
FIFOs.

650 mode has the same enhancements as the 16C750
over the 16C550, but these are enabled using different
registers.

There are also additional enhancements over those of the
16C750 in this mode, these are:

1. Automatic in-band flow control

2. Special character detection

3. Infra-red “IrDA-format” transmit and receive mode

4. Transmit trigger levels

5. Optional clock prescaler

Data Sheet Revision 1.2 Page 13

OXFORD SEMICONDUCTOR LTD.

OX16C950 rev B

5.6

950 Mode

The additional features offered in OX16C950 (950 mode)
generally only apply when the UART is in Enhanced mode
(EFR[4]=’1’). Provided FCR[0] is set, in Enhanced mode
the FIFO size is 128 regardless of the state of FIFOSEL.

Note that 950 mode configuration is identical to that of 650
mode, however additional 950 specific features are
enabled using the Additional Control Register ‘ACR’ (see
section 15.3). In addition to larger FIFOs and higher baud
rates, the enhancements of the 16C950 over the 16C654
are:

•

Selectable arbitrary trigger levels for the receiver and
transmitter FIFO interrupts

•

Improved automatic flow control using selectable
arbitrary thresholds

• DSR#/DTR# automatic flow control

•

Transmitter and receiver can be optionally disabled

• Software reset of device

•

Readable FIFO fill levels

•

Optional generation of an RS-485 buffer enable signal

• Four-byte device identification (0x16C95003)

•

Readable status for automatic in-band and out-of­band flow control

•

External 1x clock modes (see section 14.4)

• Flexible “M N/8” clock prescaler (see section 14.2)

•

Programmable sample clock to allow data rates up to
15 Mbps (see section 14.3)

•

9-bit data mode
The 950 trigger levels are enabled when ACR[5] is set (bits
4 to 7 of FCR are ignored). Then arbitrary trigger levels can
be defined in RTL, TTL, FCL and FCH registers (see
section 15). The Additional Status Register (‘ASR’) offers
flow control status for the local and remote transmitters.
FIFO levels are readable using RFL and TFL registers.

The UART has a flexible prescaler capable of dividing the
system clock by any value between 1 and 31.875 in steps
of 0.125. It divides the system clock by an arbitrary value in
“M N/8” format, where M and N are 5 and 3-bit binary
numbers programmed in CPR[7:3] and CPR[2:0]
respectively. This arrangement offers a great deal of
flexibility when choosing an input clock frequency to
synthesize arbitrary baud rates. The default division value
is 4 to provide backward compatibility with 16C650
devices.

The user may apply an external 1x (or Nx) clock for the
transmitter and receiver to the RI# and DSR# pin
respectively. The transmitter clock may be asserted on the
DTR# pin. The external clock options are selected through
the CKS register (offset 0x02 of ICR).

It is also possible to define the over-sampling rate used by
the transmitter and receiver clocks. The 16C450/16C550
and compatible devices employ 16 times over-sampling,
i.e. There are 16 clock cycles per bit. However, OX16C950
can employ any over-sampling rate from 4 to 16 by
programming the TCR register. This allows the data rates
to be increased to 460.8 Kbps using a 1.8432MHz clock, or
15 Mbps using a 60 MHz clock. The default value after a
reset for this register is 0x00, which corresponds to a 16
cycle sampling clock. Writing 0x01, 0x02 or 0x03 will also
result in a 16 cycle sampling clock. To program the value to
any value from 4 to 15 it is necessary to write this value
into TCR i.e. to set the device to a 13 cycle sampling clock
it would be necessary to write 0x0D to TCR. For further
information see sections 14.3.

The OX16C950 also offers 9-bit data frames for multi-drop
industrial applications.

Data Sheet Revision 1.2 Page 14

OXFORD SEMICONDUCTOR LTD.

EGISTER DESCRIPTION TABLES

R

6

OX16C950 rev B

The three address lines select the various registers in the UART. Since there are more than 8 registers, selection of the registers
is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:

1. LCR[7]=1 enables the divider latch registers DLL and DLM.

2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables

access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.

3. ACR[7]=1 enables access to the 950 specific registers.

4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 17.

Register

Name

THR 1 000 W Data to be transmitted

RHR 1 000 R Data received

IER

650/950

Mode

550/750

Mode

FCR 3

650 mode

750 mode

950 mode

Address R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1,2

001 R/W

010 W

CTS

interrupt

mask

RHR Trigger

RHR Trigger

Unused

Level

Level

RTS

interrupt

mask

Alternate

Unused

Special

Char.

Detect

sleep
mode

THR Trigger

FIFO

Size

Level

Sleep
mode

Unused

Modem

interrupt

mask

DMA

Mode /

Tx

Trigger

Enable

Rx Stat

interrupt

mask

Flush

THR

THRE

interrupt

mask

Flush

RHR

RxRDY

interrupt

mask

Enable

FIFO

ISR 3 010 R

LCR 4 011 R/W

3,4

MCR

550/750

Mode

650/950

Mode

3,5

LSR

Normal

9-bit data

mode

MSR 3 110 R DCD RI DSR CTS

SPR 3

Normal

9-bit data

mode

Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.

DLL 000 R/W Divisor latch bits [7:0] (Least significant byte)

DLM 001 R/W Divisor latch bits [15:8] (Most significant byte)

100 R/W

101 R

111 R/W

FIFOs

enabled

Divisor

latch

access

Baud

prescale

Data

Error

Tx

break

Unused

IrDA

mode

Tx Empty

Interrupt priority

(Enhanced mode)

Force
parity

CTS &

RTS
Flow

Control

XON-Any

THR

Empty

Indexed control register offset value bits

Odd /

even

parity

Internal

Loop
Back

Enable

Rx

Break

Temporary data storage register and

Unused

Parity

enable

OUT2

(Int En)

Framing

Error

Delta

DCD

Interrupt priority

(All modes)

Number

of stop

bits

OUT1 RTS DTR

Parity

Error

th

Rx

9

data bit
Trailing

RI edge

Data length

Overrun

Error

Delta

DSR

Interrupt
pending

RxRDY

Delta

CTS

9th Tx

data bit

Table 4: Standard 550 Compatible Registers

Data Sheet Revision 1.2 Page 15