Orsys micro-line C6713CPU Hardware Reference Manual
H
ARDWARE REFERENCE GUIDE
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 1
Orsys Orth System GmbH, Am Stadtgraben 25, 88677 Markdorf
,
Germany http://www.orsys.de
Hardware Reference Guide
micro-line
C6713CPU
High performance DSP / FPGA board
H
ARDWARE REFERENCE GUIDE
MICRO-LINE
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 2
Contents
1 PREFACE......................................................................................................................6
1.1 Document Organization.........................................................................................................6
1.2 Documentation Overview ......................................................................................................6
1.3 Notational conventions..........................................................................................................6
1.4 Trademarks.............................................................................................................................7
1.5 Revision History.....................................................................................................................8
2 HARDWARE OVERVIEW .............................................................................................9
2.1 Block Diagram of the C6713CPU ........................................................................................10
2.2 Connectors ...........................................................................................................................12
2.2.1 micro-line® Connectors........................................................................................................ 12
2.2.2 JTAG Connector.................................................................................................................. 12
2.3 Interfaces and Hardware Components...............................................................................12
2.3.1 FPGA................................................................................................................................... 12
2.3.2 External Memory (on-board SDRAM).................................................................................. 13
2.3.3 Flash Memory...................................................................................................................... 14
2.3.4 PLD .....................................................................................................................................14
2.3.5 UART / RS-232 Interface .................................................................................................... 14
2.3.6 Temperature Sensor ........................................................................................................... 14
2.3.7 Reset Generator and Watchdog.......................................................................................... 15
2.3.8 External Flags (XF signals) ................................................................................................. 15
2.3.9 Power Supply of the Board.................................................................................................. 15
2.4 Status LED's .........................................................................................................................15
2.4.1 User Programmable LED's (PLD) .......................................................................................16
2.4.2 User Programmable LED (FPGA) .......................................................................................16
2.5 DSP peripherals....................................................................................................................16
2.5.1 Multichannel Audio Serial Ports (McASP) ...........................................................................16
2.5.2 External Memory Interface (EMIF) ......................................................................................16
2.5.3 Inter Integrated Circuit (I2C) Interfaces................................................................................ 17
2.5.4 General Purpose Input / Output Pins (GPIO) ...................................................................... 17
2.5.5 Multi-channel Buffered Serial Ports (McBSP)...................................................................... 17
2.5.6 Timers .................................................................................................................................18
2.5.7 Host Port Interface (HPI) ..................................................................................................... 18
2.5.8 Interrupts ............................................................................................................................. 18
2.5.9 DMA ....................................................................................................................................19
3 MEMORY MAPS AND DESCRIPTION OF THE PLD REGISTERS ...........................20
3.1 TMS320C6713 Memory Map ................................................................................................20
3.2 C6713CPU Address Map......................................................................................................21
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3.3 Internal fast SRAM ...............................................................................................................21
3.4 DSP Peripherals ...................................................................................................................21
3.5 External SDRAM...................................................................................................................21
3.6 Flash Memory .......................................................................................................................21
3.7 Endianness ...........................................................................................................................22
3.8 EMIF Configuration ..............................................................................................................23
3.8.1 Default EMIF configuration.................................................................................................. 23
3.9 Description of the PLD Board Registers............................................................................23
3.10 Description of the PLD Registers .....................................................................................24
3.10.1 Hardware Configuration Register (HWCFG) .....................................................................24
3.10.2 FPGA Control Register (FCR)........................................................................................... 25
3.10.3 LED Control Register (LED) ..............................................................................................25
3.10.4 Module Control Register (MCR) ........................................................................................ 26
3.10.5 I2C Bus Control Register (I2C) ..........................................................................................26
3.10.6 External Flag Register (XF)............................................................................................... 27
3.10.7 Watchdog Register (WDG)................................................................................................ 27
3.10.8 Version Register (VER) ..................................................................................................... 28
4 BOOT PROCESS AND DEFAULT SETUP OF THE C6713CPU................................29
5 USING THE FLASH FILE SYSTEM............................................................................30
6 DESCRIPTION OF THE MICRO-LINE® BOARD CONNECTORS..............................31
6.1 Location of the Connectors.................................................................................................31
6.2 Connector Overview ............................................................................................................32
6.3 Pinout Tables of the micro-line® Connector ......................................................................32
6.4 Pinout of the JTAG Connector............................................................................................35
6.5 Function of the micro-line® Connector Pins......................................................................36
6.5.1 Connector A ........................................................................................................................ 36
6.5.2 Connector B ........................................................................................................................ 36
6.5.3 Connector BB ...................................................................................................................... 36
6.5.4 Connector D ........................................................................................................................ 37
6.5.5 Connector E ........................................................................................................................ 38
7 ENVIRONMENT ..........................................................................................................44
7.1 Minimum Connections.........................................................................................................44
7.2 Changing the Board Configuration.....................................................................................46
7.2.1 Location of modifiable components..................................................................................... 46
7.2.2 Configuring DSP Clock Speed ............................................................................................ 47
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7.2.3 Configuring for HPI or McASP1 Usage ...............................................................................47
7.2.4 Configuring micro-line® Pin D30 Termination ...................................................................... 47
7.2.5 Configuring for I2C interface #0 Operation ..........................................................................47
7.2.6 Configuring CLKS1 / SCL1 Termination.............................................................................. 48
7.2.7 Configuring FPGA I/O Behavior When FPGA is not Loaded............................................... 48
7.3 Signal Levels and Loads .....................................................................................................48
7.3.1 Input Voltage Levels for non-FPGA Signals........................................................................ 48
7.3.2 Output Voltage Levels for non-FPGA Signals .....................................................................48
7.3.3 Allowed Output Loads ......................................................................................................... 48
7.4 Supply Voltage .....................................................................................................................49
7.5 Power Consumption ............................................................................................................49
7.6 Reset Timing.........................................................................................................................49
7.7 Ambient Temperature ..........................................................................................................49
7.8 Ambient Humidity.................................................................................................................49
7.9 Dimensions of the Board.....................................................................................................50
7.10 Spare micro-line® Connectors...........................................................................................52
8 LIST OF ABBREVIATIONS USED IN THIS DOCUMENT ..........................................53
9 LITERATURE REFERENCES.....................................................................................54
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Date : 28 November 2005
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Iss./Rev : 1.1
Page : 5
List of Tables
Table 1: Memory map of the processor........................................................................................... 20
Table 2: Memory map of the C6713CPU ........................................................................................ 21
Table 3: default initialization values for the FPGA related CE space registers ...............................23
Table 4: CE2 default configuration .................................................................................................. 23
Table 5: CE3 default configuration .................................................................................................. 23
Table 6: PLD and UART registers of the C6713CPU...................................................................... 24
Table 7: PLD register quick reference.............................................................................................24
Table 8: Version register encoding.................................................................................................. 28
Table 9: Default clock and EMIF settings of the C6713CPU........................................................... 29
Table 10: Connector overview......................................................................................................... 32
Table 11: Pinout of the micro-line® connectors ...............................................................................32
Table 12: Pinout summary for the McBSP interfaces...................................................................... 33
Table 13: Pinout summary for the timers ........................................................................................33
Table 14: Pinout summary for the I2C interfaces............................................................................. 33
Table 15: Pinout summary and signal routing for the McASP interfaces ........................................ 34
Table 16: Pinout of the JTAG connector .........................................................................................35
Table 17: Factory default configuration summary ...........................................................................46
Table 18: Voltage limits for the C6713CPU..................................................................................... 49
Table 19: Power consumption of the C6713CPU............................................................................ 49
Table 20: Reset timing ....................................................................................................................49
List of Figures
Figure 1: Block diagram of the C6713CPU ..................................................................................... 10
Figure 2: Top side of the C6713CPU ..............................................................................................11
Figure 3: Bottom side of the C6713CPU ......................................................................................... 11
Figure 4: FPGA connections overview ............................................................................................ 13
Figure 5: Data representation in memory in little endian configuration ...........................................22
Figure 6: Connector locations .........................................................................................................31
Figure 7: JTAG adapter for the C6713CPU ....................................................................................35
Figure 8: Supplying the C6713CPU with power .............................................................................. 44
Figure 9: Connecting the serial interface (RS-232) to a PC ............................................................ 45
Figure 10: Location of configuration elements (top side) ................................................................46
Figure 11: Location of configuration elements (bottom side) ..........................................................47
Figure 12: Dimensions of the C6713CPU (in millimeters)............................................................... 50
Figure 13: Complete micro-line® footprint........................................................................................ 51
Figure 14: C6713CPU connector pins............................................................................................. 52
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ARDWARE REFERENCE GUIDE
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Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 6
1 Preface
This document describes the hardware of the C6713CPU board. It is intended to get an overview
of the board and its features. Detailed information about programming, usage of the FPGA and the
DSP is described in other documents that will be referenced throughout this document.
1.1 Document Organization
This document is organized as follows:
Chapter 2 gives an overview of the whole system and its interfaces
Chapter 3 gives an overview of the memory maps and describes the PLD registers
Chapter 4 describes the boot process and the default settings of the board
Chapter 5 gives a brief introduction to the Flash File System of the board
Chapter 6 describes externally available signals and connector pinouts
Chapter 7 lists environmental conditions, such as voltage levels, temperature range, etc.
Chapter 9 lists documents that contain further information
Chapter 8 explains the abbreviations that are used throughout this document
1.2 Documentation Overview
This chapter lists the documentation from ORSYS that is shipped together with the C6713CPU.
Further documents from other vendors may also be listed in chapter 9 and are referenced
throughout this document in square brackets.
C6713CPU DSP Development Kit User's Guide [20]
(
C6713CPU_DSP_DevKit_ug.pdf
):
This document describes software development for the C6713CPU board using DSP/BIOS and the
C6713CPU
board library. The board library is a collection of low level drivers that allow to access
hardware on the C6713CPU, such as loading the FPGA, reading the temperature sensor etc. This
makes working with the C6713CPU easier.
C6713CPU micro-line
®
busmaster BSP User's Guide [21] (
C6713CPU_ml_bm_ug.pdf
):
Describes the micro-line
®
busmaster board support package (BSP). This BSP adds an
asynchronous parallel bus peripheral interface, an UART and HPI accessibility to the C6713CPU.
The user guide includes FPGA register description and FPGA register programming
documentation.
C6713CPU FPGA Programming Guide [22] (
C6713CPU_FPGA_pg.pdf
)
Describes how to develop customized FPGA designs. Part of the FPGA development kit.
Micro-line
®
Power Supply Kit [23] (
Power_Supply.pdf
):
Describes the micro-line
®
Power Supply board.
Reference documents that contain further information are listed in chapter 9, "Literature
References”. References to these documents are given in square brackets throughout this
document.
1.3 Notational conventions
Names of registers, bit fields and single bits are written in capital letters.
Example:
HWCFG
Names of signals are also given in capital letters, active low signals are marked with a '/' at the
beginning of the name.
Example:
/RESETIN
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Configuration parameters, function names, path names and file names are written in italic typeface.
Example:
dev_id
Source code examples are given in a small, fixed-width typeface.
Example:
int a = 10;
Menus and commands from menus and submenus are enclosed in double-quotes. Example:
Create a new project using the "Create Project..." command from the "File" menu.
The members of a bit field or a group of signals are numbered starting at zero, which is the least
significant bit.
Example:
CFG[4:0] identifies a group of five signals, where CFG0 is the least significant bit and
CFG4 is the most significant bit.
If necessary, numbers are represented with a suffix that specifies their base.
Example: 12AB
16
is a hexadecimal number (base 16 = hexadecimal) and is equal to 477910.
The bit fields of a register are displayed with the most significant bit to the left. Below each bit field
is a description of its read / write accessibility and its default value:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A B C D E F G H I J K L N O
r,w,0 r,w,0 r,w,0 r,w,0 r,w,0 r,w,0 r,w,010
2
r,0 r,wc,0 w r,w,0 rc,0 r,w,0 r,w,0
bit number bit name
accessibility and default value
legend:
r bit is readable
rc this bit is cleared after a read
r,w bit is readable and writeable, reading yields the previously written value unless otherwise
specified.
w bit is writeable, read value is undefined
wc writing a 1 to this bit clears it
w,0 bit is write-only, reading always yields 0.
0 default value
1.4 Trademarks
TI, Code Composer, DSP/BIOS and TMS320C6000 are registered trademarks of Texas
Instruments.
Microsoft
and Windows are either registered trademarks or trademarks of Microsoft Corporation
in the United States and/or other countries.
Hypterterminal is a trademark of Hilgraeve Inc.
All other brand or product names are trademarks or registered trademarks of their respective
companies or organizations.
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1.5 Revision History
Revision Changes
0.1 ORSYS internal preliminary version / April 2005
0.5 First public preliminary version / May 2005
0.9 Completely revised.
Block diagram completed.
1.0 Flash File System: short description only, reference to separate user's guide.
Mentioned that HPI usage requires FPGA.
Minor corrections to signal descriptions: series resistors, /RESETOUT pull-up, default
state of RTS, recommended usage of D19..D21, SCL0/SDA0 usage, HPI driver
direction control.
Values for typical power consumption added.
Dimensions of connector pins revised.
1.1 Added note about RS-232 usage with Win 2k and XP.
Board dimensions: board and connector height added.
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Date : 28 November 2005
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Iss./Rev : 1.1
Page : 9
2 Hardware Overview
The micro-line® C6713CPU is a high performance DSP board that combines several key
technologies for high speed data processing:
a TMS320C6713 DSP with 256 KB internal fast SRAM and 225MHz or 300MHz CPU clock
(1800 MIPS / 1350 MFLOPS or 2400 MIPS / 1800 MFLOPS)
a Xilinx Spartan 3 FPGA with up to 1M gates
32 / 64 MB SDRAM in standard versions and 128 MB on request
2 MB flash memory for non-volatile program, data and FPGA design storage
The C6713CPU is available in different versions, regarding processor speed and memory size.
Please contact ORSYS or ORSYS distributors for the newest product list.
For proper operation of the micro-line
®
C6713CPU ORSYS recommends the desk carrier micro-
line
®
PowerSupply board which provides:
3.3 V regulated power supply for the C6713CPU
a 9-Pin SUB-D connector for the RS-232 interface
a reset button
Two isolated ±15 V DC/DC converters for peripheral I/O power supply (optional)
ORSYS furthermore offers complete development packages including Code Composer Studio,
XDS510 JTAG emulator/debugger or equivalent types and all necessary accessories like cables,
power supplies and software libraries.
This documentation describes the basic features of the C6713CPU. It does not include details of
the FPGA or the DSP. For further information about the FPGA, please refer to Xilinx [2]. For further
information about the DSP, please refer to Texas Instruments [1]. A good starting point is also the
chapter "documentation support" in [4].
Many operational features of the C6713CPU require the use of a specific FPGA design, which is
provided by an according board support package (BSP).
The FPGA of the C6713CPU can be used either with the default BSP from ORSYS which is preinstalled when the C6713CPU is shipped, or with individual custom designs using the FPGA
development option. The default BSP from ORSYS allows to operate the C6713CPU as a standard
micro-line
®
DSP board. In this case it is logically upward compatible to other existing micro-line
®
products such as the C6711CPU (if the C6711CPU is operated with 3.3V only).
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2.1 Block Diagram of the C6713CPU
Figure 1: Block diagram of the C6713CPU
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C9
green LED (PLD)
red LED (PLD)
yellow LED (FPGA)
JTAG
connector
DSP SDRAM
temperature
senso
r
flash memory FPG
A
PLD
micro-line connectors
Figure 2: Top side of the C6713CPU
micro-line connectors
R1
SDRAM
16 bit HPI data bus transceiver
Figure 3: Bottom side of the C6713CPU
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2.2 Connectors
2.2.1 micro-line® Connectors
The micro-line
®
connectors are the main I/O connectors of the C6713CPU. They provide access to
all signals that are needed for a wide range of I/O connectivity. The signals on the micro-line
®
connectors can be grouped into the following categories:
power supply
DSP- and board specific interfaces, such as timers and serial ports
FPGA specific signals (their function depend on the respective FPGA design)
Historically (without FPGA) the micro-line
®
connectors carried the following signals:
power supply
DSP- and board specific interfaces, such as timers and serial ports
the micro-line
®
peripheral interface which allowed straightforward access to peripherals
Today, with FPGA technology onboard, many of the micro-line
®
I/O signals can be individually
hardware-configured for nearly any application. This is possible by building an individual,
application-specific FPGA design which exactly covers the application's requirements.
Nevertheless, the micro-line
®
standard peripheral interface is still available as a board support
package, the micro-line busmaster BSP
®
. It is the default configuration when the C6713CPU board
is shipped from ORSYS. The pinning of the micro-line
®
connectors (without any particular FPGA
design loaded) is described in chapter 6. The pinning and functionality of the micro-line
®
busmaster
BSP is described in [21].
2.2.2 JTAG Connector
The JTAG connector is used during development of application software or FPGA designs. It
contains two separate JTAG interfaces, one for the DSP and one for the FPGA.
The DSP JTAG interface is used for debugging and application software download during
development, together with Texas Instruments Code Composer Studio and an XDS510 (or similar)
emulator. After the software development is finalized, the user application software can be
downloaded from the development PC to the C6713CPU's flash memory via RS232 for permanent
storage. This is managed by the Flash File System which is permanently installed on the
C6713CPU.
The FPGA JTAG interface can be used to quickly download and test FPGA designs during
development without permanent storage on the C6713CPU. After the FPGA development is
finalized, the FPGA design can be downloaded from the development PC via RS232 to the
C6713CPU's flash memory for permanent storage. This is managed by the Flash File System
which is permanently installed on the C6713CPU.
In order to connect a standard DSP JTAG emulator or a standard FPGA download cable to the
C6713CPU, a JTAG adapter is used, which is included in C6713CPU development kits. The JTAG
adapter is described in chapter 6.4.
2.3 Interfaces and Hardware Components
2.3.1 FPGA
The default FPGA design for the C6713CPU can be used for standard micro-line
®
bus compatible
applications. Alternatively the FPGA can be individually programmed by the user. This is possible
by using an optional FPGA development package from ORSYS together with standard FPGA
development tools from Xilinx. FPGA technology allows flexible internal logic and individual I/O
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interfacing over for the majority of the micro-line
®
connector pins. The user is no longer restricted
to a fixed I/O logic.
The FPGA has access to the following signal groups:
DSP EMIF (data bus, address bus, control signals)
micro-line
®
connectors
JTAG interface
DSP interrupts
RS232 line driver
The figure below gives an overview, how the FPGA is connected on the C6713CPU board. The
numbers shows the number of signals for each connection. The description of the micro-line
®
connectors in parentheses show the classic functions, as they are implemented by the micro-line
®
busmaster BSP (see [21]) and also by classic micro-line
®
CPU and peripheral boards without
FPGA.
Figure 4: FPGA connections overview
After power up or hardware reset, the FPGA is automatically cleared and has to be loaded before it
starts operation. This can be done manually by application software or automatically by the Flash
File System of the C6713CPU. The FPGA can be loaded at any time and can also be reloaded
with a different configuration during runtime without the need to power-off or reset the whole board.
During system startup, a FPGA design is loaded by the Flash File System (see chapter 2.3.3). This
FPGA design leaves all external pins passive, except the RS-232 interface. For a more detailed
description of the FPGA signals, please refer to the documentation of the micro-line busmaster
BSP [21] or FPGA development [22].
2.3.2 External Memory (on-board SDRAM)
The C6713CPU uses 32-bit wide SDRAM with 32 or 64 MB in standard off-the-shelf versions and
up to 128 MB on request. This provides a large memory space for storage of program code or
data. The memory access timings are based on the EMIF clock which is initialized to 90 MHz
(225 MHz CPU clock) or 100 MHz (300MHZ CPU clock) by the Flash File System. The EMIF clock
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can be software reconfigured by PLL settings. It can also be generated by the FPGA, allowing any
clock frequency up to 100 MHz.
Compared to the internal fast SRAM of the DSP chip, the on-board SDRAM is significantly slower.
Therefore it is strongly recommended to use the internal memory of the DSP whenever it is
possible. The internal memory can be used as memory for time critical code and data as well as L2
cache. See [4] for details.
2.3.3 Flash Memory
The C6713CPU uses an MX29LV160BT flash memory for non-volatile storage. The flash memory
is 16 bit wide and can hold up to 2 MB. It is used for permanent storage of software- and FPGA
code.
After reset or power up, the DSP boots from the first address of the flash memory. The DSP
internal boot loader copies the first 1 KB to internal memory to address 0 and executes it. Further
loading is realized by a secondary loader program.
The C6713CPU is always shipped with the Flash File System installed. It handles all flash memory
programming and management of stored data. The Flash File System is automatically booted after
reset or power up. It first initializes the system, then looks for commands from a host on the RS232 interface (See [24] for a description of the host side utilities) and then loads the FPGA(s) and a
user program that are selected for auto-boot. Since RS-232 usage on the C6713CPU requires a
loaded FPGA design, the Flash File System already contains a startup FPGA design, which is
loaded during system startup. Later on it will be overwritten when the on-board auto-boot FPGA is
loaded.
2.3.4 PLD
The PLD contains some necessary glue logic of the board. It provides all necessary resources to
run the DSP without a loaded FPGA. It also contains some register that configure board operation.
See chapter 3.10 for a description of the PLD registers,
2.3.5 UART / RS-232 Interface
The RS-232 interface is realized inside the FPGA and is connected to a RS-232 line driver.
Therefore, to use the RS-232 interface, an appropriate FPGA design must be loaded. The RS-232
interface can be used as general purpose communication interface. Functions like
fprintf(), and
fgetc(), etc. are executable by the application program on the micro-line
®
C6713CPU, using the
RS-232 interface as a communication channel, e.g. to transfer measurement results to a host
system or to control a connected peripheral device. Another common usage of the RS232 interface
is to output debugging information during testing.
The interface consists of the signals TxD (transmit data), RxD (receive data), RTS (request to
send) and CTS (clear to send). These signals are available at the micro-line
®
connector. Please
refer to chapter 6.1 for details. The CTS input signal can also be configured in a way to generate a
system reset on the C6713CPU board.
The UART of the (default) micro-line busmaster BSP can operate at programmable baud rates up
to 1Mbaud.
The RS-232 line driver can be switched into shutdown mode to reduce power consumption. Please
see chapter 3.10.4 for details.
Please note: When using the RS-232 interface in conjunction with a PC that runs Windows 2000 or
XP, the transmit buffer settings of the PC's COM port must be changed on the PC as described for
the Flash File System installation in [24].
2.3.6 Temperature Sensor
The C6713CPU has an onboard temperature sensor with a serial I
2
C-Bus interface in order to
determine the board temperature during operation. The sensor can measure a temperature range
from –25°C up to +85°C with an accuracy of 2 degrees and –55°C up to +125°C with an accuracy
of 3 degrees. If the C6713CPU is operated in an environment where it is exposed to high
temperatures, the temperature sensor can be used to detect over-temperature conditions. The
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DSP-internal temperature is roughly 15 degrees Celsius above the temperature measured by the
sensor. Software drivers for the temperature sensor are included in the development kits, see [20]
for details. Further information can be found in [18].
The temperature sensor is connected to the PLD by a separate I
2
C interface. It does not use the
I
2
C interfaces of the DSP. The temperature sensor can be accessed by the I2C bus control register
(see chapter 3.10.5).
2.3.7 Reset Generator and Watchdog
The C6713CPU board provides a triple voltage supervising reset generator which generates a
defined reset pulse in case of one or more of the following events:
power up
software reset (via the module control register; see chapter 3.10)
the /RESETIN pin is active (low)
one of the supply voltages drops below a certain limit
the reset generator's watchdog timer is enabled and has expired
The reset function of the RS232 CTS line is activated and CTS is active.
During the reset pulse the micro-line
®
signals /RESETOUT and RESETOUT are activated.
The reset generator circuit has a watchdog timer that causes a reset if it is not reset periodically by
software. The watchdog timer is disabled by default, thus no resets will be generated and the
watchdog timer does not need to be reset by software.
Enabling the watchdog timer and resetting it is described in chapter 3.10.7.
2.3.8 External Flags (XF signals)
The C6713CPU provides two dedicated general-purpose I/O pins that can be configured as either
inputs or outputs. When configured as an output, the user can write to a PLD register to control the
state driven on the output pin. When configured as an input, the user can detect the state of the
input by reading the state of a PLD register. Please refer to chapter 3.10 for a description on how
to control the XF pins. Please note that also some of the on-chip interfaces of the DSP, such as the
McBSP, can be used as general purpose I/O.
2.3.9 Power Supply of the Board
The C6713CPU must be supplied with a voltage of 3.3 V. It is not designed for 5V supply! Please
refer to chapter 7.1 for connection details.
CAUTION:
The C6713CPU is not protected against reversed voltage. Please be careful when connecting the
power supply to the board. Applying reversed voltage will damage the board!
The following voltages are generated internally on the C6713CPU by highly efficient switched
mode voltage regulators:
1.4 V supply voltage for the processor core
1.25 V supply voltage for the FPGA core
2.4 Status LED's
On the C6713CPU there are two groups of LED's:
two user programmable LED's controlled by the PLD
one user programmable LED controlled by the FPGA
H
ARDWARE REFERENCE GUIDE
MICRO-LINE
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 16
2.4.1 User Programmable LED's (PLD)
These LED's are controlled by PLD registers (see chapter 3.10). They can be switched on and off
by application software to display certain events or states.
Examples for software controlled usage of the LED's are:
displaying an error condition by the red LED
checking software activity by toggling one of the LED each time the main loop is executed
DSP load indicator, flashing the LED during interrupt handlers or calculations
Furthermore, the green LED can automatically be driven by other hardware activities:
CE1 is active, PLD or UART is accessed
Flash is accessed (default)
2.4.2 User Programmable LED (FPGA)
A yellow LED is directly connected to the FPGA. The function is defined by the respective FPGA
design or BSP and is described in the BSP documentation.
2.5 DSP peripherals
The TMS320C6713 DSP has a number peripheral interfaces integrated on the chip. These
interfaces are described briefly in this chapter. Hardware and programming details can be found in
the respective literature from Texas Instruments [6] to [9].
Some of the DSP peripheral interfaces share pins with others. Therefore, care must be taken when
using multiple peripherals to ensure that all interfaces are available at the same time.
2.5.1 Multichannel Audio Serial Ports (McASP)
The McASPs are serial ports, optimized for the needs of multi-channel audio applications. Two
McASP ports are available on the TMS320C6713. The McASP ports are described in [4] and [7] in
detail.
The signals of the McASP ports are shared with signals of other DSP peripherals like:
McBSPs
Timers
GPIO 5 / EXT_INT5
GPIO 4 / EXT_INT4
Host Port Interface
At the C6713CPU board, the McASP0 port is available at micro-line
®
connectors. Chapter 6.3
contains detailed tables of shared signals. Further information can also be found in [4].
By default, the McASP1 port is disabled by hardware and the Host Port Interface (HPI) is enabled
therefore. If McASP1 is needed for a certain application, a slight hardware reconfiguration on the
C6713CPU board is necessary. In this case please contact ORSYS. Further details about McASP1
configuration are also described in chapter 7.2.
2.5.2 External Memory Interface (EMIF)
The EMIF is the main on-board 32 bit bus-interface between the DSP and other components. It is
connected to:
on-board memory (SDRAM, flash memory)
on-board peripherals (PLD)
FPGA
The EMIF can also be used to access off-board hardware by using an appropriate FPGA design.
This can either be a standard BSP from ORSYS, or a custom FPGA design.
The EMIF is mapped into the DSP's address space, separated into four areas called CE spaces:
H
ARDWARE REFERENCE GUIDE
MICRO-LINE
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 17
CE0 is used for on-board SDRAM
CE1 is used for on-board flash memory , PLD and FPGA registers.
CE2 and CE3 are used for the FPGA
Please refer to chapter 3 for further descriptions of the CE spaces and their address ranges.
2.5.3 Inter Integrated Circuit (I
2
C) Interfaces
The TMS320C6713 DSP provides two I
2
C interfaces. These 2-wire interfaces can be used for
accessing peripherals, like temperature sensors, EEPROMS, A/D and D/A converters, etc. The I
2
C
interfaces are described in detail in [4] and [9].
At the TMS320C6713 DSP, the signals of I
2
C interface #1 are shared with signals of the McBSP
interface #1. Chapter 6.3 shows the shared signals.
By default, the C6713CPU board only provides the I
2
C interface #1 of the TMS320C6713 DSP. If
the I
2
C interface #0 is also needed for a certain application, a slight hardware reconfiguration of the
C6713CPU board is necessary. In this case please contact ORSYS.
2.5.4 General Purpose Input / Output Pins (GPIO)
At the TMS320C6713 DSP a couple of GPIO pins are shared with the Host Port Interface (HPI).
The HPI is enabled by default, therefore the GPIO signals are not available.
Instead of DSP GPIO pins, a number of other software programmable digital I/O pins can be used:
External flags (XF0, XF1)
Timer signals (TINP0, TINP1 TOUT0, TOUT1)
McBSP signals (see [6], chapter "McBSP Pins as General-Purpose I/O")
Free FPGA pins (requires a BSP or custom FPGA design)
2.5.5 Multi-channel Buffered Serial Ports (McBSP)
The TMS320C6713 DSP provides two independent McBSPs. Each port can communicate a full
duplex, continuous data stream at rates up to 75 Mbps. These ports can be used for interprocessor communication as well as for connecting industry standard peripheral devices like audio
codecs, A/D or D/A devices etc.
An implemented multi-channel protocol which provides up to 128 channels additionally opens a
variety of applications such as T1/E1 framers, MVIP framers etc.
The McBSPs are compatible to other standard synchronous serial interfaces from Texas
Instrument's TMS320C2000 or ’C5000 DSP families and can be programmed to be compatible
with many other vendors' synchronous serial interfaces. They consist of the signals DRx (data
receive), DXx (data transmit), CLKRx (clock receive), CLKXx (clock transmit), FSRx (frame sync
receive) and FSXx (frame sync transmit). Additionally the TMS320C6713 DSP supports a CLKSx
(clock source) signal. The 'x' in the signal names represent the port number and are 0 or 1 for
McBSP0 or McBSP1 respectively.
The above mentioned signals can also be used as software controllable digital general purpose
inputs or outputs.
Possible general purpose inputs are: DRx, CLKRx, CLKXx, FSRx, FSXx and CLKSx.
Possible general purpose outputs are: DXx, CLKRx, CLKXx, FSRx and FSXx.
On the TMS320C6713 DSP, the McBSP peripherals share signals with
McASP #0
I
2
C #1
On the C6713CPU board, all McBSP signals are routed to micro-line
®
connectors. Chapter 6.3
contains a detailed listing of connector pin assignments as well as a list of shared signals. Detailed
information how to use the McBSPs can be found in [4] and [6].
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