Type OPR5009 PRELIMINARY
Notes:
1. Pin (+) = 1.2 µW and Pin (-) = 0.8 µW.
2. Pin (+) = 100.0 nW and Pin (-) = 1.0 µW.
3. Pin (+) = 1.0 µW and Pin (-) 100.0 nW.
4. Pin (-) held at 1.0 µW while Pin (+) is ramped from 0.5 µW to 1.5 µW and back to 0.5 µW.
5. Pin (+) modulated from 1.0 µW to 2.0 µW. Pin (-) modulated from 1.0 µW to 2.0 µW with phase shifted 180o with respect to Pin (+). Use 100
kΩ trimpot to set the output signal to 50% duty cycle for maximum operating frequency.
6. Measured between 10% and 90% points.
7. Optical Hysteresis and Optical Offset are found by placing 1.0 µW of light on the inverting photodiode and ramping the light intensity of the
noninverting input from .5 µW up to 1.5 µW and back down. This will produce two trigger points, an upper trigger point and lower trigger point.
These points are used to calculate the optical hysteresis and offset.
These are de fined as:
% Optical Hysteresis = 100 x (P rise - P fall)
P in (-)
% Optical Offset = 100 x (P average - P (-) )
P in (-)
Where:
P in (-) = Light level incident upon the “-” photodiode on the I.C. chip (Pin (-) = 1.0 µW).
P rise = Value of light power level incident upon the “+” photodiode that is required to switch the digital output when the light level is an
increasing level (rising edge).
P fall = Value of light power level incident upon the “+” photodiode that is required to switch the digital output when the light level is a
decreasing level (falling edge).
P average = (P rise + P fall)
2
Elec tri cal Char ac ter is tics (TA = 25o C un less oth er wise noted)
SYM BOL PA RAME TER MIN TYP MAX UNITS TEST CON DI TIONS NOTES
I
CC
Supply Current 9 20 mA VCC = 24 V
V
OL
Low Level Output Voltage 0.3 0.4 V IOL = 14 mA, VCC = 4.5 V 2
I
OH
High Level Output Current 0.1 1.0
µA
VCC = VO = 20.0 V 3
OPT-HYS Optical Hysteresis 2.0 15.0 40 % VCC = 5.0 V, I
OL
= 1.0 mA 4, 7
OPT-OFF Optical Offset -40 10 +40 % VCC = 5.0 V, IOL = 1.0 mA 4, 7
fmax Frequency Response 1.0 MHz VCC = 5.0 V 5
tlh Output Rise Time 1.0
µs
6
thl Output Fall Time 300 ns
Notes:
1. A capacitor of a value between .001 to .01 µF connected as close as possible to the trim terminals is recommended if the device
appears to be susceptable to noise transients. These capacitors will reduce f
max
. It is left to the user to determine the best
value for the application.
2. The 74LS04 is recommended as a means of isolating the “DOC” comparator circuitry from transients induced by inductive and
capacitive loads.
3. It is re com me ded that a de cou pling ca paci tor be placed as close as pos si ble to the de vice.
Ap pli ca tion Cir cuit
Op tek re serves the right to make changes at any time in or der to im prove de sign and to sup ply the best prod uct pos si ble.
Op tek Tech nol ogy, Inc. 1215 W. Crosby Road Car roll ton, Texas 75006 (972)323- 2200 Fax (972)323- 2396
9-25
OPR5009