TIP131, TIP132 (NPN),
TIP137 (PNP)
Preferred Devices
Darlington Complementary
Silicon Power Transistors
Designed for general-purpose amplifier and low-speed switching
applications.
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Features
•High DC Current Gain -
hFE= 2500 (Typ) @ I
= 4.0 Adc
C
•Collector-Emitter Sustaining Voltage - @ 30 mAdc
V
CEO(sus)
= 80 Vdc (Min) - TIP131
= 100 Vdc (Min) - TIP132, TIP137
•Low Collector-Emitter Saturation Voltage -
V
= 2.0 Vdc (Max) @ IC = 4.0 Adc
CE(sat)
= 3.0 Vdc (Max) @ IC = 6.0 Adc
•Monolithic Construction with Built-In Base-Emitter Shunt Resistors
•Pb-Free Packages are Available*
MAXIMUM RATINGS
TIP132
Rating
Collector-Emitter Voltage
Collector-Base Voltage
Emitter-Base Voltage
Collector Current - Continuous
Peak
Base Current
Total Power Dissipation @ TC = 25°C
Total Power Dissipation @ TA = 25°C
Operating and Storage Junction,
Temperature Range
Symbol
V
CEO
V
CB
V
EB
I
C
I
B
P
D
P
D
TJ, T
stg
TIP131
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance,
Junction-to-Case
Thermal Resistance,
Junction-to-Ambient
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Symbol
R
q
JC
R
q
JA
TIP137
80
80
–65 to +150
100
100
5.0
8.0
12
300
70
2.0
Max
1.78
63.5
Unit
Vdc
Vdc
Vdc
Adc
mAdc
W
W
°C
Unit
°C/W
°C/W
DARLINGTON 8 AMPERE
COMPLEMENTARY SILICON
POWER TRANSISTORS
80-100 VOLTS, 70 WATTS
MARKING
DIAGRAM
4
TO-220AB
CASE 221A
1
2
3
TIP13x = Device Code
x = 1, 2, or 7
A = Assembly Location
Y = Year
WW = Work Week
G = Pb-Free Package
STYLE 1
ORDERING INFORMATION
Device Package Shipping
TIP131 TO-220
TIP131G TO-220
TIP132 TO-220 50 Units/Rail
TIP132G TO-220
TIP137 TO-220 50 Units/Rail
TIP137G TO-220
(Pb-Free)
(Pb-Free)
(Pb-Free)
TIP13xG
AYWW
50 Units/Rail
50 Units/Rail
50 Units/Rail
50 Units/Rail
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2007
November, 2007 - Rev. 2
1 Publication Order Number:
Preferred devices are recommended choices for future use
and best overall value.
TIP131/D
TIP131, TIP132 (NPN), TIP137 (PNP)
PNP
COLLECTOR
TIP137
BASE
≈ 8.0 k ≈ 120
EMITTER
Figure 1. Darlington Circuit Schematic
ELECTRICAL CHARACTERISTICS (T
OFF CHARACTERISTICS
Collector-Emitter Sustaining Voltage (Note 1)
(IC = 30 mAdc, IB = 0) TIP131
Collector Cutoff Current
(VCE = 40 Vdc, IB = 0) TIP131
(VCE = 50 Vdc, IB = 0) TIP132, TIP137
Collector Cutoff Current
(VCB = 80 Vdc, IE = 0) TIP131
(VCB = 100 Vdc, IE = 0) TIP132, TIP137
Emitter Cutoff Current
(VBE = 5.0 Vdc, IC = 0)
ON CHARACTERISTICS (Note 1)
DC Current Gain
(IC = 1.0 Adc, VCE = 4.0 Vdc)
(IC = 4.0 Adc, VCE = 4.0 Vdc)
Collector-Emitter Saturation Voltage
(IC = 4.0 Adc, IB = 16 mAdc)
(IC = 6.0 Adc, IB = 30 mAdc)
Base-Emitter On Voltage
(IC = 4.0 Adc, VCE = 4.0 Vdc)
1. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
= 25°C unless otherwise noted)
C
Characteristic
TIP132, TIP137
NPN
TIP131
TIP132
BASE
COLLECTOR
≈ 8.0 k ≈ 120
V
EMITTER
Symbol
CEO(sus)
I
CEO
I
CBO
I
EBO
h
FE
V
CE(sat)
V
BE(on)
Min
80
100
-
-
-
-
-
500
1000
-
-
-
Max
-
-
0.5
0.5
0.2
0.2
5.0
-
15000
2.0
3.0
2.5
Unit
Vdc
mAdc
mAdc
mAdc
-
Vdc
Vdc
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2
1.0
0.7
0.5
0.3
0.2
0.1
0.07
(NORMALIZED)
0.05
0.03
0.02
r(t), TRANSIENT THERMAL RESISTANCE
0.01
0.01
0.2
0.1
0.05
0.02
0.01
D = 0.5
0.02
TIP131, TIP132 (NPN), TIP137 (PNP)
T
T
C
A
80
4.0
60
3.0
T
C
40
2.0
T
20
1.0
, POWER DISSIPATION (WATTS)
D
P
0
0
0 20 40 60 80 100 120 160
Figure 2. Power Derating
SINGLE PULSE
0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 1.0 k500
A
T, TEMPERATURE (°C)
Z
q
JC(t)
R
= 1.78°C/W MAX
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
- TC = P
J(pk)
t, TIME (ms)
= r(t) R
140
P
q
JC
1
Z
q
JC(t)
(pk)
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
2
Figure 3. Thermal Response
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3
TIP131, TIP132 (NPN), TIP137 (PNP)
l
PACKAGE DIMENSIONS
TO-220
CASE 221A-09
ISSUE AE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
SEATING
-T-
PLANE
B
4
Q
123
F
T
A
U
C
S
H
K
Z
L
V
R
J
G
D
N
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MIN MAX MIN MAX
A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.161 3.61 4.09
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.014 0.025 0.36 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 --- 1.15 ---
Z --- 0.080 --- 2.04
MILLIMETERSINCHES
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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TIP131/D
4
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