ON Semiconductor TCC-202 User Manual

TCC-202

Two-Output PTIC Control IC

Introduction

TCC−202 is a two−output high−voltage digital to analog control IC specifically designed to control and bias ON Semiconductor’s Passive Tunable Integrated Circuits (PTICs).

These tunable capacitor control circuits are intended for use in mobile phones and dedicated RF tuning applications. The implementation of ON Semiconductor’s tunable circuits in mobile phones enables significant improvement in terms of antenna radiated performance.

The tunable capacitors are controlled through a bias voltage ranging from 1 V to 24 V. The TCC−202 high−voltage PTIC control IC has been specifically designed to cover this need, providing two independent high−voltage outputs that control up to two different tunable PTICs in parallel. The device is fully controlled through a MIPI interface.

Key Features

• Controls ON Semiconductor’s PTIC Tunable Capacitors

• Compliant with Timing Needs of Cellular and Other Wireless System

Requirements

• Integrated Boost Converter with 2 Programmable DAC Outputs

(up to 24 V)

• Low Power Consumption

• MIPI−RFFE Interface

• Compliant with MIPI 26 MHz Read−back

• Available in WLCSP (RDL ball arrays)

• This is a Pb−Free Device

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WLCSP12

CASE 567KZ

MARKING DIAGRAM

XXXX ALYW

A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information on page 21 o this data sheet.

Typical Applications

• Multi−band, Multi−standard, Advanced and Simple Mobile Phones

• Tunable Antenna Matching Networks

• Compatible with Closed−loop and Open−loop Antenna Tuner

Applications

September, 2016 − Rev. 3

1 Publication Order Number:

TCC−202/D

TCC−202

VDDA

GND

VIO

L_BOOST VHV

VIO

POR

Start

Reference

Interface

Level

Shifter

Booster

Registers

GND_BOOST

vio_on

ibias_start / vref_start

Level

Shifter

OTP

VREG

Regulator

4 bit

DAC

por_vreg

Bandgap

VREG

POR

7 bit

DAC

7 bit

DAC

OSC

OUTA

OUTB

VIO VDDA VREG VHV

CLK DATA

Figure 1. Control IC Functional Block Diagram

ATEST

Figure 2. Die Bump Side View

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TCC−202

RDL Pin Out

Table 1. PAD DESCRIPTIONS

Bump RDL Name Type Description

A1 OUTB AOH High Voltage Output B A2 ATEST AO Analog Test Out (Note 1) A3 VHV AOH/AIH Boost High Voltage A4 L_BOOST AOH Boost Inductor B1 OUTA AOH High Voltage Output A B2 GNDA P Analog Ground B3 GND_BOOST P Ground for Booster B4 VIO Digital IO Supply C1 VREG AO Regulator Output C2 AVDD Analog Supply C3 DATA DIO MIPI RFFE Data C4 CLK DI MIPI RFFE Clock

1. To be grounded when not in use.

Legend: Pad Types

AIH = High Voltage Analog Input AO = Analog Input AOH = High Voltage Analog Input DI = Digital Input DIO = Digital Input/Output (IO) P = Power

ELECTRICAL PERFORMANCE SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Rating Unit

AVDD Analog Supply Voltage −0.3 to +6.0 V

VIO IO Reference Supply Voltage −0.3 to +2.5 V V

I/O

HVH

ESD (HBM)

ESD (MM)

STG

AMB_OP_MAX

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

Input Voltage Logic Lines (DATA, CLK, CS) −0.3 to VIO + 0.3 V VHV Maximum Voltage −0.3 to 30 V Human Body Model, JESD22−A114, All I/O 2,000 V Machine Model, JESD22−A115 200 V Storage Temperature −55 to +150 °C Max Operating Ambient Temperature without Damage +110 °C

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TCC−202

Table 3. RECOMENDED OPERATING CONDITIONS

Rating

Symbol Parameter

AMB_OP

J_OP

Operating Ambient Temperature −30 − +85 °C Operating Junction Temperature −30 − +125 °C

AVDD Analog Supply Voltage 2.3 − 5.5 V

VIO IO Reference Supply Voltage 1.62 − 1.98 V

Min Typ Max

Unit

Table 4. DC CHARACTERISTICS (T

= equivalent series load of 5.6 kW and 2.7 nF; CHV = 47 nF; L

LOAD

Symbol

Parameter Min Typ Max Unit Comment

= −30 to +85°C; V

SHUTDOWN MODE

AVDD

L_BOOST

BATT

VIO

CLK

DATA

AVDD Supply Current − − 1.5 mA L_BOOST Leakage − − 1.5 Battery Current − − 2.5 VIO Supply Current −1 − 1 CLK Leakage −1 − 1 DATA Leakage −1 − 1

ACTIVE MODE

BATT_SS0

BAT_SS2

BATT_SS16

L_BOOST_SS0

L_BOOST_SS2

L_BOOST_SS16

VIO_INACT

VIO_ACTIVE

VREG

Average battery current, 2 outputs @ 0 V steady state

Average battery current, 2 outputs @ 2 V steady state

Average battery current, 2 outputs @ 16 V steady state

Average inductor current, 2 outputs @ 0 V steady state

Average inductor current, 2 outputs @ 2 V steady state

Average inductor current, 2 outputs @ 16 V steady state

VIO average inactive current − − 3 VIO is high, no bus activity VIO average active current − − 250 VIO = 1.8 V, master sending

LOW POWER MODE

AVDD

L_BOOST

BATT

VIO

VREG

AVDD Supply Current − − 8 mA L_BOOST Leakage − − 6 Battery Current − − 14 I VIO Supply Current − − 3 No bus activity

= 15 V for each output; 2.3 V < AVDD < 5.5 V; 1.62 V < VIO < 1.98 V;

OUTX

= 15 mH; unless otherwise specified)

BOOST

VIO Supply is Low

− 380 750

At VHV = 20 V

AVDD = 3.3 V

− 400 780 mA At VHV = 20 V AVDD = 3.3 V

− 510 870 At VHV = 20 V AVDD = 3.3 V

− 260 490 At VHV = 20 V AVDD = 3.3 V

− 280 510 At VHV = 20 V AVDD = 3.3 V

− 400 600 At VHV = 20 V AVDD = 3.3 V

data at 26 MHz

1.7 − 1.9 V No external load allowed

+ I

AVDD

L_BOOST

1.6 − 1.9 V No external load allowed

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TCC−202

Table 5. BOOST CONVERTER CHARACTERISTICS

(AVDD from 2.3 V to 5.5 V; VIO from 1.62 V to 1.98 V; TA = –30 to +85°C; CHV = 47 nF; L

Symbol

VHV_min Minimum programmable output volt-

Parameter Conditions Min Typ Max Unit

Active mode − 13 −

age (average), DAC Boost = 0h

VHV_max Maximum programmable output volt-

Active mode − 28 −

age (average), DAC Boost = Fh

Resolution Boost voltage resolution 4−bit DAC − 1 −

L_BOOST_LIMIT

Inductor current limit − 200 − mA

Table 6. ANALOG OUTPUTS (OUT A, OUT B)

(AVDD from 2.3 V to 5.5 V; VIO from 1.62 V to 1.98 V; VHV = 26 V; TA = –30 to +85°C; Rload = ∞ unless otherwise specified)

Parameter

SHUTDOWN MODE

OUT

OUT A, OUT B output impedance 7 − −

ACTIVE MODE

Maximum output voltage − 23.8 − V DAC A, B = 7Fh,

Minimum output voltage − − 1 V DAC A, B = 01h, DAC

Slew Rate − 3 10

OUT A, OUT B set in pull−down mode

Resolution Voltage resolution (1−bit) − 188 − mV (1 LSB = 1−bit)

OFFSET

Zero scale, least squared best fit −1 − +1 LSB

Error −3.0 − +3.0 %V

DNL Differential non−linearity least

squared best fit

INL Integral non−linearity least squared

best fit

RIPPLE

Over current protection − 5 65 mA Any DAC output shorted to ground Output ripple with all outputs at

steady state

Description Min Typ Max Unit Comment

− − 1000

−0.9 − +0.9 LSB Over 2 V – 24 V VO range

−1 − +1 LSB Over 2 V – 24 V VO range

− − 40 mV RMS Over 2 V – 24 V for VHV = 23.5 V

= 15 mH; unless otherwise specified)

BOOST

DAC disabled

DAC Boost = Fh, I

Boost = 0h to Fh, I

2 V to 24 V step, measured at V

= 15.2 V,

OUT

= equivalent series load of

LOAD

2.7 kW and 5.6 nF, Turbo enabled DAC A, B = 00h, DAC Boost = 0h to

Fh, selected output(s) is disabled

OUT

Over 2 V – 24 V VO range

< 10 mA

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TCC−202

THEORY OF OPERATION

Overview

The control IC outputs are directly controlled by programming the two DACs (DAC A and DAC B) through the digital interface.

The DAC stages are driven from a reference voltage, generating an analog output voltage driving a high−voltage amplifier supplied from the boost converter (see Figure 1 − Control IC Functional Block Diagram).

The control IC output voltages are scaled from 0 V to 24 V, with 128 steps of 188 mV (2x (24 / 255 V) =

0.188235 V). The nominal control IC output can be approximated to 188 mV x DAC value.

For performance optimization the boost output voltage (VHV) can be programmed to levels between 13 V and 28 V via the DAC_boost register (4 bits with 1 V steps). The startup default level for the boosted voltage is VHV = 24 V.

For proper operation and to avoid saturation of the output devices and noise issues it is recommended to operate the boosted VHV voltage at least 2 V above the highest programmed V

Operating Modes

voltage of any of the two outputs.

OUT

The following operating modes are available:

1. Shutdown Mode: All circuit blocks are off, the

DAC outputs are disabled and placed in high Z state and current consumption is limited to minimal leakage current. The shutdown mode is entered upon initial application of AVDD or upon VIO being placed in the low state. The contents of the registers are not maintained in shutdown mode.

2. Startup Mode: Startup is only a transitory mode.

Startup mode is entered upon a VIO high state. In

startup mode all registers are reset to their default states, the digital interface is functional, the boost converter is activated, outputs OUT A and OUT B are disabled and the DAC outputs are placed in a high Z state. Control software can request a full hardware and register reset of the TCC−202 by sending an appropriate PWR_MODE command to direct the chip from either the active mode or the low power mode to the startup mode. From the startup mode the device automatically proceeds to the active mode.

3. Active Mode: All blocks of the TCC−202 are

activated and the DAC outputs are fully controlled through the digital interface, DACs remain off until enabled. The DAC settings can be dynamically modified and the HV outputs will be adjusted according to the specified timing diagrams. Each DAC can be individually controlled and/or switched off according to application requirements. Active mode is automatically entered from the startup mode. Active mode can also be entered from the low power mode under control software command.

4. Low Power Mode: In low power mode the serial

interface stays enabled, the DAC outputs are disabled and are placed in a high Z state and the boost voltage circuit is disabled. Control software can request to enter the low power mode from the active mode by sending an appropriate PWR_MODE command. The contents of all registers are maintained in the low power mode.

VDDA = 0

Shutdown

VIO = LOW

(User Defined)

Battery insertion

VIO = HIGH

PWR_MODE =

VIO = LOW

PWR_MODE = 0b00

Low Power

PWR_MODE = 0b10

Figure 3. Modes of Operation

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Startup

(Registers reset)

0b01

PWR_MODE =

0b01

automatic

Active

(User Defined)

TCC−202

AVDD Power−On Reset (POR)

Upon application of AVDD the TCC−202 will be in shutdown mode. All circuit blocks are off and the chip draws only minimal leakage current.

VIO Power−On Reset and Startup Conditions

A high level on VIO places the chip in startup mode which provides a POR to the TCC−202. POR resets all registers to their default settings as described in T able 8. VIO POR also resets the serial interface circuitry . POR is not a brown−out detector and VIO needs to be brought back to a low level to enable the POR to trigger again.

Table 7. VIO POWER−ON RESET AND STARTUP

Default State for

DAC Boost [1011] VHV = 24 V Power Mode [01]>[00] Transitions from shutdown to startup and then automatically to active mode DAC Enable [000000] V

DAC A Output in High−Z Mode DAC B Output in High−Z Mode

VIO POR

A, B Disabled

OUT

Comment

VIO Shutdown

A low level at any time on VIO places the chip in shutdown mode in which all circuit blocks are off. The contents of the

registers are not maintained in shutdown mode.

Table 8. VIO THRESHOLDS (AVDD from 2.3 V to 5.5 V; T

Parameter

VIORST VIO Low Threshold − − 0.2 V When VIO is lowered below this threshold level the

Description Min Typ Max Unit Comments

= –30 to +85°C unless otherwise specified)

chip is reset and placed into the shutdown state

Power Supply Sequencing

The AVDD input i s typically d irectly s upplied f rom t he b attery a nd t hus i s t he f irst o n. A fter AVDD is applied a nd b efore V IO is applied to the chip, all circuits are in the shutdown state and draw minimum leakage currents. Upon application of VIO, the chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface.

Table 9. TIMING (AVDD from 2.3 V to 5.5 V; VIO from 1.62 V to 1.98 V; T

= 15 mH; VHV = 24 V; Turbo−Charge mode off unless otherwise specified; VDDA = 1.7 V)

Parameter

POR_VREG

BOOST_START

SD_TO_ACT

SET+

SET−

SET+

SET−

Internal bias settling time from shutdown to active mode − 50 120 Time to charge CHV @ 80% of set VHV

(set to 24 V, V Startup time from shutdown to active mode − 180 300 Output A, B positive settling time to within 5% of the

delta voltage, equivalent series load of 5.6 kW and 2.7 nF, V

Output A, B negative settling time to within 5% of the delta voltage, equivalent series load of 5.6 kW and 2.7 nF, V

Output A, B positive settling time with Turbo − 35 −

Output A, B negative settling time with Turbo − 35 −

from 2 V to 20 V; 0Bh (11d) to 55h (85d)

OUT

from 20 V to 2 V; 55h (85d) to 0Bh (11d)

OUT

Description Min Typ Max Unit Comments

= 2.7 V)

DDA

= –30 to +85°C; OUT A and OUT B; CHV = 47 nF; L

For info only For info only

Voltage settling time

connected on V

A, B

Voltage settling time

connected on V

A, B

Voltage settling time

connected on V

A, B

Voltage settling time

connected on V

A, B

− 130 −

− 50 60

ms ms

BOOST

OUT

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TCC−202

Figure 5. Startup Timing Diagram

Figure 4. Output Settling Diagram

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