ON Semiconductor RHYTHM SA3229 User Manual

Preconfigured DSP System for Hearings Aids

RHYTHM SA3229

Description

The RHYTHMt SA3229 hybrid from ON Semiconductor is a trimmer−configurable DSP system based on a four−channel compression circuit featuring a feedback cancellation algorithm.

Based on a phase cancellation method, SA3229’s adaptive feedback reduction algorithm provides added stable gain to enable extra gain and user comfort. It features rapid adjustment for dynamic feedback situations and resistance to tonal inputs.

In addition to these adaptive algorithms, SA3229 also supports the following features: up to four channel WDRC, low−distortion compression limiting, cross fading between audio paths for click−free memory changes, eight−band graphic equalizer, eight configurable generic biquad filters, programming speed enhancements, in−channel squelch to attenuate microphone and circuit noise in quiet environments, optional peak clipping, flexible compression adjustments, volume control, rocker switch, noise generation for Tinnitus treatment, and industry−leading security features to avoid cloning and software piracy.

A trimmer interface supports manual circuit configuration. It continuously monitors trimmer positions and translates them into the hearing−aid parameters of choice. A Serial Data or I provides full programmability at the factory and in the field.

RHYTHM SA3229 is a single−chip hybrid with a one−time programmable (OTP) memory intended for low cost applications requiring high gain.

Features

• Adaptive Feedback Cancellation

• WDRC Compression with Choice of 1, 2 or 4 Channels of

Compression

• Auto Telecoil with Programmable Delay

• EVOKE Acoustic Indicators

• Noise Generator for Tinnitus Treatment or In−Situ Audiometry

• Frequency Response Shaping with Graphic EQ

• Trimmer Compatibility – Four Three−Terminal Trimmers with

Configurable Assignments of Control Parameters

• I

C and SDA Programming

• Rocker Switch Support for Memory Change and/or Volume Control

Adjustment

• Support for Active High or Active Low Switching

• Analog or Digital Volume Control with Programmable Range

• High Quality 20−bit Audio Processing

• High Power/High Gain Capability

• Configurable Low Battery Indicator

C Interface

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SIP25

HYBRID

CASE 127DZ

PAD CONNECTION

VIN2

D_VC

SDA

CLK

MS1

See detailed ordering and shipping information on page 13 of this data sheet.

TIN

DAI

MARKING DIAGRAM

SA3229 = Specific Device Code E1 = RoHS Compliant Hybrid XXXXXX = Work Order Number

ORDERING INFORMATION

VIN1

TR4

TR3

TR2

TR1

N/C

25 24

N/C

MS2

(Bottom View)

SA3229−E1

XXXXXX

N/C

VREG

MGND

GND

PGND

OUT+

OUT−

VBP

8910

March, 2021 − Rev. 4

1 Publication Order Number:

SA3229/D

RHYTHM SA3229

• Eight Biquadratic Filters

• 16 kHz or 8 kHz Bandwidth

• Four Fully Configurable Memories with Audible

Memory Change Indicator

• 96 dB Input Dynamic Range with Headroom Extension

• 128−bit Fingerprint Security System and Other Security

Features to Protect Against Device Cloning and Software Piracy

BLOCK DIAGRAM

MS2

VREG

MIC1

MIC2

TIN

DAI

MGND

SA3229

REGULATOR

A/D

910

MIC / TELECOIL

COMPENSATION

D_VC

MS1

TRIMMER/VC INTERFACE

SDA CLK

12 11

PROGRAMMING

INTERFACE

PRE BIQUAD FILTERS

22 20 19

1−4

1, 2 or 4 CHANNEL

WDRC

POST BIQUAD FILTERS

1 & 2

TR4TR3TR2TR1

• High Fidelity Audio CODEC

• Soft Acoustic Fade between Memory Changes

• Drives Zero−Bias Two−Terminal Receivers

• E1 RoHS−compliant Hybrid

• Hybrid Typical Dimensions:

0.225 x 0.125 x 0.045 in (5.72 x 3.18 x 1.14 mm)

• These Devices are Pb−Free and are RoHS Compliant

FEEDBACK

CANCELLER

POST BIQUAD FILTERS

3 & 4

AGC−O

VC GAIN

WIDEBAND GAIN

NOISE GENERATOR

TONE

GENERATOR

BIQUAD 1−4

CROSS FADER

EVOKE

PEAK

CLIPPING

GND

D/A HBRIDGE

VBP

OUT+

OUT −

PGND

Figure 1. Hybrid Block Diagram

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RHYTHM SA3229

SPECIFICATIONS

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Value Units

Operating Temperature Range 0 to +40 °C

Storage Temperature Range −20 to +70 °C

Absolute Maximum Power Dissipation 25 mW

Maximum Operating Supply Voltage 1.65 VDC

Absolute Maximum Supply Voltage 1.8 VDC

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

WARNING: Electrostatic Sensitive Device − Do not open packages or handle except at a static−free workstation.

WARNING: Moisture Sensitive Device − RoHS Compliant; Level 3 MSL. Do not open packages except under controlled conditions.

Table 2. ELECTRICAL CHARACTERISTICS (Supply Voltage V

Parameter

Hybrid Current I

Symbol Conditions Min Typ Max Units

AMP

All functions, 32 kHz sampling rate − 640 − mA

= 1.25 V; Temperature = 25°C)

All functions, 16 kHz sampling rate − 535 −

Minimum Operating Supply Voltage V

BOFF

Ramp down, audio path 0.93 0.95 0.97

Ramp down, control logic 0.77 0.80 0.83

Supply Voltage Turn On Threshold V

BON

Ramp up 1.06 1.10 1.16 V

Low Frequency System Limit − − − 125 − Hz

High Frequency System Limit − − − 16 − kHz

Total Harmonic Distortion THD VIN = −40 dBV − − 1 %

THD at Maximum Input THD

Clock Frequency f

CLK

Audio Path Latency

− 8 kHz bandwidth − 4.2 −

VIN = −15 dBV, Headroom Extension

− ON

− 3.973 4.096 4.218 MHz

− − 3 %

− 16 kHz bandwidth − 4.0 −

System Power On Time (Note 1) − SA3229 − 700 − ms

REGULATOR

Regulator Voltage

REG

System PSRR PSRR

SYS

1 kHz, Input referred, Headroom

Extension enabled

− 0.87 0.90 0.93 V

− 70 − dB

INPUT

Input Referred Noise

IRN Bandwidth 100 Hz − 8 kHz,

− −108 −106 dBV

Headroom Extension on

Input Impedance Z

Anti−aliasing Filter Rejection − f = f

CLK/2

1 kHz − 3 −

− 8 kHz, VIN = −40 dBV − 80 − dB

Crosstalk − Between both A/D and Mux − 60 − dB

Maximum Input Level − − −15 −13 − dBV

Analogue Input Voltage Range

AN_IN

AN_TIN

, V

, Al 0 − 800

IN1

IN2

Input Dynamic Range − Headroom Extension − ON

−100 − 800

− 95 96 dB

Bandwidth

100 Hz − 8 kHz

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RHYTHM SA3229

Table 2. ELECTRICAL CHARACTERISTICS (Supply Voltage V

= 1.25 V; Temperature = 25°C) (continued)

Parameter UnitsMaxTypMinConditionsSymbol

OUTPUT

D/A Dynamic Range

Output Impedance Z

− 100 Hz − 8 kHz − 88 − dB

OUT

− − 10 13

CONTROL A/D

Resolution (monotonic)

− − 7 − − bits

Zero Scale Level − − − 0 − V

Full Scale Level − − − V

REG

− V

VOLUME CONTROL

Volume Control Resistance

Three−terminal connection 100 − 360

Volume Control Range − − − − 42 dB

PC_SDA INPUT

Logic 0 Voltage

− − 0 − 0.3 V

Logic 1 Voltage − − 1 − 1.25 V

PC_SDA OUTPUT

Stand−by Pull Up Current

Sync Pull Up Current − Creftrim = 6 748 880 1020

Max Sync Pull Up Current − Creftrim = 15 − 1380 −

Min Sync Pull Up Current − Creftrim = 0 − 550 −

Logic 0 Current (Pull Down) − Creftrim = 6 374 440 506

Logic 1 Current (Pull Up) − Creftrim = 6 374 440 506

Synchronization Time (Synchronization Pulse Width)

− Creftrim = 6 3 5 6.5

SYNC

Baud = 0 237 250 263 ms

Baud = 1 118 125 132

Baud = 2 59 62.5 66

Baud = 3 29.76 31.25 32.81

Baud = 4 14.88 15.63 16.41

Baud = 5 7.44 7.81 8.20

Baud = 6 3.72 3.91 4.10

Baud = 7 1.86 1.95 2.05

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. Times do not include additional programmable startup delay.

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RHYTHM SA3229

Table 3. I2C TIMING

Standard Mode Fast Mode

Parameter Symbol

Clock Frequency f

Hold time (repeated) START condition. After this period, the first clock pulse is generated.

LOW Period of the PC_CLK Clock t

HIGH Period of the PC_CLK Clock t

Set−up time for a repeated START condition t

Data Hold Time:

for CBUS Compatible Masters

PC_CLK

HD;STA

LOW

HIGH

SU;STA

HD;DAT

for I2C−bus Devices

Data set−up time t

Rise time of both PC_SDA and PC_CLK signals t

Fall time of both PC_SDA and PC_CLK signals t

Set−up time for STOP condition t

Bus free time between a STOP and START condition t

Output fall time from V capacitance from 10 pF to 400 pF

IHmin

to V

ILmax

with a bus

Pulse width of spikes which must be suppressed by the input filter

Capacitive load for each bus line C

SU;DAT

SU;STO

BUF

1. A device must internally provide a hold time of at least 300 ns for the PC_SDA signal to bridge the undefined region of the falling edge of PC_CLK.

2. The maximum t

3. A Fast−mode I

has only to be met if the device does not stretch the LOW period (t

HD;DAT

C−bus device can be used in a Standard−mode I2C−bus system, but the requirement t This will automatically be the case if the device does not stretch the LOW period of the PC_CLK signal. If such a device does stretch the LOW period of the PC_CLK signal, it must output the next data bit to the PC_SDA line t to the Standard−mode I

= total capacitance of one bus line in pF.

4. C

C−bus specification) before the PC_CLK line is released.

Min Max Min Max

0 100 0 400 kHz

4.0 − 0.6 −

4.7 − − −

4.0 − − −

4.7 − − −

5.0 0

(Note 1)

−

3.4

(Note 2)

−

(Note 1)

−

0.9

(Note 2)

250 − 100 − nsec

− 1000 20 + 0.1 C

(Note 4)

− 300 20 + 0.1 C

(Note 4)

300 nsec

4.0 − 0.6 − nsec

4.7 − 1.3 −

− 250 20 + 0.1 C

(Note 4)

250 nsec

n/a n/a 0 50 nsec

− 400 − 400 pF

) of the PC_CLK signal.

LOW

max + t

SU;DAT

P250ns must then be met.

SU;DAT

= 1000 + 250 = 1250 ns (according

Units

msec

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