Page 1
MOSFET - Power, Single
N-Channel
80 V, 20 mW, 30 A
NVTFS6H860NL
Features
• Small Footprint (3.3 x 3.3 mm) for Compact Design
• Low R
• Low Capacitance to Minimize Driver Losses
• NVTFS6H860NLWF − Wettable Flanks Product
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain
Current R
(Notes 1, 2, 3, 4)
Power Dissipation
(Notes 1, 2, 3)
R
q
JC
Continuous Drain
Current R
(Notes 1, 3, 4)
Power Dissipation
(Notes 1, 3)
R
q
JA
Pulsed Drain Current
Operating Junction and Storage Temperature
Range
Source Current (Body Diode) I
Single Pulse Drain−to−Source Avalanche
Energy (I
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Junction−to−Case − Steady State (Note 3)
Junction−to−Ambient − Steady State (Note 3)
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
to Minimize Conduction Losses
DS(on)
= 25°C unless otherwise noted)
J
Parameter
TC = 25°C
TC = 100°C 21
TC = 25°C
TC = 100°C 21
TA = 25°C
TA = 100°C 5.7
TA = 25°C
TA = 100°C 1.6
q
JC
q
JA
L(pk)
Steady
State
Steady
State
TA = 25°C, t
= 1.5 A)
Parameter
= 10 ms
p
Symbol Value Unit
stg
80 V
±20 V
30
42
8.1
3.1
122 A
−55 to
+175
35 A
121 mJ
260 °C
3.6
48
A
W
A
W
°C
°C/W
DSS
GS
I
D
P
D
I
D
P
D
I
DM
TJ, T
S
E
AS
T
L
Symbol Value Unit
R
q
JC
R
q
JA
2
, 2 oz. Cu pad.
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V
(BR)DSS
80 V
G (4)
R
MAX ID MAX
DS(ON)
20 mW @ 10 V
26 mW @ 4.5 V
N−Channel
D (5 − 8)
30 A
S (1, 2, 3)
MARKING
DIAGRAMS
1
WDFN8
(m8FL)
CASE 511AB
WDFNW8
(Full−Cut m8FL)
CASE 515AN
XXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
1
S
XXXX
S
AYWWG
S
G
G
XXXX
AYWWG
G
D
D
D
D
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2019
November, 2020 − Rev. 1
1 Publication Order Number:
NVTFS6H860NL/D
Page 2
NVTFS6H860NL
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise noted)
J
Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
(BR)DSS
DSS
GSS
VGS = 0 V, ID = 250 mA
VGS = 0 V,
V
= 80 V
DS
TJ = 25°C 10 mA
TJ = 125°C 100
VDS = 0 V, VGS = 20 V 100 nA
80 V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage V
Threshold Temperature Coefficient V
GS(TH)/TJ
Drain−to−Source On Resistance R
Forward Transconductance g
GS(TH)
DS(on)
FS
VGS = VDS, ID = 30 mA
VGS = 10 V ID = 5 A 16.5 20
VGS = 4.5 V ID = 5 A 20.5 26
VDS = 8 V, ID = 15 A 45 S
1.2 2.0 V
−5.1 mV/°C
mW
mW
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
Plateau Voltage V
Total Gate Charge Q
C
ISS
OSS
RSS
G(TOT)
G(TH)
GS
GD
GP
G(TOT)
VGS = 0 V, f = 1 MHz, VDS = 40 V
VGS = 10 V, VDS = 40 V; ID = 15 A 12
VGS = 4.5 V, VDS = 40 V; ID = 15A
610
83
5
1
2
2
3 V
6 nC
pF
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
t
Rise Time t
Turn−Off Delay Time t
d(OFF)
Fall Time t
d(ON)
r
f
VGS = 4.5 V, VDS = 64 V,
= 15 A, RG = 2.5 W
I
D
32
14
8
ns
5
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage V
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
RR
SD
a
b
RR
VGS = 0 V,
I
= 5 A
S
VGS = 0 V, dIS/dt = 100 A/ms,
I
= 15 A
S
TJ = 25°C 0.80 1.2
TJ = 125°C 0.66
29
18
11
21 nC
V
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
Page 3
NVTFS6H860NL
TYPICAL CHARACTERISTICS
30
25
20
15
10
, DRAIN CURRENT (A)
D
I
5
0
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
45
40
35
30
25
20
15
10
5
, DRAIN−TO−SOURCE RESISTANCE (mW)
DS(on)
R
0
4
3
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
3.4 V
6
Voltage
VGS = 10 V to 3.6 V
3210
TJ = 25°C
= 5 A
I
D
975
3.2 V
3.0 V
2.8 V
2.6 V
30
25
20
15
10
, DRAIN CURRENT (A)
D
I
5
0
24
22
20
18
16
14
, DRAIN−TO−SOURCE RESISTANCE (mW)
108
12
DS(on)
R
TJ = 25°C
TJ = 25°C
TJ = 125°C
1.5 3.5
1.00.554
23
TJ = −55°C
3.02.00
2.5 4.0
VGS = 4.5 V
VGS = 10 V
4
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
51
, NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
DS(on)
R
2.5
2.0
1.5
1.0
0.5
100
VGS = 10 V
= 5 A
I
D
, LEAKAGE (nA)
DSS
I
50
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
150
0.0001
17512510075250−25−50
Figure 5. On−Resistance Variation with
Temperature
10
0.1
0.01
0.001
TJ = 175°C
TJ = 150°C
1
TJ = 125°C
TJ = 85°C
TJ = 25°C
25
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
554535155
7565
Page 4
NVTFS6H860NL
TYPICAL CHARACTERISTICS
10K
1K
100
10
C, CAPACITANCE (pF)
1
100
t
d(off)
10
t
t, TIME (ns)
d(on)
10
9
C
ISS
8
7
6
C
OSS
5
Q
4
GS
Q
GD
3
VGS = 0 V
= 25°C
T
J
f = 1 MHz
30
C
RSS
60504010 200
8070 2
2
, GATE−TO−SOURCE VOLTAGE (V)
1
GS
0
V
4
VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
5
VGS = 0 V
t
r
860
VDS = 40 V
= 15 A
I
D
T
= 25°C
J
1210
t
f
1
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
1000
TA = 25°C
Single Pulse
VGS ≤ 10 V
100
10
, DRAIN CURRENT (A)
1
D
I
0.1
VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area Figure 12. Maximum Drain Current vs. Time in
vs. Gate Resistance
Limit
R
DS(on)
Thermal Limit
Package Limit
101
VGS = 4.5 V
= 64 V
V
DS
I
= 15 A
D
10 ms
1 ms
0.5 ms
10 ms
1000.1
50101
1000
, SOURCE CURRENT (A)
S
I
1
TJ = 125°C
0.3
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
Figure 10. Diode Forward Voltage vs. Current
100
10
(A)
PEAK
I
T
1
0.1
0.00001
J(initial)
= 100°C
0.0001 0.001 0.01
TJ = 25°C
T
Avalanche
J(initial)
= 25°C
TJ = −55°C
0.90.80.70.60.50.4
1.0
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4
Page 5
100
†
10
1
R(t) (°C/W)
0.1
NVTFS6H860NL
TYPICAL CHARACTERISTICS
50% Duty Cycle
20%
10%
5%
2%
1%
Single Pulse
0.01
0.010.001 10000.0001 0.10.000010.000001
PULSE TIME (sec)
1 10 100
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device Marking Package Shipping
NVTFS6H860NLTAG 860L WDFN8
(Pb−Free)
NVTFS6H860NLWFTAG 60LW WDFN8
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1500 / Tape & Reel
1500 / Tape & Reel
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5
Page 6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
0.05
E2
G
0.10 C
0.10 C
8X
C
A0.10 B
C
4X
E3
1234
TOP VIEW
SIDE VIEW
b
L
14
8
BOTTOM VIEW
78
D
D1
D2
56
5
2X
E1
e/2
K
C
0.20
A
B
E
A
DETAIL A
M
L1
2X
0.20 C
c
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
4X
q
A1
6X
e
DETAIL A
C
SEATING
PLANE
0.75
DATE 23 APR 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
DIM MIN NOM
MILLIMETERS
A 0.70 0.75
A1 0.00 −−−
b 0.23 0.30
c 0.15 0.20
D
D1 2.95 3.05
D2 1.98 2.11
E
E1 2.95 3.05
E2 1.47 1.60
E3 0.23 0.30 0.40
e 0.65 BSC
G 0.30 0.41
K 0.65 0.80
L 0.30 0.43
L1 0.06 0.13
M 1.40 1.50
q 0 −−−
3.30 BSC
3.30 BSC
_
MAX
0.80
0.05
0.40
0.25
3.15
2.24
3.15
1.73
0.51
0.95
0.56
0.20
1.60
12
_
INCHES
MIN NOM
0.028 0.030
0.000 −−−
0.009 0.012
0.006 0.008
0.130 BSC
0.116 0.120
0.078 0.083
0.130 BSC
0.116 0.120
0.058 0.063
0.009 0.012 0.016
0.026 BSC
0.012 0.016
0.026 0.032
0.012 0.017
0.002 0.005
0.055 0.059
0 −−−
_
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.020
0.037
0.022
0.008
0.063
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
0.57
8X
0.650.42
PITCH
2.30
4X
0.66
3.60
12
_
GENERIC
MARKING DIAGRAM*
1
XXXXX
AYWWG
G
XXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON30561E
WDFN8 3.3X3.3, 0.65P
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
0.47
2.37
3.46
DIMENSION: MILLIMETERS
PAGE 1 OF 1
© Semiconductor Components Industries, LLC, 2019
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Page 7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
CASE 515AN
ISSUE O
DATE 25 AUG 2020
GENERIC
MARKING DIAGRAM*
XXXX
AYWWG
G
DOCUMENT NUMBER:
98AON24556H
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
XXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
PAGE 1 OF 1WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
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Page 8
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