MOSFET - Power, Single
N-Channel, m8FL
60 V, 20.3 mW, 27 A
NVTFS020N06C
Features
• Small Footprint (3.3 x 3.3 mm) for Compact Design
• Low R
• Low Q
• NVTFWS020N06C − Wettable Flank Option for Enhanced Optical
Inspection
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Power Tools, Battery Operated Vacuums
• UAV/Drones, Material Handling
• BMS/Storage, Home Automation
to Minimize Conduction Losses
DS(on)
and Capacitance to Minimize Driver Losses
G
V
(BR)DSS
60 V
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R
DS(on)
20.3 mW @ 10 V
N−Channel
D (5 − 8)
G (4)
MAX ID MAX
27 A
MAXIMUM RATINGS (T
Parameter Symbol Value Unit
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain
Current R
(Notes 1, 3)
Power Dissipation
R
q
JC
Continuous Drain
Current R
(Notes 1, 2, 3)
Power Dissipation
R
q
JA
Pulsed Drain Current
Operating Junction and Storage Temperature
Range
Source Current (Body Diode) I
Single Pulse Drain−to−Source Avalanche
Energy (I
Lead Temperature Soldering Reflow for Soldering Purposes (1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
q
JC
(Note 1)
q
JA
(Notes 1, 2)
= 5.7 A)
L(pk)
= 25°C unless otherwise noted)
J
TC = 25°C
Steady
State
Steady
State
TA = 25°C, t
TC = 100°C 19
TC = 25°C
TC = 100°C 15
TA = 25°C
TA = 100°C 5
TA = 25°C
TA = 100°C 1.2
= 10 ms
p
P
P
I
TJ, T
E
2
, 2 oz. Cu pad.
DSS
GS
I
D
D
I
D
D
DM
S
AS
T
L
stg
60 V
±20 V
27
31
7
2.5
128 A
−55 to
+175
25 A
17 mJ
260 °C
A
W
A
W
°C
S (1, 2, 3)
MARKING
DIAGRAMS
1
WDFN8
(m8FL)
CASE 511AB
WDFNW8
(Full−Cut m8FL)
CASE 515AN
XXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
1
S
XXXX
S
AYWWG
S
G
G
XXXX
AYWWG
G
D
D
D
D
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2020
November, 2020 − Rev. 1
1 Publication Order Number:
NVTFS020N06C/D
NVTFS020N06C
THERMAL RESISTANCE RATINGS
Parameter Symbol Value Unit
Junction−to−Case − Steady State (Note 4)
Junction−to−Ambient − Steady State (Note 4)
4. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
R
q
JC
R
q
JA
4.8
59.7
°C/W
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise noted)
J
Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
V
(BR)DSS/TJ
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
(BR)DSS
DSS
GSS
VGS = 0 V, ID = 250 mA
ID = 250 mA, referenced to 25°C
VGS = 0 V,
V
= 60 V
DS
TJ = 25°C 10 mA
TJ = 125°C 250
VDS = 0 V, VGS = 20 V 100 nA
60 V
29 mV/°C
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Treshold Temperature
Coefficient
V
GS(TH)
V
GS(TH)/TJ
Drain−to−Source On Resistance R
Forward Transconductance g
Gate−Resistance R
DS(on)
FS
G
VGS = VDS, ID = 20 mA
ID = 20 mA, referenced to 25°C
VGS = 10 V, ID = 4 A 16.9 20.3
VDS = 5 V, ID = 4 A 12 S
TA = 25°C 1.0
2.0 4.0 V
−7.8 mV/°C
mW
W
CHARGES AND CAPACITANCES
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
C
iss
oss
rss
G(TOT)
G(TH)
GS
GD
VGS = 0 V, f = 1 MHz,
V
= 30 V
DS
VGS = 10 V, VDS = 48 V, ID = 4 A
355
260
4.9
5.8
1.4
2.3
0.53
pF
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
t
Rise Time t
Turn−Off Delay Time t
Fall Time t
d(on)
d(off)
6.5
r
f
VGS = 10 V, VDS = 48 V,
= 4 A, RG = 6 W
I
D
1.4
9.7
4.0
ns
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
VGS = 0 V,
IS = 4 A
RR
a
b
RR
VGS = 0 V, dlS/dt = 100 A/ms,
V
= 30 V, IS = 4 A
DS
TJ = 25°C 0.81 1.2
TJ = 125°C 0.67
24
12
12
12 nC
V
ns
5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
NVTFS020N06C
TYPICAL CHARACTERISTICS
70
60
50
40
30
20
, DRAIN CURRENT (A)
D
I
10
0
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
22
21
20
19
18
VGS = 10 V to 7 V
3.02.52.01.51.00.50
TJ = 25°C
= 4 A
I
D
6.0 V
5.0 V
4.5 V
3.6 V
35
30
25
20
15
10
, DRAIN CURRENT (A)
D
I
5
0
20
19
18
17
1.00.55.04.54.03.5
TJ = 25°C
TJ = −55°C
TJ = 25°C
TJ = 125°C
3.02.00 4.5 5.0
1.5 3.5
2.5 4.0
VGS = 10 V
17
, DRAIN−TO−SOURCE RESISTANCE (mW)
16
DS(on)
R
, NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
DS(on)
R
7.5
7.0
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
8.5
9.08.0
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2.5
2.0
1.5
1.0
0.5
0
VGS = 10 V
= 4 A
I
D
50
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
150
, DRAIN−TO−SOURCE RESISTANCE (mW)
109.5
DS(on)
R
100K
, LEAKAGE (nA)
DSS
I
17512510075250−25−50
16
15
16 24 28
20 321284
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
TJ = 175°C
10K
TJ = 150°C
1K
TJ = 125°C
100
TJ = 85°C
10
TJ = 25°C
1
0.1
25
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
554535155
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3
NVTFS020N06C
TYPICAL CHARACTERISTICS
10K
1K
100
10
C, CAPACITANCE (pF)
VGS = 0 V
T
f = 1 MHz
1
100
VGS = 10 V
V
DS
I
D
t
d(off)
10
t
d(on)
t, TIME (ns)
1
10
9
8
C
C
ISS
OSS
7
Q
6
Q
GS
GD
5
4
3
= 25°C
J
30
C
RSS
60504010 200
2
, GATE−TO−SOURCE VOLTAGE (V)
1
GS
0
V
2
3
VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
= 48 V
= 4 A
t
f
t
r
, SOURCE CURRENT (A)
S
I
VGS = 0 V
1
VDS = 48 V
= 4 A
I
D
T
= 25°C
J
5410
6
7
0.1
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
TA = 25°C
Single Pulse
100
VGS ≤ 10 V
10
1
, DRAIN CURRENT (A)
D
I
0.1
VDS, DRAIN−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area Figure 12. Maximum Drain Current vs. Time in
vs. Gate Resistance
Limit
R
DS(on)
Thermal Limit
Package Limit
101
1 sec
10 ms
100 ms
1 ms
100101
10 ms
100 ms
100
100
(A)
PEAK
I
0.1
TJ = 125°C
TJ = 25°C
0.3
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
Figure 10. Diode Forward Voltage vs. Current
T
= 25°C
J(initial)
10
T
= 100°C
J(initial)
1
0.000001
0.00001 0.0001 0.001 0.01
Avalanche
TJ = −55°C
0.90.80.70.60.50.4
1.0
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4
100
†
10
(°C/W)
JA
q
Z
0.1
1
NVTFS020N06C
TYPICAL CHARACTERISTICS
50% Duty Cycle
20%
10%
5%
2%
1%
Single Pulse
0.01
0.010.001 10.0001 0.10.00001 100.000001
PULSE TIME (sec)
100 1000
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device Marking Package Shipping
NVTFS020N06CTAG 20NC
NVTFWS020N06CTAG 20NW
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
m8FL
(Pb−Free)
m8FL
1500 / Tape & Reel
1500 / Tape & Reel
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
0.05
E2
G
0.10 C
0.10 C
8X
C
A0.10 B
C
4X
E3
1234
TOP VIEW
SIDE VIEW
b
L
14
8
BOTTOM VIEW
D1
78
D2
2X
C
0.20
D
A
B
2X
56
E
E1
0.20 C
c
A
DETAIL A
e/2
K
M
5
L1
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
4X
q
A1
6X
e
DETAIL A
C
SEATING
PLANE
0.75
DATE 23 APR 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
DIM MIN NOM
MILLIMETERS
A 0.70 0.75
A1 0.00 −−−
b 0.23 0.30
c 0.15 0.20
D
D1 2.95 3.05
D2 1.98 2.11
E
E1 2.95 3.05
E2 1.47 1.60
E3 0.23 0.30 0.40
e 0.65 BSC
G 0.30 0.41
K 0.65 0.80
L 0.30 0.43
L1 0.06 0.13
M 1.40 1.50
q 0 −−−
3.30 BSC
3.30 BSC
_
MAX
0.80
0.05
0.40
0.25
3.15
2.24
3.15
1.73
0.51
0.95
0.56
0.20
1.60
12
_
INCHES
MIN NOM
0.028 0.030
0.000 −−−
0.009 0.012
0.006 0.008
0.130 BSC
0.116 0.120
0.078 0.083
0.130 BSC
0.116 0.120
0.058 0.063
0.009 0.012 0.016
0.026 BSC
0.012 0.016
0.026 0.032
0.012 0.017
0.002 0.005
0.055 0.059
0 −−−
_
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.020
0.037
0.022
0.008
0.063
12
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
0.57
8X
0.650.42
PITCH
2.30
4X
0.66
3.60
_
GENERIC
MARKING DIAGRAM*
1
XXXXX
AYWWG
G
XXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON30561E
WDFN8 3.3X3.3, 0.65P
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
0.47
2.37
3.46
DIMENSION: MILLIMETERS
PAGE 1 OF 1
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
CASE 515AN
ISSUE O
DATE 25 AUG 2020
GENERIC
MARKING DIAGRAM*
XXXX
AYWWG
G
DOCUMENT NUMBER:
98AON24556H
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
XXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
PAGE 1 OF 1WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
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