Page 1
MOSFET – Power, Single,
P-Channel
-40 V, 13.8 mW, -49 A
NVTFS014P04M8L
Features
• Small Footprint (3.3 x 3.3 mm) for Compact Design
• Low R
• Low Capacitance to Minimize Driver Losses
• NVTFWS014P04M8L − Wettable Flanks Product
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR−Free and are RoHS
Compliant
to Minimize Conduction Losses
DS(on)
V
(BR)DSS
−40 V
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R
MAX ID MAX
DS(on)
13.8 mW @ −10 V
18.7 mW @ −4.5 V
−49 A
MAXIMUM RATINGS (T
Parameter
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain
Current R
(Notes 1, 2, 4)
Power Dissipation
R
q
JC
Continuous Drain
Current R
(Notes 1, 3, 4)
Power Dissipation
R
q
JA
Pulsed Drain Current
Operating Junction and Storage Temperature
Range
Source Current (Body Diode) I
Single Pulse Drain−to−Source Avalanche
Energy (I
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
q
JC
(Notes 1, 2)
q
JA
(Notes 1, 3)
= −6.1 A)
L(pk)
= 25°C unless otherwise noted)
J
Symbol Value Unit
TC = 25°C
Steady
State
Steady
State
TA = 25°C, t
TC = 100°C −35
TC = 25°C
TC = 100°C 30
TA = 25°C
TA = 100°C −8
TA = 25°C
TA = 100°C 1.6
= 10 ms
p
P
P
I
TJ, T
E
DSS
GS
I
D
D
I
D
D
DM
S
AS
T
L
stg
−40 V
±20 V
−49
61
−11.3
3.2
224 A
−55 to
+175
−50 A
143 mJ
260 °C
A
W
A
W
°C
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Junction−to−Case − Steady State (Drain)
(Notes 1, 2, 4)
Junction−to−Ambient − Steady State (Note 3)
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Assumes heat−sink sufficiently large to maintain constant case temperature
independent of device power.
3. Surface−mounted on FR4 board using a 650 mm
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
Symbol Value Unit
°C/W
R
q
JC
R
q
JA
2
, 2 oz. Cu pad.
2.5
47
P−Channel MOSFET
D (5−8)
G (4)
S (1,2,3)
MARKING DIAGRAM
1
WDFN8
(m8FL)
CASE 511AB
XXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
1
S
XXXX
S
AYWWG
S
G
G
D
D
D
D
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
May, 2020 − Rev. 4
1 Publication Order Number:
NVTFS014P04M8L/D
Page 2
NVTFS014P04M8L
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise noted)
J
Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
V
(BR)DSS/TJ
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
(BR)DSS
DSS
GSS
VGS = 0 V, ID = −250 mA
VGS = 0 V,
V
= −40 V
DS
TJ = 25°C −1.0 mA
TJ = 125°C −1000
VDS = 0 V, VGS = "20 V "100 nA
−40 V
21 mV/°C
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature
V
Coefficient
Drain−to−Source On Resistance R
V
GS(TH)
GS(TH)/TJ
DS(on)
VGS = VDS, ID = −420 mA
VGS = −10 V, ID = −15 A 10 13.8 mW
−1.0 −2.4 V
5.1 mV/°C
VGS = −4.5 V, ID = −7.5 A 14.6 18.7
Forward Transconductance g
FS
VDS = −1.5 V, ID = −15 A 42 S
CHARGES AND CAPACITANCES
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
Plateau Voltage V
iss
oss
rss
G(TOT)
G(TH)
GS
GD
GP
VGS = 0 V, f = 1.0 MHz,
V
= −20 V
DS
VDS = −20 V,
I
= −20 A
D
VGS = −4.5V 12.5
VGS = −10V 26.5
VGS = −10 V, VDS = −20 V,
I
= −30 A
D
1734
682
32
2.6
5.6
3.8
3.2 V
pF
nC
nC
SWITCHING CHARACTERISTICS, VGS = −4.5 V (Note 6)
Turn−On Delay Time t
Rise Time t
Turn−Off Delay Time t
Fall Time t
d(on)
r
d(off)
f
VGS = −4.5 V, VDS = −20 V,
= −30 A, RG = 2.5 W
I
D
11.5
97.4
44.5
38.2
ns
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
RR
a
b
RR
VGS = 0 V,
I
= −15 A
S
TJ = 25°C −0.86 −1.25
TJ = 125°C −0.74
VGS = 0 V, dIS/dt = 100 A/ms,
I
= −10 A
S
V
34.9
ns
15.8
19.1
16.3 52 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
Page 3
NVTFS014P04M8L
TYPICAL CHARACTERISTICS
120
VGS = 5.5 V to 10 V
100
80
60
40
, DRAIN CURRENT (A)
D
−I
20
..
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
32
28
24
20
(mW)
16
VGS = 4.8 V
VGS = 4.5 V
VGS = 4.0 V
VGS = 3.6 V
VGS = 3.2 V
VGS = 2.8 V
VGS = 2.6 V
VGS = 2.4 V
TJ = 25°C
ID = −15 A
120
VDS = −3 V
100
80
60
40
, DRAIN CURRENT (A)
D
−I
20
TJ = −55°C
= 25°C
T
J
T
= 125°C
J
0
0123456
−VGS, GATE−TO−SOURCE VOLTAGE (V)
40
30
20
(mW)
V
GS
= −4.5 V
12
, DRAIN−TO−SOURCE RESISTANCE
8
4
DS(ON)
R
2345678910
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2.5
VGS = −10 V
I
= −15 A
D
2
1.5
1
RESISTANCE
0.5
, NORMALIZED DRAIN−TO−SOURCE
DS(ON)
0
R
−50 −25 0 25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (°C)
, DRAIN−TO−SOURCE RESISTANCE
DS(ON)
R
10
0
1 1121314151617181
V
GS
= −10 V
−ID, DRAIN CURRENT (A)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1,E−04
1,E−05
1,E−06
1,E−07
, LEAKAGE (A)
1,E−08
DSS
−I
1,E−09
1,E−10
0 5 10 15 20 25 30 35 40
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ = 25°C
T
= 85°C
J
T
= 125°C
J
T
= 150°C
J
T
= 175°C
J
Figure 5. On−Resistance Variation with
Temperature
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Figure 6. Drain−to−Source Leakage Current
vs. Voltage
3
Page 4
NVTFS014P04M8L
TYPICAL CHARACTERISTICS (continued)
1,E+04
C
ISS
1,E+03
1,E+02
C, CAPACITANCE (pF)
C
ISS
C
OSS
C
RSS
C
OSS
C
RSS
1,E+01
0,1 1 10 100
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge
1000
VGS = −4.5 V
V
= −20 V
DS
= −30 A
I
D
100
VGS = −0 V
T
= 25°C
J
f = 1 MHz
10
VDS = −20 V
9
= −30 A
I
D
8
= 25°C
T
J
7
6
5
4
Q
Q
GS
GD
3
2
, GATE−TO−SOURCE VOLTAGE (V)
1
GS
0
−V
0 5 10 15 20 25 30
QG, TOTAL GATE CHARGE (nC)
50
VGS = 0 V
TJ = −55°C
T
40
= 25°C
J
T
= 125°C
J
30
t, TIME (ns)
10
1
1 10 100
Figure 9. Resistive Switching Time Variation
1000
V
≤ 10 V
GS
SINGLE PULSE
100
, DRAIN CURRENT (A)
D
I
TC = 25°C
10
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1 1 10 100 1000
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
, GATE RESISTANCE (W)
R
G
vs. Gate Resistance
10 ms
0.5 ms
1 ms
10 ms
td(on)
tr
td(off)
tf
20
, SOURCE CURRENT (A)
10
S
I
0
0 0.2 0.4 0.6 0.8 1 1.2
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
Figure 10. Diode Forward Voltage vs. Current
100
T
(initial) = 25°C
(A)
10
PEAK
I
TJ (initial) = 100°C
1
0.0001 0.001 0.01
J
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Dafe operating Area
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Figure 12. Maximum Drain Current vs. Time in
Avalanche
4
Page 5
100
†
10
NVTFS014P04M8L
TYPICAL CHARACTERISTICS (continued)
1
R(t) (°C/W)
Single Pulse
Duty Cycle 1%
2%
5%
10%
0.1
0.01
0.000001 0.00001 0.0001 0.001
0.01 0.1 1 10 100 1000
20%
50%
Time (s)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device Marking Package Shipping
NVTFS014P04M8LTAG 014M WDFN8
(Pb−Free)
NVTFWS014P04M8LTAG 014W WDFN8
(Pb−Free, Wettable Flank)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1500 / Tape & Reel
1500 / Tape & Reel
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5
Page 6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
0.05
E2
G
0.10 C
0.10 C
8X
C
A0.10 B
C
4X
E3
1234
TOP VIEW
SIDE VIEW
b
L
14
8
BOTTOM VIEW
D1
78
D2
2X
C
0.20
D
A
B
2X
56
E
E1
0.20 C
c
A
DETAIL A
e/2
K
M
5
L1
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
4X
q
A1
6X
e
DETAIL A
C
SEATING
PLANE
0.75
DATE 23 APR 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
DIM MIN NOM
A1 0.00 −−−
D1 2.95 3.05
D2 1.98 2.11
E1 2.95 3.05
E2 1.47 1.60
E3 0.23 0.30 0.40
L1 0.06 0.13
MILLIMETERS
A 0.70 0.75
b 0.23 0.30
c 0.15 0.20
D
E
e 0.65 BSC
G 0.30 0.41
K 0.65 0.80
L 0.30 0.43
M 1.40 1.50
q 0 −−−
3.30 BSC
3.30 BSC
_
MAX
0.80
0.05
0.40
0.25
3.15
2.24
3.15
1.73
0.51
0.95
0.56
0.20
1.60
12
_
INCHES
MIN NOM
0.028 0.030
0.000 −−−
0.009 0.012
0.006 0.008
0.130 BSC
0.116 0.120
0.078 0.083
0.130 BSC
0.116 0.120
0.058 0.063
0.009 0.012 0.016
0.026 BSC
0.012 0.016
0.026 0.032
0.012 0.017
0.002 0.005
0.055 0.059
0 −−−
_
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.020
0.037
0.022
0.008
0.063
12
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
0.57
8X
0.650.42
PITCH
2.30
4X
0.66
3.60
_
GENERIC
MARKING DIAGRAM*
1
XXXXX
AYWWG
G
XXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON30561E
WDFN8 3.3X3.3, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.47
2.37
3.46
DIMENSION: MILLIMETERS
PAGE 1 OF 1
© Semiconductor Components Industries, LLC, 2019
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