NVMFS5C450N
MOSFET – Power, Single
N-Channel
40 V, 3.3 mW, 102 A
Features
• Small Footprint (5x6 mm) for Compact Design
• Low R
• Low Q
to Minimize Conduction Losses
DS(on)
and Capacitance to Minimize Driver Losses
G
• NVMFS5C450NWF − Wettable Flank Option for Enhanced Optical
Inspection
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T
Parameter
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain
Current R
(Notes 1, 3)
Power Dissipation
R
q
JC
Continuous Drain
Current R
(Notes 1, 2, 3)
Power Dissipation
R
q
JA
Pulsed Drain Current
Operating Junction and Storage Temperature TJ, T
Source Current (Body Diode) I
Single Pulse Drain−to−Source Avalanche
Energy (I
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
q
JC
(Note 1)
q
JA
(Notes 1 & 2)
= 7.0 A)
L(pk)
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
= 25°C unless otherwise noted)
J
Symbol Value Unit
TC = 25°C
Steady
State
Steady
State
TA = 25°C, t
TC = 100°C 72
TC = 25°C
TC = 100°C 34
TA = 25°C
TA = 100°C 17
TA = 25°C
TA = 100°C 1.8
= 10 ms
p
P
P
I
E
R
q
R
q
2
, 2 oz. Cu pad.
DSS
GS
I
D
D
I
D
D
DM
S
AS
T
L
JC
JA
stg
40 V
±20 V
102
68
24
3.6
554 A
−55 to
+ 175
65 A
215 mJ
260 °C
2.2
41
A
W
A
W
°C
°C/W
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V
(BR)DSS
40 V
G (4)
R
MAX ID MAX
DS(ON)
3.3 mW @ 10 V
D (5,6)
S (1,2,3)
N−CHANNEL MOSFET
102 A
MARKING
DIAGRAM
1
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
XXXXXX = 5C450N
XXXXXX = (NVMFS5C450N) or
XXXXXX = 450NWF
XXXXXX = (NVMFS5C450NWF)
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
S
S
S
G
D
D
XXXXXX
AYWZZ
D
D
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
July, 2019 − Rev. 2
1 Publication Order Number:
NVMFS5C450N/D
NVMFS5C450N
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
Symbol Test Condition Min Ty p Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
V
V
Temperature Coefficient
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
(BR)DSS
(BR)DSS
T
J
DSS
GSS
VGS = 0 V, ID = 250 mA
/
VGS = 0 V,
V
= 40 V
DS
TJ = 25°C 10
TJ = 125°C 100
VDS = 0 V, VGS = 20 V 100 nA
40 V
20
mV/°C
mA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient V
V
GS(TH)/TJ
Drain−to−Source On Resistance R
Forward Transconductance g
GS(TH)
DS(on)
FS
VGS = VDS, ID = 65 mA
VGS = 10 V ID = 50 A 2.7 3.3
VDS =15 V, ID = 50 A 93 S
2.5 3.5 V
−9.1 mV/°C
mW
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
Plateau Voltage V
C
ISS
OSS
RSS
G(TOT)
G(TH)
GS
GD
GP
VGS = 0 V, f = 1 MHz, VDS = 25 V
VGS = 10 V, VDS = 20 V; ID = 50 A 23
VGS = 10 V, VDS = 20 V; ID = 50 A
1600
830
28
5.1
9.0
3.5
5.3 V
pF
nC
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
d(ON)
Rise Time t
Turn−Off Delay Time t
d(OFF)
Fall Time t
r
f
VGS = 10 V, VDS = 20 V,
= 50 A, RG = 2.5 W
I
D
10
47
19
3.0
ns
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
RR
a
b
RR
VGS = 0 V,
I
= 50 A
S
VGS = 0 V, dIS/dt = 100 A/ms,
I
= 50 A
S
TJ = 25°C 0.9 1.2
TJ = 125°C 0.78
37
18
19
23 nC
V
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS5C450N
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
30
, DRAIN CURRENT (A)
D
20
I
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
10 V to
6.0 V
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
, DRAIN−TO−SOURCE RESISTANCE (mW)
0
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
DS(on)
R
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
TJ = 25°C
= 50 A
I
D
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2.0
VGS = 10 V
= 50 A
I
1.8
D
1.6
5.2 V
4.8 V
4.4 V
4.0 V
100
VDS = 10 V
90
80
70
60
50
40
30
, DRAIN CURRENT (A)
D
20
I
10
0
012345
4.0
TJ = 25°C
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
, DRAIN−TO−SOURCE RESISTANCE (mW)
2.0
0 10 20 40 50 100
DS(on)
R
TJ = 25°C
TJ = 125°C
VGS = 10 V
30
TJ = −55°C
60 80 9070
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.E−04
1.E−05
TJ = 150°C
67
1.4
1.2
1.0
, NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
0.8
DS(on)
R
0.6
−50 −25 0 25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
1.E−06
, LEAKAGE (A)
DSS
I
1.E−07
1.E−08
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3
TJ = 125°C
TJ = 85°C
5152535
10 20 30 40
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
NVMFS5C450N
TYPICAL CHARACTERISTICS
10000
C
ISS
1000
100
C, CAPACITANCE (pF)
VGS = 0 V
= 25°C
T
J
f = 1 MHz
10
0 10203040
5152535
C
C
OSS
RSS
VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
100
10
t
d(off)
t
r
t
f
t
d(on)
10
9
Q
T
8
7
Q
6
GS
Q
GD
5
4
3
2
1
, GATE−TO−SOURCE VOLTAGE (V)
GS
0
V
0102025
515
VDS = 20 V
= 50 A
I
D
T
= 25°C
J
Drain−to−Source Voltage vs. Total Charge
100
VGS = 0 V
10
t, TIME (ns)
VGS = 10 V
V
DD
I
1.0
1 10 100
D
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
1000
100
10
TC = 25°C
≤ 10 V
V
GS
D
Single Pulse
1
R
DS(on)
Limit
, DRAIN CURRENT (A)
I
Thermal Limit
0.1
Package Limit
1 10 1000.1
VDS (V) TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area Figure 12. I
= 20 V
= 50 A
0.5 ms
1 ms
10 ms
, SOURCE CURRENT (A)
S
I
1.0
TJ = 150°C
0.3
0.4 0.5 0.6 0.7 0.8 0.9 1.0
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
TJ = 125°C
TJ = 25°C
TJ = −55°C
Figure 10. Diode Forward Voltage vs. Current
100
, (A)
10
PEAK
I
TJ = 100°C
1
1E−41E−3 10E−2
TJ = 25°C
vs. Time in Avalanche
PEAK
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4
NVMFS5C450N
TYPICAL CHARACTERISTICS
100
50% Duty Cycle
10
20%
10%
5%
1
(°C/W)
JA
q
R
0.01
DEVICE ORDERING INFORMATION
NVMFS5C450NT1G 5C450N DFN5
NVMFS5C450NWFT1G 450NWF DFN5
NVMFS5C450NT3G 5C450N DFN5
NVMFS5C450NWFT3G 450NWF DFN5
NVMFS5C450NAFT1G 5C450N DFN5
NVMFS5C450NWFAFT1G 450NWF DFN5
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
2%
1%
0.1
Single Pulse
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
Device Marking Package Shipping
1500 / Tape & Reel
(Pb−Free)
1500 / Tape & Reel
(Pb−Free, Wettable Flanks)
5000 / Tape & Reel
(Pb−Free)
5000 / Tape & Reel
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
(Pb−Free)
1500 / Tape & Reel
(Pb−Free, Wettable Flanks)
†
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5
DFN5 5x6, 1.27P
8
s
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
2 X
0.20 C
0.10 C
0.10 C
C
0.05
c
PIN 5
(EXPOSED PAD)
D
2
D1
1234
TOP VIEW
SIDE VIEW
8X
b
A0.10 B
L
14
E2
G
D2
BOTTOM VIEW
A
B
E1
E
2
A
DETAIL A
e/2
e
K
M
L1
0.475
2 X
SOLDERING FOOTPRINT*
2X
2X
(SO−8FL)
CASE 488AA
ISSUE N
0.20 C
c
DETAIL A
RECOMMENDED
4.5600.495
2X
1.530
4 X
q
A1
SEATING
3.200
C
PLANE
DATE 25 JUN 201
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
DIM MIN NOM
MILLIMETERS
A 0.90 1.00
A1 0.00 −−−
b 0.33 0.41
c 0.23 0.28
D 5.15
5.00 5.30
D1 4.70 4.90
D2 3.80 4.00
E 6.15
6.00 6.30
E1 5.70 5.90
E2 3.45 3.65
e 1.27 BSC
G 0.51 0.575
K 1.20 1.35
L 0.51 0.575
L1 0.125 REF
M 3.00 3.40
q 0 −−−
_
MAX
1.10
0.05
0.51
0.33
5.10
4.20
6.10
3.85
0.71
1.50
0.71
3.80
12
_
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some product
may not follow the Generic Marking.
4.530
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
STYLE 2:
PIN 1. ANODE
2. ANODE
3. ANODE
4. NO CONNECT
5. CATHODE
2X
0.905
0.965
1.000
4X
4X
0.750
1
DIMENSIONS: MILLIMETERS
1.330
1.270
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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