ON Semiconductor NTMFS5844NL, NVMFS5844NL User Manual

Page 1
NTMFS5844NL, NVMFS5844NL
MOSFET – Power, Single,
N-Channel
Features
Small Footprint (5x6 mm) for Compact Design
Low R
Low Q
to Minimize Conduction Losses
DS(on)
and Capacitance to Minimize Driver Losses
G
NVMFS5844NLWF Wettable Flanks Product
NVMFS Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ101 Qualified and PPAP Capable
These Devices are PbFree and are RoHS Compliant
MAXIMUM RATINGS (T
Parameter
DraintoSource Voltage V
Gateto−Source Voltage V
Continuous Drain Cur­rent R 2, 3, 4)
Power Dissipation R
Y
Jmb
Continuous Drain Cur­rent R
4)
Power Dissipation R
q
JA
Pulsed Drain Current
Current Limited by Package (Note 4)
Operating Junction and Storage Temperature TJ, T
Source Current (Body Diode) I
Single Pulse DraintoSource Avalanche Energy (T I
L(pk)
Lead Temperature for Soldering Purposes (1/8 from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
(Notes 1,
Y
Jmb
(Notes 1, 2, 3)
(Notes 1, 3,
q
JA
(Notes 1 & 3)
= 25°C, VDD = 50 V, VGS = 10 V,
J
= 31 A, L = 0.1 mH, RG = 25 W)
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
JunctiontoMounting Board (top) Steady
State (Notes 2, 3)
JunctiontoAmbient Steady State (Note 3)
1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD5112 for packages in which substantially less than 100% of the heat flows to single case surface.
= 25°C unless otherwise noted)
J
Symbol Value Unit
Tmb = 25°C
Steady
State
Steady
State
TA = 25°C, t
Tmb = 100°C 43
Tmb = 25°C
Tmb = 100°C 54
TA = 25°C
TA = 100°C 8.0
TA = 25°C
TA = 100°C 1.8
= 10 ms
p
TA = 25°C I
P
P
I
DmaxPkg
E
R
Y
R
q
DSS
GS
I
D
D
I
D
D
DM
S
AS
T
L
Jmb
JA
stg
60 V
"20 V
61
107
11.2
3.7
247 A
80 A
55 to 175
60 A
48 mJ
260 °C
1.4
41
A
W
A
W
°C
°C/W
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V
(BR)DSS
60 V
G (4)
R
MAX ID MAX
DS(ON)
12 mW @ 10 V
16 mW @ 4.5 V
D (5)
S (1,2,3)
NCHANNEL MOSFET
61 A
MARKING DIAGRAM
D
1
DFN5
(SO8FL)
CASE 488AA
STYLE 1
A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability
S S S G
D
XXXXXX
AYWZZ
D
D
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
May, 2019 − Rev. 5
1 Publication Order Number:
NTMFS5844NL/D
Page 2
NTMFS5844NL, NVMFS5844NL
3. Surfacemounted on FR4 board using a 650 mm
2
, 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle.
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
DraintoSource Breakdown Voltage Temperature Coefficient
Zero Gate Voltage Drain Current I
GatetoSource Leakage Current I
V
(BR)DSS
V
(BR)DSS
T
DSS
GSS
VGS = 0 V, ID = 250 mA
/
J
VGS = 0 V,
V
= 60 V
DS
VDS = 0 V, VGS = ±20 V ±100 nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient V
DraintoSource On Resistance R
V
GS(TH)
GS(TH)/TJ
DS(on)
VGS = VDS, ID = 250 mA
VGS = 10 V ID = 10 A 10.2 12
VGS = 4.5 V ID = 10 A 13 16
Forward Transconductance g
FS
VDS = 5 V, ID = 10 A 27 S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Total Gate Charge Q
Threshold Gate Charge Q
GatetoSource Charge Q
GatetoDrain Charge Q
Plateau Voltage V
Gate Resistance R
C
ISS
OSS
RSS
G(TOT)
G(TOT)
G(TH)
GS
GD
GP
G
VGS = 0 V, f = 1 MHz, VDS = 25 V
VGS = 10 V, VDS = 48 V; ID = 10 A 30
VGS = 4.5 V, VDS = 48 V; ID = 10 A
SWITCHING CHARACTERISTICS (Note 6)
TurnOn Delay Time
Rise Time t
TurnOff Delay Time t
Fall Time t
t
d(ON)
r
d(OFF)
f
VGS = 4.5 V, VDS = 48 V,
= 10 A, RG = 2.5 W
I
D
DRAINSOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
RR
a
b
RR
VGS = 0 V,
I
= 10 A
S
VGS = 0 V, dIS/dt = 100 A/ms,
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
I
= 10 A
S
60 V
57
TJ = 25 °C 1
TJ = 125°C 100
1.5 2.3 V
6.2 mV/°C
1460
150
96
15
1.0
4.0
8.0
3.0 V
0.62
12
25
20
10
TJ = 25°C 0.79 1.2
TJ = 125°C 0.65
19
13
6.0
15 nC
mV/°C
mA
mW
pF
nC
W
ns
V
ns
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2
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NTMFS5844NL, NVMFS5844NL
0
TYPICAL CHARACTERISTICS
80
10 V
70
60
50
40
30
20
, DRAIN CURRENT (A)
D
I
10
0
012345
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS = 5 V
4.0 V
3.8 V
3.6 V
3.4 V
3.2 V
3.0 V
2.8 V
TJ = 25°C
Figure 1. On−Region Characteristics
0.030
ID = 10 A
= 25°C
T
0.025
0.020
0.015
0.010
J
80
VDS 10 V
70
60
50
40
30
20
, DRAIN CURRENT (A)
D
I
10
0
12345
TJ = 25°C
TJ = 125°C
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ = 55°C
Figure 2. Transfer Characteristics
0.016
TJ = 25°C
0.014
0.012
0.010
VGS = 4.5 V
VGS = 10 V
, DRAINTOSOURCE RESISTANCE (W)
0.005 24681012
DS(on)
R
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2.5
VGS = 10 V
ID = 10 A
2
1.5
1
0.5
50 25 0 25 50 75 100 125 150
, DRAINTOSOURCE RESISTANCE (NORMALIZED)
DS(on)
R
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. OnResistance Variation with
Temperature
, DRAINTOSOURCE RESISTANCE (W)
0.008
DS(on)
R
100,000
10,000
, LEAKAGE (nA)
1,000
DSS
I
175
100
5 10152025303540
ID, DRAIN CURRENT (A)
Figure 4. OnResistance vs. Drain Current and
Gate Voltage
VGS = 0 V
TJ = 150°C
TJ = 125°C
10 20 30 40 50 6
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
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NTMFS5844NL, NVMFS5844NL
0
TYPICAL CHARACTERISTICS
1800
1600
1400
C
iss
VGS = 0 V TJ = 25°C
1200
1000
800
600
C, CAPACITANCE (pF)
400
C
oss
200
C
rss
0
0 102030405060
DRAINTOSOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
1000
VDD = 48 V
= 10 A
I
D
V
= 4.5 V
GS
100
t
d(off)
d(on)
t, TIME (ns)
10
t
f
t
r
t
10
Q
T
8
6
4
Q
Q
gs
2
, GATE−TO−SOURCE VOLTAGE (V)
GS
0
V
0 5 10 15 20 25 3
gd
VDS = 48 V
I
D
T
J
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source Voltage vs. Total
Charge
40
VGS = 0 V
TJ = 25°C
30
20
10
, SOURCE CURRENT (A)
S
I
= 10 A = 25°C
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
1000
VGS = 10 V Single Pulse TC = 25°C
100
100 ms
10
1
, DRAIN CURRENT (A)
D
I
R
Limit
DS(on)
Thermal Limit
1 ms
Package Limit
0.1
0.1 1 10 100 VDS, DRAISN VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10 ms
10 ms
dc
0
0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
50
40
30
20
10
, SINGLE PULSE DRAINTO
AS
E
SOURCE AVALANCHE ENERGY (mJ)
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
175
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4
Page 5
NTMFS5844NL, NVMFS5844NL
0
TYPICAL CHARACTERISTICS
100
Duty Cycle = 0.5
0.2
10
0.1
0.05
1
0.02
0.01
0.1
THERMAL RESISTANCE
(°C/W) EFFECTIVE TRANSIENT
JA(t)
q
R
0.01
Single Pulse
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device Marking Package Shipping
NTMFS5844NLT1G 5844NL DFN5
(PbFree)
NVMFS5844NLT1G V5844L DFN5
(PbFree)
NVMFS5844NLWFT1G 5844LW DFN5
(PbFree)
NVMFS5844NLT3G V5844L DFN5
(PbFree)
NVMFS5844NLWFT3G 5844LW DFN5
(PbFree)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1500 / Tape & Reel
1500 / Tape & Reel
1500 / Tape & Reel
5000 / Tape & Reel
5000 / Tape & Reel
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5
Page 6
DFN5 5x6, 1.27P
8
s
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
2 X
0.20 C
0.10 C
0.10 C
C
0.05
c
PIN 5
(EXPOSED PAD)
D
2
D1
1234
TOP VIEW
SIDE VIEW
8X
b
A0.10 B
L
14
E2
G
D2
BOTTOM VIEW
A
B
E1
E
2
A
DETAIL A
e/2 e
K
M
L1
0.475
2 X
2X
2X
(SO−8FL)
CASE 488AA
ISSUE N
0.20 C
4 X
q
c
DETAIL A
RECOMMENDED
SOLDERING FOOTPRINT*
4.5600.495
2X
1.530
A1
C
SEATING
PLANE
3.200
DATE 25 JUN 201
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS.
DIM MIN NOM
MILLIMETERS
A 0.90 1.00
A1 0.00 −−−
b 0.33 0.41 c 0.23 0.28 D 5.15
5.00 5.30
D1 4.70 4.90 D2 3.80 4.00
E 6.15
6.00 6.30
E1 5.70 5.90 E2 3.45 3.65
e 1.27 BSC G 0.51 0.575 K 1.20 1.35 L 0.51 0.575
L1 0.125 REF
M 3.00 3.40
q 0 −−−
_
MAX
1.10
0.05
0.51
0.33
5.10
4.20
6.10
3.85
0.71
1.50
0.71
3.80 12
_
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability
*This information is generic. Please refer to
device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some product may not follow the Generic Marking.
4.530
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
STYLE 2:
PIN 1. ANODE
2. ANODE
3. ANODE
4. NO CONNECT
5. CATHODE
2X
0.905
0.965
1.000
4X
4X
0.750
1
DIMENSIONS: MILLIMETERS
1.330
1.270 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
98AON14036D DFN5 5x6, 1.27P (SO−8FL)
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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