Page 1
NVMFD5C466N
MOSFET – Power, Dual
N-Channel
40 V, 8.1 mW, 49 A
Features
• Small Footprint (5x6 mm) for Compact Design
• Low R
• Low Q
• NVMFD5C466NWF − Wettable Flank Option for Enhanced Optical
Inspection
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
to Minimize Conduction Losses
DS(on)
and Capacitance to Minimize Driver Losses
G
V
(BR)DSS
40 V
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R
MAX ID MAX
DS(ON)
8.1 m @ 10 V
49 A
MAXIMUM RATINGS (T
Parameter
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain
Current R
(Notes 1, 2, 3)
Power Dissipation
R
Continuous Drain
Current R
(Notes 1, 2, 3)
Power Dissipation
R
Pulsed Drain Current
Operating Junction and Storage Temperature TJ, T
Source Current (Body Diode) I
Single Pulse Drain−to−Source Avalanche
Energy (T
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
(Notes 1, 2)
JC
(Notes 1 & 2)
JA
J
JC
JA
= 25°C, I
= 25°C unless otherwise noted)
J
TC = 25°C
TC = 100°C 35
TC = 25°C
TC = 100°C 19
TA = 25°C
TA = 100°C 10
TA = 25°C
TA = 100°C 1.5
= 10 s
p
L(pk)
Steady
State
Steady
State
TA = 25°C, t
= 3 A)
Symbol Value Unit
stg
40 V
±20 V
49
38
14
3.0
169 A
−55 to
+ 175
31 A
72 mJ
260 °C
A
W
A
W
°C
P
P
I
E
DSS
GS
I
D
D
I
D
D
DM
S
AS
T
L
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
49
°C/W
4
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
R
JC
R
JA
2
, 2 oz. Cu pad.
Dual N−Channel
D2
S2
G1
D1
G2
S1
MARKING
DIAGRAM
D1
D1
1
DFN8 5x6
(SO8FL)
CASE 506BT
XXXXXX = 5C466N (NVMFD5C466N)
= or 466NWF (NVMFD5C466NWF)
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
S1
G1
S2
G2
XXXXXX
AYWZZ
D2
D1
D1
D2
D2
D2
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
July, 2019 − Rev. 1
1 Publication Order Number:
NVMFD5C466N/D
Page 2
NVMFD5C466N
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
V
V
Temperature Coefficient
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
(BR)DSS
(BR)DSS
T
J
DSS
GSS
VGS = 0 V, ID = 250 A
/
VGS = 0 V,
V
= 40 V
DS
TJ = 25 °C 10
TJ = 125°C 100
VDS = 0 V, VGS = 20 V 100 nA
40 V
23
mV/°C
A
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient V
Drain−to−Source On Resistance R
V
GS(TH)
GS(TH)/TJ
DS(on)
VGS = VDS, ID = 250 A
VGS = 10 V ID = 15 A 6.75 8.1
2.5 3.5 V
−6.4 mV/°C
m
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
Plateau Voltage V
C
ISS
OSS
RSS
G(TOT)
G(TH)
GS
GD
GP
VGS = 0 V, f = 1 MHz, VDS = 25 V
VGS = 10 V, VDS = 32 V; ID = 15 A
650
320
14
11
2.3
3.6
1.8
4.8 V
pF
nC
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time t
d(ON)
Rise Time t
Turn−Off Delay Time t
d(OFF)
Fall Time t
r
f
VGS = 10 V, VDS = 32 V,
= 15 A, RG = 1.0
I
D
9.0
22
19
6.0
ns
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
RR
a
b
RR
VGS = 0 V,
I
= 15 A
S
VGS = 0 V, dIS/dt = 100 A/s,
I
= 15 A
S
TJ = 25°C 0.9 1.2
TJ = 125°C 0.7
24
11
13
10 nC
V
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
Page 3
NVMFD5C466N
TYPICAL CHARACTERISTICS
200
180
160
140
120
100
80
60
, DRAIN CURRENT (A)
D
I
40
20
0
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
40
35
30
25
20
15
10
5
, DRAIN−TO−SOURCE RESISTANCE (m)
0
DS(on)
4
R
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
10 V
1.51.00.50
Voltage
9 V
ID = 15 A
= 25°C
T
J
60
8 V
7 V
6 V
5 V
4 V
3.02.52.0 51
1098765
50
40
30
20
, DRAIN CURRENT (A)
D
I
10
10
, DRAIN−TO−SOURCE RESISTANCE (m)
DS(on)
R
VDS = 3 V
TJ = 25°C
TJ = 125°C
0
9
8
7
6
5
4
3
10
504020 30 1000
TJ = −55°C
70
VGS = 10 V
80
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
64320
9060
1.9
ID = 15 A
= 10 V
V
1.7
1.5
1.3
1.1
0.9
0.7
, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
DS(on)
R
GS
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
150
1251007550250−25−50
175
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1K
100
, LEAKAGE (nA)
10
DSS
I
1
3
TJ = 150°C
TJ = 125°C
TJ = 85°C
15 35
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
40302520105
Page 4
NVMFD5C466N
TYPICAL CHARACTERISTICS
10K
1K
100
10
C, CAPACITANCE (pF)
TJ = 25°C
V
f = 1 MHz
1
100
t
r
t
d(off)
t
d(on)
10
t, TIME (ns)
t
f
10
9
C
iss
C
oss
8
7
6
Q
gs
Q
gd
5
4
3
2
1
, GATE−TO−SOURCE VOLTAGE (V)
GS
0
V
420
8
GS
= 0 V
15 35
3025520 40100
C
rss
VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge
VGS = 0 V
10
TJ = 125°C
1
VDS = 32 V
= 25 A
I
D
T
= 25°C
J
10
126
1
RG, GATE RESISTANCE ()
Figure 9. Resistive Switching Time Variation
1000
, DRAIN CURRENT (A)
D
I
100
10
1
0.1
TC = 25°C
≤ 10 V
V
GS
Single Pulse
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
101
vs. Gate Resistance
10 s
0.5 ms
R
Limit
DS(on)
Thermal Limit
Package Limit
1 ms
10 ms
Safe Operating Area
VGS = 10 V
= 32 V
V
DS
100
, SOURCE CURRENT (A)
S
I
0.1
100
10
(A)
PEAK
I
1
0.1
10001010.1
1.0E−05
TJ = 25°C
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
TJ = −55°C
0.8 1.0
0.90.70.60.50.4
Figure 10. Diode Forward Voltage vs. Current
T
= 25°C
J(initial)
T
= 100°C
J(initial)
1.0E−04 1.0E−03 1.0E−02
TIME IN AVALANCHE (s)
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
Page 5
100
10
1
R(t) (°C/W)
0.1
NVMFD5C466N
TYPICAL CHARACTERISTICS
50% Duty Cycle
20%
10%
5%
2%
1%
Single Pulse
0.01
0.010.001 100.0001 0.10.00001 10.000001
PULSE TIME (sec)
100 1000
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device Marking Package Shipping
NVMFD5C466NT1G 5C466N DFN8
(Pb−Free)
NVMFD5C466NWFT1G 466NWF DFN8
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1500 / Tape & Reel
1500 / Tape & Reel
†
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5
Page 6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
1
SCALE 2:1
PIN ONE
IDENTIFIER
NOTE 7
0.10 C
0.10 C
NOTE 4
DETAIL B
M
1234
TOP VIEW
SIDE VIEW
D3
e
14
N
8
4X
G
K1
BOTTOM VIEW
D
D1
78
D2
5
56
2X
DETAIL A
4X
4X
b1
0.20 C
A
E1
A
L
8X
B
2X
0.20 C
E
c
SEATING
C
PLANE
NOTE 6
K
DETAIL B
ALTERNATE
CONSTRUCTION
E2
b
C
A0.10 B
0.05
C
NOTE 3
CASE 506BT
ISSUE E
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
4X
h
GENERIC
MARKING DIAGRAM*
A1
*This information is generic. Please refer
to device data sheet for actual part
marking.
1
XXXXXX
AYWZZ
XXXXXX= Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
SOLDERING FOOTPRINT*
4.56
8X
0.75
4.84
2.30
DATE 26 FEB 2013
MILLIMETERS
3.70
MAX
0.42
4.90
4.10
5.90
4.15
0.55
0.61
3.50
2X
0.56
6.59
DIM MIN
A 0.90
A1 −−−
b 0.33
b1 0.33 0.42
c 0.20
D 5.15 BSC
D1 4.70
D2 3.90
D3 1.50 1.70
E 6.15 BSC
E1 5.70
E2 3.90
e 1.27 BSC
G 0.45
h −−−
K 0.51
K1 0.56 −−−
L 0.48
M 3.25
N 1.80 2.00
2X
2.08
4X
1.40
−−−
−−−
−−−
−−−
−−−
MAX
1.10
0.05
0.51
0.51
0.33
5.10
4.30
1.90
6.10
4.40
0.65
12
−−−
−−−
0.71
3.75
2.20
_
0.70
4X
1.00
1.27
PITCH
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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