Page 1
NVMFD5C446NL
MOSFET – Power, Dual
N-Channel
40 V, 2.65 mW, 145 A
Features
• Small Footprint (5x6 mm) for Compact Design
• Low R
• Low Q
to Minimize Conduction Losses
DS(on)
and Capacitance to Minimize Driver Losses
G
• NVMFD5C446NLWF − Wettable Flank Option for Enhanced Optical
Inspection
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T
Parameter
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain
Current R
(Notes 1, 2, 3)
Power Dissipation
R
Continuous Drain
Current R
(Notes 1, 2, 3)
Power Dissipation
R
Pulsed Drain Current
Operating Junction and Storage Temperature TJ, T
Source Current (Body Diode) I
Single Pulse Drain−to−Source Avalanche
Energy (T
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
(Notes 1, 2)
JC
(Notes 1 & 2)
JA
J
JC
JA
= 25°C, I
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
= 25°C unless otherwise noted)
J
TC = 25°C
TC = 100°C 105
TC = 25°C
TC = 100°C 62
TA = 25°C
TA = 100°C 18
TA = 25°C
TA = 100°C 1.8
= 10 s
p
L(pk)
Steady
State
Steady
State
TA = 25°C, t
= 11 A)
Symbol Value Unit
stg
40 V
±20 V
145
125
25
3.5
644 A
−55 to
+ 175
91 A
171 mJ
260 °C
1.38
46.9
A
W
A
W
°C
°C/W
DSS
GS
I
D
P
D
I
D
P
D
I
DM
S
E
AS
T
L
R
JC
R
JA
2
, 2 oz. Cu pad.
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G1
V
(BR)DSS
40 V
R
DS(ON)
2.65 m @ 10 V
3.9 m @ 4.5 V
Dual N−Channel
D1
S1
MAX ID MAX
145 A
D2
G2
S2
MARKING
DIAGRAM
D1
D1
1
DFN8 5x6
(SO8FL)
CASE 506BT
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
S1
G1
S2
G2
XXXXXX
AYWZZ
D2
D1
D1
D2
D2
D2
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
July. 2019 − Rev. 0
1 Publication Order Number:
NVMFD5C446NL/D
Page 2
NVMFD5C446NL
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
Symbol Test Condition Min Ty p Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
V
V
Temperature Coefficient
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
(BR)DSS
(BR)DSS
T
J
DSS
GSS
VGS = 0 V, ID = 250 A
/
VGS = 0 V,
V
= 40 V
DS
TJ = 25 °C 10
TJ = 125°C 100
VDS = 0 V, VGS = 20 V 100 nA
40 V
23
mV/°C
A
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient V
V
GS(TH)/TJ
Drain−to−Source On Resistance R
Forward Transconductance g
GS(TH)
DS(on)
FS
VGS = VDS, ID = 90 A
VGS = 10 V ID = 20 A 2.2 2.65
VGS = 4.5 V ID = 20 A 3.0 3.9
VDS = 15 V, ID = 50 A 138 S
1.2 2.2 V
−5.2 mV/°C
m
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
Plateau Voltage V
C
ISS
OSS
RSS
G(TOT)
G(TOT)
G(TH)
GS
GD
GP
VGS = 0 V, f = 1 MHz, VDS = 25 V
VGS = 4.5 V, VDS = 32 V; ID = 50 A 25
VGS = 10 V, VDS = 32 V; ID = 50 A 54
VGS = 4.5 V, VDS = 32 V; ID = 50 A
3170
1270
48
5.7
10.7
7.0
5.7 V
pF
nC
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
d(ON)
Rise Time t
Turn−Off Delay Time t
d(OFF)
Fall Time t
r
f
VGS = 4.5 V, VDS = 32 V,
= 5 A, RG = 1.0
I
D
14.8
16.8
34.9
15.2
ns
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
RR
a
b
RR
VGS = 0 V,
I
= 20 A
S
VGS = 0 V, dIS/dt = 50 A/s,
I
= 5 A
S
TJ = 25°C 0.8 1.2
TJ = 125°C 0.7
54
24
30
55 nC
V
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
Page 3
NVMFD5C446NL
TYPICAL CHARACTERISTICS
220
200
180
160
140
120
100
80
60
, DRAIN CURRENT (A)
D
I
40
20
0
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
6
5
4
3
2
1
, DRAIN−TO−SOURCE RESISTANCE (m)
0
DS(on)
R
43
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
10 to 5 V
1.51.00.50
Voltage
4.5 V
3.8 V
3.6 V
3.4 V
VGS = 3.2 V
ID = 20 A
= 25°C
T
J
180
160
140
120
100
, DRAIN CURRENT (A)
D
I
3.02.52.0 3.00.5
, DRAIN−TO−SOURCE RESISTANCE (m)
1098765
DS(on)
R
VDS = 10 V
80
60
40
20
0
4.0
TJ = 25°C
3.5
3.0
2.5
2.0
1.5
Figure 4. On−Resistance vs. Drain Current and
TJ = 25°C
TJ = 125°C
1.5 3.5
5525 3515
45 65
TJ = −55°C
VGS = 4.5 V
VGS = 10 V
75
Gate Voltage
4.02.52.01.00
85
2.1
ID = 20 A
= 10 V
V
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
DS(on)
R
GS
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
1251007550250−25−50
150
175
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1M
100K
10K
1K
100
, LEAKAGE (nA)
10
DSS
I
1
0.1
3
TJ = 175°C
TJ = 150°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
15 35
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
40302520105
Page 4
NVMFD5C446NL
TYPICAL CHARACTERISTICS
10K
1K
100
C, CAPACITANCE (pF)t, TIME (ns)
TJ = 25°C
V
f = 1 MHz
10
1000
VGS = 4.5 V
V
I
100
10
VDS = 32 V
C
iss
C
oss
9
= 50 A
I
D
8
= 25°C
T
J
7
6
5
Q
4
GS
Q
GD
3
= 0 V
GS
15 35
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
C
rss
3025520 40100
2
, GATE−TO−SOURCE VOLTAGE (V)
1
GS
0
V
0
10 50
3020 40
QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge
VGS = 0 V
= 32 V
DS
= 5 A
D
t
d(off)
t
f
t
r
10
10
RG, GATE RESISTANCE ()
Figure 9. Resistive Switching Time Variation
1000
100
TC = 25°C
10
V
GS
≤ 10 V
Single Pulse
, DRAIN CURRENT (A)
1
D
I
0.1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
vs. Gate Resistance
R
Limit
DS(on)
Thermal Limit
Package Limit
Safe Operating Area
10 s
0.5 ms
1 ms
10 ms
100
t
d(on)
, SOURCE CURRENT (A)
S
I
1
100101
100
(A)
10
PEAK
I
10001010.1
1
0.00001
TJ = 25°CTJ = 125°C TJ = −55°C
0.8 1.0
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
0.90.70.60.50.4
Figure 10. Diode Forward Voltage vs. Current
T
= 25°C
J(initial)
T
= 100°C
J(initial)
0.0001 0.001 0.01
TIME IN AVALANCHE (s)
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
Page 5
100
10
1
R(t) (°C/W)
0.1
NVMFD5C446NL
TYPICAL CHARACTERISTICS
50% Duty Cycle
20%
10%
5%
2%
1%
0.01
Single Pulse
0.010.001 100.0001 0.10.00001 10.000001
PULSE TIME (sec)
100 1000
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device Marking Package Shipping
NVMFD5C446NLT1G 5C446L DFN8
(Pb−Free)
NVMFD5C446NLWFT1G 446LWF DFN8
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1500 / Tape & Reel
1500 / Tape & Reel
†
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5
Page 6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
1
SCALE 2:1
PIN ONE
IDENTIFIER
NOTE 7
0.10 C
0.10 C
NOTE 4
DETAIL B
M
1234
TOP VIEW
SIDE VIEW
D3
e
14
N
8
4X
G
K1
BOTTOM VIEW
D
D1
78
D2
5
56
2X
DETAIL A
4X
4X
b1
0.20 C
A
E1
A
L
8X
B
2X
0.20 C
E
c
SEATING
C
PLANE
NOTE 6
K
DETAIL B
ALTERNATE
CONSTRUCTION
E2
b
C
A0.10 B
0.05
C
NOTE 3
CASE 506BT
ISSUE E
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
4X
h
GENERIC
MARKING DIAGRAM*
A1
*This information is generic. Please refer
to device data sheet for actual part
marking.
1
XXXXXX
AYWZZ
XXXXXX= Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
SOLDERING FOOTPRINT*
4.56
8X
0.75
4.84
2.30
DATE 26 FEB 2013
MILLIMETERS
3.70
MAX
0.42
4.90
4.10
5.90
4.15
0.55
0.61
3.50
2X
0.56
6.59
DIM MIN
A 0.90
A1 −−−
b 0.33
b1 0.33 0.42
c 0.20
D 5.15 BSC
D1 4.70
D2 3.90
D3 1.50 1.70
E 6.15 BSC
E1 5.70
E2 3.90
e 1.27 BSC
G 0.45
h −−−
K 0.51
K1 0.56 −−−
L 0.48
M 3.25
N 1.80 2.00
2X
2.08
4X
1.40
−−−
−−−
−−−
−−−
−−−
MAX
1.10
0.05
0.51
0.51
0.33
5.10
4.30
1.90
6.10
4.40
0.65
12
−−−
−−−
0.71
3.75
2.20
_
0.70
4X
1.00
1.27
PITCH
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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