ON Semiconductor NVMFD5873NL User Manual

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Page 1

NVMFD5873NL

)

Power MOSFET

60 V, 13 mW, 58 A, Dual N−Channel Logic Level, Dual SO−8FL

Features

• Small Footprint (5x6 mm) for Compact Designs

• Low R

• Low Capacitance to Minimize Driver Losses

• NVMFD5873NLWF − Wettable Flanks Option for Enhanced Optical

Inspection

• AEC−Q101 Qualified and PPAP Capable

• This is a Pb−Free Device

MAXIMUM RATINGS (T

Drain−to−Source Voltage V Gate−to−Source Voltage V Continuous Drain Cur

rent R

2, 3, 4) Power Dissipation

J−mb

Continuous Drain Cur rent R

& 4) Power Dissipation

(Notes 1 & 3)

Pulsed Drain Current Operating Junction and Storage Temperature TJ, T

Source Current (Body Diode) I Single Pulse Drain−to−Source Avalanche

Energy (TJ = 25°C, VGS = 10 V, I L = 0.1 mH, R

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)

Junction−to−Mounting Board (top) − Steady State (Notes 2, 3)

Junction−to−Ambient − Steady State (Note 3) R

1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted.

2. P si (Y) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface.

3. Surface−mounted on FR4 board using a 650 mm

4. Maximum current for pulses as long as 1 second are higher but are dependent on pulse duration and duty cycle.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise noted)

Parameter

(Notes 1,

J−mb

(Notes 1, 2, 3

(Notes 1, 3

= 25 W)

Steady

State

Steady

State

TA = 25°C, t

L(pk)

Parameter

Symbol Value Unit

stg

60 V

"20 V

107

3.1

190 A

−55 to 175

58 A 40 mJ

260 °C

1.4

DSS

Tmb = 25°C

Tmb = 100°C 41

Tmb = 25°C

Tmb = 100°C 54

TA = 25°C

TA = 100°C 7.0

TA = 25°C

TA = 100°C 1.6

= 10 ms

= 28.3 A,

Symbol Value Unit

J−mb

, 2 oz. Cu pad.

°C

°C/W

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(BR)DSS

60 V

DS(on)

13 mW @ 10 V

16.5 mW @ 4.5 V

Dual N−Channel

MAX ID MAX

58 A

MARKING DIAGRAM

DFN8 5x6

(SO8FL)

CASE 506BT

5873NL = Specific Device Code

5873LW = Specific Device Code

A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability

S1 G1 S2 G2

for NVMFD5873NL

for NVMFD5873NLWF

5873xx

AYWZZ

D1 D1 D2 D2

ORDERING INFORMATION

Device Package Shipping

NVMFD5873NLT1G DFN8

(Pb−Free)

NVMFD5873NLWFT1G DFN8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

1500 / Tape &

Reel

1500 / Tape &

Reel

†

September, 2014 − Rev. 3

1 Publication Order Number:

NVMFD5873NL/D

Page 2

NVMFD5873NL

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise specified)

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage

Temperature Coefficient Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

(BR)DSS/TJ

DSS

GSS

VGS = 0 V, ID = 250 mA

VGS = 0 V,

= 60 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage Threshold Temperature Coefficient V Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V, ID = 15 A 10.7 13 mW

VGS = 4.5 V, ID = 10 A 13.6 16.5

Forward Transconductance g

VDS = 5.0 V, ID = 15 A 15 S

CHARGES AND CAPACITANCES

Input Capacitance Output Capacitance C Reverse Transfer Capacitance C Total Gate Charge Q Threshold Gate Charge Q Gate−to−Source Charge Q Gate−to−Drain Charge Q Total Gate Charge Q

iss oss rss

G(TOT)

G(TH)

GS GD

G(TOT)

VGS = 0 V, f = 1.0 MHz, VDS = 25 V

VGS = 4.5 V, VDS = 48 V,

ID = 15 A

VGS = 10 V, VDS = 48V, ID = 15 A 30.5 nC

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time Rise Time t Turn−Off Delay Time t Fall Time t Turn−On Delay Time t Rise Time t Turn−Off Delay Time t Fall Time t

d(on)

d(off)

d(on)

d(off)

VGS = 4.5 V, VDS = 48 V,

= 15 A, RG = 2.5 W

VGS = 10 V, VDS = 48 V,

= 15 A, RG = 2.5 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t Charge Time t Discharge Time t Reverse Recovery Charge Q

b RR

VGS = 0 V,

= 15 A

VGS = 0 V, dIS/dt = 100 A/ms,

= 15 A

5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

60 V

54.9 mV/°C

TJ = 25°C 1.0 mA

TJ = 125°C 100

1.5 2.5 V

−5.8 mV/°C

1560

145

16.5

1.3

4.0

8.8

10.8 51 21

42.6

9.5 13 25

6.6

TJ = 25°C 0.8 1.0

TJ = 125°C 0.7

22.4

14.5

9.0 18 nC

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NVMFD5873NL

TYPICAL CHARACTERISTICS

10 V

, DRAIN CURRENT (A)

0.0 1.0 2.0 3.0 4.0 5.0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)

4.5 V

VGS = 3.0 V

TJ = 25°C

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.025 ID = 15 A

0.020

0.015

0.010

3.8 V

3.4 V

= 25°C

VDS ≥ 10 V

TJ = 25°C

, DRAIN CURRENT (A)

0.0200

0.0175

0.0150

0.0125

0.0100

0.0075

TJ = 125°C

2.0 2.5 3.0 3.5 4.0 4.5

TJ = 25°C

TJ = −55°C

VGS = 4.5 V

VGS = 10 V

, DRAIN−TO−SOURCE RESISTANCE (W)

0.005

2345678910

DS(on)

2.4

2.2

2.0

1.8

1.6

1.4

1.2

, DRAIN−TO−SOURCE

1.0

DS(on)

RESISTANCE (NORMALIZED)

0.8

0.6

−50 −25 0 25 50 75 100 125 150 175

VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)

Figure 3. On−Resistance vs. V

ID = 15 A

= 10 V

TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 5. On−Resistance Variation with

Temperature

, DRAIN−TO−SOURCE RESISTANCE (W)

0.0050 5 1015202530

DS(on)

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

100000

VGS = 0 V

10000

, LEAKAGE (nA)

1000

DDS

100

10 20 30 40 50 60

TJ = 150°C

TJ = 125°C

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

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Page 4

NVMFD5873NL

TYPICAL CHARACTERISTICS

2000

VGS = 0 V

iss

= 25°C

1500

1000

500

C, CAPACITANCE (pF)

oss

rss

0 102030405060

VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation Figure 8. Gate−to−Source and

1000

VDS = 48 V

= 15 A

= 10 V

100

d(off)

, GATE−TO−SOURCE VOLTAGE (V)

0 5 10 15 20 25 30 35

Drain−to−Source Voltage vs. Total Charge

VGS = 0 V

TJ = 25°C

60 50 40

TJ = 25°C

= 48 V

= 15 A

t, TIME (ns)

1 10 100

RG, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time Variation

vs. Gate Resistance

100

NVMFD5873NL

, DRAIN CURRENT (A)

FBSOA

TA = 25°C, 650 mm2, 2 oz Cu Pad, V

0.1

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 11. Maximum Rated Forward Biased

d(on)

, SOURCE CURRENT (A)

= 10 V

Safe Operating Area

30 20 10

0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 V

, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 10. Diode Forward Voltage vs. Current

0.01 ms

0.1 ms

1 ms

10 ms

1001010.1

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Page 5

NVMFD5873NL

TYPICAL CHARACTERISTICS

100

Duty Cycle = 50%

20%

10%

5% 2%

(°C/W)

(t)

0.1

Single Pulse

0.01

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec)

Figure 12. Thermal Response

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Page 6

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)

SCALE 2:1

PIN ONE

IDENTIFIER

NOTE 7

0.10 C

NOTE 4

DETAIL B

BOTTOM VIEW

1234

TOP VIEW

SIDE VIEW

0.20 C

DETAIL A

0.05

0.20 C

SEATING

PLANE

NOTE 6

DETAIL B

ALTERNATE

CONSTRUCTION

A0.10 B

NOTE 3

CASE 506BT

ISSUE E

DETAIL A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.

4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.

6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.

7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.

GENERIC

MARKING DIAGRAM*

*This information is generic. Please refer

to device data sheet for actual part marking.

XXXXXX

AYWZZ

XXXXXX= Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability

SOLDERING FOOTPRINT*

4.56

0.75

4.84

2.30

DATE 26 FEB 2013

MILLIMETERS

3.70

MAX

0.42

4.90

4.10

5.90

4.15

0.55

0.61

3.50

0.56

6.59

DIM MIN

A 0.90

A1 −−−

b 0.33

b1 0.33 0.42

c 0.20

D 5.15 BSC D1 4.70 D2 3.90 D3 1.50 1.70

E 6.15 BSC E1 5.70 E2 3.90

e 1.27 BSC

G 0.45

h −−−

K 0.51 K1 0.56 −−−

L 0.48 M 3.25 N 1.80 2.00

2.08

1.40

−−−

MAX

1.10

0.05

0.51

0.33

5.10

4.30

1.90

6.10

4.40

0.65 12

−−−

0.71

3.75

2.20

0.70

1.00

1.27 PITCH

5.55

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98AON50417E

DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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ON Semiconductor NVMFD5873NL User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual