Page 1
NTMD6N04, NVMD6N04
MOSFET – Power, Dual
N-Channel, SOIC-8
40 V, 5.8 A
Features
• Designed for use in low voltage, high speed switching applications
• Ultra Low On−Resistance Provides
Higher Efficiency and Extends Battery Life
− R
− R
• Miniature SOIC−8 Surface Mount Package Saves Board Space
• Diode is Characterized for Use in Bridge Circuits
• Diode Exhibits High Speed, with Soft Recovery
• NVMD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable*
• These Devices are Pb−Free and are RoHS Compliant
Applications
• DC−DC Converters
• Computers
• Printers
• Cellular and Cordless Phones
• Disk Drives and Tape Drives
MAXIMUM RATINGS (T
Drain−to−Source Voltage V
Gate−to−Source Voltage − Continuous V
Drain Current (Note 1)
− Continuous @ T
− Single Pulse (tp ≤ 10 ms)
Drain Current (Note 2)
− Continuous @ T
Total Power Dissipation
@ T
= 25°C (Note 1)
A
@ TA = 25°C (Note 2)
Operating and Storage Temperature
Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
(VDD = 40 Vdc, VGS = 5.0 Vdc,
Vdc, Peak IL = 7.0 Apk,
L = 10 mH, R
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for
Soldering Purposes for 10 Sec
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 1″ pad size, t ≤ 10 s
= 0.027 W, VGS = 10 V (Typ)
DS(on)
= 0.034 W, VGS = 4.5 V (Typ)
DS(on)
= 25°C unless otherwise noted)
J
Rating
= 25°C
A
= 25°C
A
= 25°C
J
= 25 W)
G
Symbol Value Unit
DSS
I
I
DM
I
P
TJ, T
E
R
T
GS
D
D
AS
q
D
stg
JA
L
40 V
"20 V
5.8
29
4.6 Adc
2.0
1.29
−55 to +150 °C
245 mJ
62.5
97
260 °C
Adc
Apk
W
°C/W
http://onsemi.com
G
V
DSS
40 V
R
27 mW @ V
N−Channel
D
S
Typ ID Max
DS(ON)
= 10 V
GS
G
5.8 A
D
S
MARKING DIAGRAM &
PIN ASSIGNMENT
8
1
SOIC−8
CASE 751
STYLE 11
E6N04 = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
D1 D1 D2 D2
8
E6N04
AYWW G
G
1
S1 G1 S2 G2
ORDERING INFORMATION
Device Package Shipping
NTMD6N04R2G SOIC−8
(Pb−Free)
NVMD6N04R2G* SOIC−8
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
2500 / Tape &
2500 / Tape &
†
Reel
Reel
© Semiconductor Components Industries, LLC, 2013
July, 2019 − Rev. 2
1 Publication Order Number:
NTMD6N04R2/D
Page 2
NTMD6N04, NVMD6N04
2. When surface mounted to an FR4 board using 1″ pad size, t = steady state
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2
Page 3
NTMD6N04, NVMD6N04
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
C
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
= 0 Vdc, ID = 250 mA)
(V
GS
Temperature Coefficient (Positive)
V
Zero Gate Voltage Drain Current
(V
= 40 Vdc, VGS = 0 Vdc, TJ = 25°C)
DS
(VDS = 40 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate−Body Leakage Current
(V
= ±20 Vdc, VDS = 0 Vdc)
GS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
= VGS, ID = 250 mAdc)
(V
DS
Temperature Coefficient (Negative)
Static Drain−to−Source On−State Resistance
(V
= 10 Vdc, ID = 5.8 Adc)
GS
= 4.5 Vdc, ID = 3.9 Adc)
(V
GS
Forward Transconductance
(V
= 10 Vdc, ID = 5.8 Adc)
DS
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance C
(VDS = 32 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance C
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t
(VDD = 20 Vdc, ID = 5.8 A,
V
= 10 V,
GS
= 6 W)
R
G
Fall Time t
Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t
(VDD = 20 Vdc, ID = 5.8 A,
V
= 4.5 V,
GS
= 6 W)
R
G
Fall Time t
Gate Charge
(VDS = 20 Vdc,
V
= 10 Vdc,
GS
ID = 5.8 A)
BODY−DRAIN DIODE RATINGS (Note 3)
Diode Forward On−Voltage (IS = 1.7 Adc, VGS = 0 V)
(I
= 1.7 Adc, VGS = 0 V, TJ = 150°C)
S
Reverse Recovery Time
(IS = 1.7 A, VGS = 0 V,
/dt = 100 A/ms)
dI
S
Reverse Recovery Stored Charge
= 1.7 A, dIS/dt = 100 A/ms, VGS = 0 V)
(I
S
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
Symbol Min Typ Max Unit
Vdc
V
(BR)DSS
(BR)DSS/TJ
I
DSS
I
GSS
40
−
−
−
47
45
−
−
−
−
1.0
10
− − "100
mV/°C
mAdc
nAdc
Vdc
V
GS(th)
V
GS(th)/TJ
R
DS(on)
g
FS
C
iss
oss
rss
t
d(on)
d(off)
t
d(on)
d(off)
Q
Q
gs
Q
gd
V
SD
t
rr
t
a
t
b
Q
RR
r
f
r
f
T
1.0
−
−
−
1.9
4.7
0.027
0.034
3.0
−
0.034
0.043
mV/°C
Mhos
− 8.12 −
− 723 900
− 156 225
− 53 75
− 10 18
− 20 35
− 45 70
− 40 65
− 15 −
− 55 −
− 30 −
− 35 −
− 20 30
− 2.5 −
− 5.5 −
−
−
0.76
0.56
1.1
−
− 23 −
− 16 −
− 7 −
− 20 − nC
Vdc
W
pF
ns
ns
nC
ns
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3
Page 4
NTMD6N04, NVMD6N04
14
12
6 V − 10 V
4.0 V
3.8 V
10
8
3.6 V
6
4
, DRAIN CURRENT (A)
D
I
2
2.4 V
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
Figure 1. On−Region Characteristics
0.2
0.15
0.1
TJ = 25°C
3.4 V
3.2 V
3.0 V
2.8 V
VGS = 2.6 V
20
VDS w 10 V
18
16
14
12
10
8
6
, DRAIN CURRENT (A)
D
4
I
TJ = 25°C
TJ = 100°C
TJ = −55°C
2
0
1.5 2 2.5 3 3.5 4
, GATE−TO−SOURCE VOLTAGE (V)
V
GS
Figure 2. Transfer Characteristics
VGS = 10 V
= 25°C
T
J
0.05
0
, DRAIN−TO−SOURCE RESISTANCE (W)
2345678910
DS(on)
R
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 3. On−Resistance vs. Gate−to−Source
1.8
ID = 5.8 A
1.7
1.6
= 10 V
V
GS
1.5
1.4
1.3
1.2
1.1
1
0.9
(NORMALIZED)
0.8
0.7
, DRAIN−TO−SOURCE RESISTANCE
0.6
−50 −25 0 25 50 75 100 125 150
DS(on)
R
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. On Resistance Variation with
Temperature
Voltage
10000
VGS = 0 V
TJ = 150°C
1000
100
, LEAKAGE (nA)
DSS
10
I
TJ = 100°C
1
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. Drain−to−Source Leakage Current
vs. Voltage
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4
Page 5
NTMD6N04, NVMD6N04
2400
VDS = 0 V
= 0 V
V
GS
1800
1200
600
C, CAPACITANCE (pF)
C
iss
C
rss
0
−10 −50 5 101520
V
GS
V
DS
TJ = 25°C
C
iss
C
oss
C
rss
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLT-
AGE (V)
Figure 6. Capacitance Variation
4
VGS = 0 V
3.5
= 25°C
T
J
3
2.5
2
1.5
, SOURCE CURRENT (A)
1
S
I
0.5
0
0.4 0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 8. Diode Forward Voltage vs. Current
10
Q
T
8
V
DS
V
GS
6
Q
1
Q
2
2
, GATE−TO−SOURCE VOLTAGE (V)
GS
V
0
ID = 5.8 A
= 25°C
T
J
0 3 6 9 12 15 18 21
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
100
VGS = 20 V
Single Pulse T
TA = 25°C
10
C
1
R
DS(on)
THERMAL LIMIT
0.1
, DRAIN CURRENT (A)
D
I
PACKAGE LIMIT
Mounted on FR4 board using 1 in pad size,
0.01
with die operating 10s max.
0.1 1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
25
20
15
10
5
0
10 ms
100 ms
1 ms
10 ms
dc
DRAIN−TO−SOURCE VOLTAGE (V)
DS,
V
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5
Page 6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
8
1
SCALE 1:1
−Y−
−Z−
−X−
A
58
B
1
4
G
H
D
0.25 (0.010) Z
M
SOLDERING FOOTPRINT*
7.0
0.275
S
Y
0.25 (0.010)
C
SEATING
PLANE
SXS
0.060
0.10 (0.004)
1.52
4.0
0.155
CASE 751−07
M
M
Y
N
SOIC−8 NB
ISSUE AK
K
X 45
_
M
J
MARKING DIAGRAM*
8
XXXXX
ALYWX
1
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
8
XXXXX
ALYWX
G
1
IC
IC
(Pb−Free)
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
____
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
INCHES
GENERIC
8
XXXXXX
AYWW
1
Discrete
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
8
XXXXXX
AYWW
1
Discrete
(Pb−Free)
G
0.6
0.024
1.270
0.050
SCALE 6:1
ǒ
inches
mm
Ǔ
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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Page 7
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
SOIC−8 NB
CASE 751−07
ISSUE AK
STYLE 3:
STYLE 7:
STYLE 11:
STYLE 15:
STYLE 19:
STYLE 23:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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Page 8
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