ON Semiconductor NV34C02WF User Manual

NV34C02WF

EEPROM SPD 2-kb I2C for DDR2 DIMM

Description

The NV34C02WF is a EEPROM Serial 2−kb, internally organized

as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each.

It features a 16−byte page write buffer and supports both the

Standard (100 kHz) as well as Fast (400 kHz) I

Write operations can be inhibited by taking the WP pin High (this protects the entire memory) or by setting an internal Write Protect flag via Software command (this protects the lower half of the memory).

In addition to Permanent Software Write Protection, the NV34C02WF also features JEDEC compatible Reversible Software Write Protection for DDR2 Serial Presence Detect (SPD) applications operating over the 1.7 V to 3.6 V supply voltage range.

The NV34C02WF is fully backwards compatible with earlier DDR1 SPD applications operating over the 1.7 V to 5.5 V supply voltage range.

Features

• Supports Standard and Fast I

C Protocol

• 1.7 V to 5.5 V Supply Voltage Range

• 16−Byte Page Write Buffer

• Hardware Write Protection for Entire Memory

• Software Write Protection for Lower 128 Bytes

• Schmitt Triggers and Noise Suppression Filters on I

(SCL and SDA)

• Low power CMOS Technology

• 1,000,000 Program/Erase Cycles

• 100 Year Data Retention

• Automotive Grade 1 Temperature Range

• This Device is Pb−Free, Halogen Free/BFR Free and RoHS

Compliant*

C protocol.

C Bus Inputs

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UDFN8

U SUFFIX

CASE 517DH

PIN CONFIGURATION

US8 (U)

PART MARKING

XXXXX

AWLYWG

XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

SCL

SDA

SCL

A2, A1, A

NV34C02WF

SDA

Figure 1. Functional Symbol

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

May, 2018 − Rev. 0

1 Publication Order Number:

PIN FUNCTION

FunctionPin Name

Device Address InputA0, A1, A

Serial Data Input/OutputSDA

Serial Clock InputSCL

Write Protect InputWP

Power SupplyV

GroundV

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.

NV34C02WF/D

NV34C02WF

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Unit

Operating Temperature −45 to +130 °C

Storage Temperature −65 to +150 °C

Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V

Voltage on Pin A0 with Respect to Ground −0.5 to +10.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V

undershoot to no less than −1.5 V or overshoot to no more than V

+ 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol

(Note 3) Endurance 1,000,000 Program/ Erase Cycles

END

Data Retention 100 Years

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Page Mode, V

= 5 V, 25°C

Parameter Min Units

+ 0.5 V. During transitions, the voltage on any pin may

Table 3. D.C. OPERATING CHARACTERISTICS (V

Symbol

Parameter Test Conditions Min Max Units

Supply Current

VCC < 3.6 V, f

VCC > 3.6 V, f

Standby Current All I/O Pins at GND or V

I/O Pin Leakage Pin at GND or V

Input Low Voltage −0.5 0.3 x V

Input High Voltage 0.7 x V

Output Low Voltage

VCC > 2.5 V, IOL = 3 mA 0.4

= 1.7 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)

= 100 kHz 1

SCL

= 400 kHz 2

SCL

TA = −40°C to +125°C

≤ 3.3 V

TA = −40°C to +125°C V

> 3.3 V

CCVCC

1 mA

+ 0.5

VCC < 2.5 V, IOL = 1 mA 0.2

Table 4. PIN IMPEDANCE CHARACTERISTICS (V

= 1.7 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)

Symbol Parameter Conditions Max Units

CIN (Note 4)

SDA I/O Pin Capacitance

VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V

Other Input Pins 6

IWP (Note 5) WP Input Current

VIN < VIH, VCC = 5.5 V 130 mA

VIN < VIH, VCC = 3.6 V 120

VIN < VIH, VCC = 1.7 V 80

IA (Note 5) Address Input Current

(A0, A1, A2) Product Rev H

VIN > V

VIN < VIH, VCC = 5.5 V 50 mA

VIN < VIH, VCC = 3.6 V 35

VIN < VIH, VCC = 1.7 V 25

VIN > V

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is

relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V source.

), the strong pull-down reverts to a weak current

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NV34C02WF

Table 5. A.C. CHARACTERISTICS (V

= 1.7 V to 5.5 V, TA = −40°C to +125°C) (Note 6)

Standard Fast

Symbol

SCL

HD:STA

LOW

HIGH

SU:STA

HD:DAT

SU:DAT

Parameter

Clock Frequency 100 400 kHz

START Condition Hold Time 4 0.6

Low Period of SCL Clock 4.7 1.3

High Period of SCL Clock 4 0.6

START Condition Setup Time 4.7 0.6

Data Hold Time 0 0

Data Setup Time 250 100 ns

Min Max Min Max

Units

tR (Note 7) SDA and SCL Rise Time 1000 300 ns

tF (Note 7) SDA and SCL Fall Time 300 300 ns

SU:STO

BUF

STOP Condition Setup Time 4 0.6

Bus Free Time Between STOP and START 4.7 1.3

SCL Low to SDA Data Out 3.5 0.9

Data Out Hold Time 100 100 ns

Ti (Note 7) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns

SU:WP

HD:WP

WP Setup Time 0 0

WP Hold Time 2.5 2.5

Write Cycle Time 5 5 ms

tPU (Notes 7 & 8) Power−up to Ready Mode 1 1 ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

6. Test conditions according to “A.C. Test Conditions” table.

7. Tested initially and after a design or process change that affects this parameter.

is the delay between the time VCC is stable and the device is ready to accept commands.

8. t

Table 6. A.C. TEST CONDITIONS

Input Levels 0.2 VCC to 0.8 V

Input Rise and Fall Times ≤ 50 ns

Input Reference Levels 0.3 VCC, 0.7 V

Output Reference Levels 0.5 V

Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF

ORDERING INFORMATION

Device Marking Package Shipping

NV34C02WF TBD UDFN8

3000 / Tape & Reel

(Pb−Free)

9. All packages are RoHS−compliant (Lead−free, Halogen−free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

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NV34C02WF

Power−On Reset (POR)

The NV34C02WF incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state.

The NV34C02WF will power up into Standby mode after V

exceeds the POR trigger level and will power down into

Reset mode when V

drops below the POR trigger level.

This bi−directional POR feature protects the device against ‘brown−out’ failure following a temporary loss of power.

Pin Description

SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master.

SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL.

, A1 and A2: The Address pins accept the device address.

These pins have on−chip pull−down resistors.

WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. This pin has an on−chip pull−down resistor.

Functional Description

The NV34C02WF supports the Inter−Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The NV34C02WF acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A and A

C Bus Protocol

two wires are connected to the V

The I

C bus consists of two ‘wires’, SCL and SDA. The

supply via pull−up

, A1,

resistors. Master and Slave devices connect to the 2−wire bus via their respective SCL and SDA pins. The transmitting

device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.

Data transfer may be initiated only when the bus is not

busy (see A.C. Characteristics).

During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 2).

Start

The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands.

Stop

The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby mode (when following a Read command).

Device Addressing

The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 3). The next 3 bits, A devices. The last bit, R/W

, A1 and A0, select one of 8 possible Slave

, specifies whether a Read (1) or

Write (0) operation is to be performed.

Acknowledge

After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line

during the 9

clock cycle (Figure 4). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9

clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 5.

SDA

SCL

START BIT

STOP BIT

Figure 2. Start/Stop Timing

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