NV34C02WF
EEPROM SPD 2-kb I2C for
DDR2 DIMM
Description
The NV34C02WF is a EEPROM Serial 2−kb, internally organized
as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each.
It features a 16−byte page write buffer and supports both the
Standard (100 kHz) as well as Fast (400 kHz) I
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory) or by setting an internal Write Protect flag
via Software command (this protects the lower half of the memory).
In addition to Permanent Software Write Protection, the
NV34C02WF also features JEDEC compatible Reversible
Software Write Protection for DDR2 Serial Presence Detect (SPD)
applications operating over the 1.7 V to 3.6 V supply voltage range.
The NV34C02WF is fully backwards compatible with earlier
DDR1 SPD applications operating over the 1.7 V to 5.5 V supply
voltage range.
Features
• Supports Standard and Fast I
2
C Protocol
• 1.7 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Software Write Protection for Lower 128 Bytes
• Schmitt Triggers and Noise Suppression Filters on I
(SCL and SDA)
• Low power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Automotive Grade 1 Temperature Range
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
V
CC
2
C protocol.
2
C Bus Inputs
www.onsemi.com
1
UDFN8
U SUFFIX
CASE 517DH
PIN CONFIGURATION
A
A
A
V
SS
1
0
1
2
US8 (U)
PART MARKING
1
XXXXX
AWLYWG
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
V
CC
WP
SCL
SDA
SCL
A2, A1, A
WP
0
NV34C02WF
V
SS
SDA
Figure 1. Functional Symbol
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2018
May, 2018 − Rev. 0
1 Publication Order Number:
PIN FUNCTION
FunctionPin Name
Device Address InputA0, A1, A
2
Serial Data Input/OutputSDA
Serial Clock InputSCL
Write Protect InputWP
CC
SS
Power SupplyV
GroundV
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
NV34C02WF/D
NV34C02WF
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Unit
Operating Temperature −45 to +130 °C
Storage Temperature −65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V
Voltage on Pin A0 with Respect to Ground −0.5 to +10.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
undershoot to no less than −1.5 V or overshoot to no more than V
+ 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
N
(Note 3) Endurance 1,000,000 Program/ Erase Cycles
END
T
DR
Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
= 5 V, 25°C
CC
Parameter Min Units
+ 0.5 V. During transitions, the voltage on any pin may
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V
Symbol
I
CC
I
SB
I
L
V
IL
V
IH
V
OL
Parameter Test Conditions Min Max Units
Supply Current
VCC < 3.6 V, f
VCC > 3.6 V, f
Standby Current All I/O Pins at GND or V
I/O Pin Leakage Pin at GND or V
Input Low Voltage −0.5 0.3 x V
Input High Voltage 0.7 x V
Output Low Voltage
VCC > 2.5 V, IOL = 3 mA 0.4
= 1.7 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
CC
= 100 kHz 1
SCL
= 400 kHz 2
SCL
TA = −40°C to +125°C
CC
V
≤ 3.3 V
CC
TA = −40°C to +125°C
V
> 3.3 V
CC
CC
CCVCC
mA
1 mA
3
2
mA
CC
+ 0.5
V
VCC < 2.5 V, IOL = 1 mA 0.2
Table 4. PIN IMPEDANCE CHARACTERISTICS (V
= 1.7 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
CC
Symbol Parameter Conditions Max Units
CIN (Note 4)
SDA I/O Pin Capacitance
VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V
8
pF
Other Input Pins 6
IWP (Note 5) WP Input Current
VIN < VIH, VCC = 5.5 V 130 mA
VIN < VIH, VCC = 3.6 V 120
VIN < VIH, VCC = 1.7 V 80
IA (Note 5) Address Input Current
(A0, A1, A2)
Product Rev H
VIN > V
IH
VIN < VIH, VCC = 5.5 V 50 mA
VIN < VIH, VCC = 3.6 V 35
2
VIN < VIH, VCC = 1.7 V 25
VIN > V
IH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is
relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To
conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
source.
), the strong pull-down reverts to a weak current
CC
www.onsemi.com
2
NV34C02WF
Table 5. A.C. CHARACTERISTICS (V
= 1.7 V to 5.5 V, TA = −40°C to +125°C) (Note 6)
CC
Standard Fast
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
Parameter
Clock Frequency 100 400 kHz
START Condition Hold Time 4 0.6
Low Period of SCL Clock 4.7 1.3
High Period of SCL Clock 4 0.6
START Condition Setup Time 4.7 0.6
Data Hold Time 0 0
Data Setup Time 250 100 ns
Min Max Min Max
Units
ms
ms
ms
ms
ms
tR (Note 7) SDA and SCL Rise Time 1000 300 ns
tF (Note 7) SDA and SCL Fall Time 300 300 ns
t
SU:STO
t
BUF
t
AA
t
DH
STOP Condition Setup Time 4 0.6
Bus Free Time Between STOP and START 4.7 1.3
SCL Low to SDA Data Out 3.5 0.9
ms
ms
ms
Data Out Hold Time 100 100 ns
Ti (Note 7) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns
t
SU:WP
t
HD:WP
t
WR
WP Setup Time 0 0
WP Hold Time 2.5 2.5
ms
ms
Write Cycle Time 5 5 ms
tPU (Notes 7 & 8) Power−up to Ready Mode 1 1 ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
is the delay between the time VCC is stable and the device is ready to accept commands.
8. t
PU
Table 6. A.C. TEST CONDITIONS
Input Levels 0.2 VCC to 0.8 V
Input Rise and Fall Times ≤ 50 ns
Input Reference Levels 0.3 VCC, 0.7 V
Output Reference Levels 0.5 V
CC
Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
CC
CC
ORDERING INFORMATION
Device Marking Package Shipping
NV34C02WF TBD UDFN8
3000 / Tape & Reel
(Pb−Free)
9. All packages are RoHS−compliant (Lead−free, Halogen−free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
www.onsemi.com
3
NV34C02WF
Power−On Reset (POR)
The NV34C02WF incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
The NV34C02WF will power up into Standby mode after
V
exceeds the POR trigger level and will power down into
CC
Reset mode when V
drops below the POR trigger level.
CC
This bi−directional POR feature protects the device against
‘brown−out’ failure following a temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A
, A1 and A2: The Address pins accept the device address.
0
These pins have on−chip pull−down resistors.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor.
Functional Description
The NV34C02WF supports the Inter−Integrated Circuit
(I2C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The NV34C02WF acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
the bus as determined by the device address inputs A
and A
.
2
2
C Bus Protocol
I
two wires are connected to the V
2
The I
C bus consists of two ‘wires’, SCL and SDA. The
supply via pull−up
CC
, A1,
0
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
Start
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
Stop
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when following a
Write command) or sends the Slave into standby mode
(when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 3 bits, A
devices. The last bit, R/W
, A1 and A0, select one of 8 possible Slave
2
, specifies whether a Read (1) or
Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
th
during the 9
clock cycle (Figure 4). The Slave will also
acknowledge the byte address and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9
th
clock cycle. If
the Master acknowledges the data, then the Slave continues
transmitting. The Master terminates the session by not
acknowledging the last data byte (NoACK) and by sending
a STOP to the Slave. Bus timing is illustrated in Figure 5.
SDA
SCL
START BIT
STOP BIT
Figure 2. Start/Stop Timing
www.onsemi.com
4
NV34C02WF
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
1010
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
189
START
ACK DELAY (≤ t
Figure 4. Acknowledge Timing
t
F
t
LOW
t
HIGH
A
A
1
2
DEVICE ADDRESS
)
AA
t
R
t
LOW
A
R/W
0
BUS RELEASE DELAY
(RECEIVER)
ACK SETUP (≥ t
SU:DAT
)
SCL
t
AA
t
HD:DAT
SDA IN
SDA OUT
t
SU:STA
t
HD:STA
Figure 5. Bus Timing
Write Operations
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, byte address and data to be written
(Figure 6). The Slave acknowledges all 3 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Page Write
The NV34C02WF contains 256 bytes of data, arranged in
16 pages of 16 bytes each. A page is selected by the 4 most
significant bits of the address byte following the Slave
address, while the 4 least significant bits point to the byte
within the page. Up to 16 bytes can be written in one Write
cycle (Figure 8).
t
SU:DAT
t
DH
t
SU:STO
t
BUF
The internal byte address counter is automatically
incremented after each data byte is loaded. If the Master
transmits more than 16 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
NV34C02WF is busy writing or is ready to accept
commands. Polling is implemented by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS).
The NV34C02WF will not acknowledge the Slave
address, as long as internal Write is in progress.
www.onsemi.com
5
NV34C02WF
Delivery State
The NV34C02WF is shipped ‘unprotected’, i.e. neither
SWP flag is set. The entire 2 kb memory is erased, i.e. all
bytes are FFh.
S
T
BUS ACTIVITY:
MASTER
SDA LINE
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
S
T
O
P
P
SCL
SDA
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
8th Bit
Byte n
SLAVE
ADDRESS
A
C
K
Figure 6. Byte Write Timing
ACK
STOP
CONDITION
Figure 7. Write Cycle Timing
BYTE
ADDRESS (n)
DATA n
t
WR
A
C
K
START
CONDITION
DATA n+1
A
C
K
ADDRESS
S
T
DATA n+P
O
P
P
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
A
C
K
A
C
K
Figure 8. Page Write Timing
www.onsemi.com
6
A
C
K
A
C
K
SCL
NV34C02WF
BYTE ADDRESS DATA
1891 8
SDA
WP
A
7
A
0
Figure 9. WP Timing
Read Operations
Immediate Address Read
In standby mode, the NV34C02WF internal address
counter points to the data byte immediately following the
last byte accessed by a previous operation. If that ‘previous’
byte was the last byte in memory, then the address counter
will point to the 1
st
memory byte, etc.
When, following a START, the NV34C02WF is presented
with a Slave address containing a ‘1’ in the R/W
(Figure 10), it will acknowledge (ACK) in the 9
bit position
th
clock cycle,
and will then transmit data being pointed at by the internal
address counter. The Master can stop further transmission by
issuing a NoACK, followed by a STOP condition.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address counter.
t
SU:WP
D
t
HD:WP
7
D
0
The address counter can be initialized by performing a
‘dummy’ Write operation (Figure 11). Here the START is
followed by the Slave address (with the R/W
bit set to ‘0’)
and the desired byte address. Instead of following up with
nd
data, the Master then issues a 2
START, followed by the
‘Immediate Address Read’ sequence, as described earlier.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the NV34C02WF, then the device will continue
transmitting as long as each data byte is acknowledged by
the Master (Figure 12). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap−around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting byte
address.
BUS ACTIVITY:
MASTER
SDA LINE
SCL
SDA 8th Bit
8
Figure 10. Immediate Address Read Timing
S
T
A
SLAVE
R
ADDRESS
T
S
www.onsemi.com
7
S
T
O
P
P
A
DATA
C
K
9
NO ACKDATA OUT
N
O
A
C
K
STOP
NV34C02WF
S
T
BUS ACTIVITY:
MASTER
SDA LINE
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS (n)
A
C
K
Figure 11. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
ADDRESS
A
C
K
A
C
K
Figure 12. Sequential Read Timing
Software Write Protection
The lower half of memory (first 128 bytes) can be
protected against Write requests by setting one of two
Software Write Protection (SWP) flags.
The Permanent Software Write Protection (PSWP) flag
can be set or read while all address pins are at regular CMOS
levels (GND or V
), whereas the very high voltage V
CC
HV
must be present on address pin A0 to set, clear or read the
Reversible Software Write Protection (RSWP) flag. The
D.C. OPERATING CONDITIONS for RSWP operations
are shown in Table 7.
The SWP commands are listed in Table 8. All commands
are preceded by a START and terminated with a STOP,
following the ACK or NoACK from the NV34C02WF. All
SWP related Slave addresses use the pre−amble: 0110 (6h),
instead of the regular 1010 (Ah) used for memory access.
For PSWP commands, the three address pins can be at any
logic level, whereas for RSWP commands the address pins
must be at pre−assigned logic levels. V
logic ‘1’. The V
condition must be established on pin A
HV
is interpreted as
HV
before the START and maintained just beyond the STOP.
Otherwise an RSWP request could be interpreted by the
NV34C02WF as a PSWP request.
The SWP Slave addresses follow the standard I
2
convention, i.e. to read the state of the SWP flag, the LSB of
the Slave address must be ‘1’, and to set or clear a flag, it
must be ‘0’. For Write commands a dummy byte address and
dummy data byte must be provided (Figure 14). In contrast
to a regular memory Read, a SWP Read does not return Data.
Instead the NV34C02WF will respond with NoACK if the
DATA n+1
0
C
S
A
C
K
T
A
R
T
S
A
C
K
SLAVE
ADDRESS
DATA n+2
A
DATA n
C
K
A
C
K
S
T
O
P
P
N
O
A
C
K
S
T
DATA n+xDATA n
O
P
P
N
O
A
C
K
flag is set and with ACK if the flag is not set. Therefore, the
Master can immediately follow up with a STOP, as there is
no meaningful data following the ACK interval (Figure 15).
Hardware Write Protection
With the WP pin held HIGH, the entire memory, as well
as the SWP flags are protected against Write operations, see
Memory Protection Map below. If the WP pin is left floating
or is grounded, it has no impact on the operation of the
NV34C02WF.
The state of the WP pin is strobed on the last falling edge
of SCL immediately preceding the first data byte (Figure 9).
If the WP pin is HIGH during the strobe interval, the
NV34C02WF will not acknowledge the data byte and the
Write request will be rejected.
FFH
Hardware Write Protectable
(by connecting WP pin to
)
V
7FH
00H
Figure 13. Memory Protection Map
CC
Software Write Protectable
(by setting the write
protect flags)
www.onsemi.com
8
NV34C02WF
Table 7. RSWP D.C. OPERATING CONDITIONS (Note 10)
Symbol
DV
I
V
HVD
HV
I
HV
A0 Overdrive (VHV − VCC)
HV
A0 High Voltage Detector Current 0.1 mA
A0 Very High Voltage 7 10 V
A0 Input Current @ V
10.To prevent damaging the NV34C02WF while applying VHV, it is strongly recommended to limit the power delivered to pin A0, by inserting
a series resistor (> 1.5 kW) between the supply and the input pin. The resistance is only limited by the combination of V
. While the resistor can be omitted if VHV is clamped well below 10 V, it nevertheless provides simple protection against EOS events.
I
HVD
As an example: V
= 1.7 V, VHV = 8 V, 1.5 kW < RS < 15 kW.
CC
Table 8. SWP COMMANDS
Parameter Test Conditions Min Max Units
1.7 V < VCC < 3.6 V
HV
4.8 V
1 mA
and maximum
HV
Action
Set
PSWP
Set
RSWP
Clear
RSWP
Control Pin Levels Flag State
(Note 11) (Note 12)
A
WP PSWP RSWP
X 1 XXNo
GND
V
CC
X0X 1Yes
X GND GND 1 X001XNo
X GND GND 0 1 001X No
GND GND GND 0 0 0 0 1 0 Yes X Yes X Yes Yes
V
GND GND 0 0 0 0 1 0 Yes X Yes X No No
CC
X GND GND 0 0 0 0 1 1 Yes
X GND 1 X011XNo
GND GND 0 X 0 1 1 0 Ye s X Ye s X Yes Ye s
GND 0 X 0110Ye s X Ye s X No No
V
CC
XGND 0 X 0111Ye s
A1A
2
A
A
2
A
A
2
A
A
2
A
A
2
V
V
V
V
CC
CC
CC
CC
0
A
1
0
A
1
A
1
A
1
V
V
V
V
V
V
V
V
V
0X 0Yes X Yes X Yes Yes
0
0X 0Yes X Yes X No No
0
0
HV
HV
HV
HV
HV
HV
HV
HV
HV
Slave Address
b7 to b
4
0110
11.Here A2, A1 and A0 are either at VCC or GND.
12.1 stands for ‘Set’, 0 stands for ‘Not Set’, X stands for ‘don’t care’.
b3b2b1b
A
2A1A0
A2A1A
A2A1A
A2A1A
0
0
0
ACK
Address
?
0
Byte
ACK
?
Data
Byte
ACK?Write
Cycle
www.onsemi.com
9
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
SLAVE
ADDRESS
NV34C02WF
BYTE
ADDRESS
X
XXXXXXX XXXXX XX X
DATA
S
T
O
P
P
A
C
K
X = Don’t Care
A
C
K
Figure 14. Software Write Protect (Write)
S
BUS ACTIVITY:
MASTER
SDA LINE
T
A
R
T
S
SLAVE
ADDRESS
S
T
O
P
P
N
A
or
O
C
K
A
C
K
Figure 15. Software Write Protect (Read)
N
A
or
O
C
K
A
C
K
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
www.onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
UDFN8 2x3, 0.5P
CASE 517DH
ISSUE A
DATE 10 DEC 2020
GENERIC
MARKING DIAGRAM*
1
XXXXX
AWLYWG
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98AON06579G
UDFN8 2X3, 0.5P
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
PAGE 1 OF 1
www.onsemi.com
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
. ON Semiconductor reserves the right to make changes without further notice to any products herein.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
◊
www.onsemi.com
1
Loading...