• Small Footprint (3.3 x 3.3 mm) for Compact Design
• Low R
to Minimize Conduction Losses
DS(on)
• Low Capacitance to Minimize Driver Losses
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T
Parameter
Drain−to−Source VoltageV
Gate−to−Source VoltageV
Continuous Drain
Current R
(Notes 1, 2, 3, 4)
Power Dissipation
R
q
JC
Continuous Drain
Current R
(Notes 1, 3, 4)
Power Dissipation
R
q
JA
Pulsed Drain Current
Operating Junction and Storage Temperature
Range
Source Current (Body Diode)I
Single Pulse Drain−to−Source Avalanche
Energy (I
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
q
JC
(Notes 1, 2, 3)
q
JA
(Notes 1, 3)
= 4.6 A)
L(pk)
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Junction−to−Case − Steady State (Note 3)
Junction−to−Ambient − Steady State (Note 3)
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
= 25°C unless otherwise noted)
J
SymbolValueUnit
TC = 25°C
Steady
State
Steady
State
TA = 25°C, t
TC = 100°C42
TC = 25°C
TC = 100°C16
TA = 25°C
TA = 100°C13
TA = 25°C
TA = 100°C1.6
= 10 ms
p
P
P
I
TJ, T
E
SymbolValueUnit
R
q
R
q
2
, 2 oz. Cu pad.
DSS
GS
I
D
D
I
D
D
DM
S
AS
T
L
JC
JA
stg
40V
±20V
74
50
19
3.1
321A
−55 to
+175
42A
104mJ
260°C
3.0
47.7
A
W
A
W
°C
°C/W
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V
(BR)DSS
40 V
G (4)
R
MAXID MAX
DS(on)
4.8 mW @ 10 V
7.6 mW @ 4.5 V
N−Channel
D (5 − 8)
S (1, 2, 3)
74 A
MARKING DIAGRAM
1
WDFN8
(m8FL)
CASE 511AB
60NL= Specific Device Code
A= Assembly Location
Y= Year
WW= Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
1
S
60NL
S
AYWWG
S
G
G
D
D
D
D
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Switching characteristics are independent of operating junction temperatures.
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2
NTTFS5C460NL
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
30
, DRAIN CURRENT (A)
D
I
20
10
0
VDS, DRAIN−TO−SOURCE VOLTAGE (V)VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region CharacteristicsFigure 2. Transfer Characteristics
14
12
10
8
4.0 V
VGS = 4.5 V to 10 V
1.2
0.81.62.02.4
TJ = 25°C
= 35 A
I
D
3.6 V
3.2 V
2.8 V
100
90
80
70
60
50
40
30
, DRAIN CURRENT (A)
D
I
20
10
2.80.40
0
8
7
6
5
4
TJ = 25°C
TJ = 125°C
VGS = 4.5 V
VGS = 10 V
21
TJ = −55°C
3
40
TJ = 25°C
5
6
4
, DRAIN−TO−SOURCE RESISTANCE (mW)
DS(on)
R
2
476
VGS, GATE−TO−SOURCE VOLTAGE (V)ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2.0
VGS = 10 V
, NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
DS(on)
R
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
= 35 A
I
D
25125
50175
TJ, JUNCTION TEMPERATURE (°C)VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
3
2
1
, DRAIN−TO−SOURCE RESISTANCE (mW)
DS(on)
R
0
1098532
10
1540
25
205
3035
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100K
10K
1K
100
, LEAKAGE (nA)
10
DSS
I
1
150100750−25−50
0.1
TJ = 175°C
TJ = 150°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
1020
40353025155
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NTTFS5C460NL
TYPICAL CHARACTERISTICS
10K
1K
100
10
C, CAPACITANCE (pF)
VGS = 0 V
T
f = 1 MHz
1
1000
100
t
t, TIME (ns)
10
t
10
9
C
ISS
C
OSS
8
7
6
5
= 25°C
J
10
Q
4
C
RSS
3
2
, GATE−TO−SOURCE VOLTAGE (V)
1
GS
0
200
30405101520
V
0
GS
Q
GD
VDS, DRAIN−TO−SOURCE VOLTAGE (V)QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance VariationFigure 8. Gate−to−Source vs. Total Charge
VGS = 10 V
= 20 V
V
DS
I
= 35 A
D
d(off)
d(on)
100
t
r
t
f
, SOURCE CURRENT (A)
S
I
VGS = 0 V
10
1
TJ = 125°C
VDS = 20 V
= 25°C
T
J
I
= 35 A
D
25
1
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
1000
TC = 25°C
Single Pulse
VGS ≤ 10 V
100
10
1
, DRAIN CURRENT (A)
D
I
0.1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
10
vs. Gate Resistance
R
Limit
DS(on)
Thermal Limit
Package Limit
Safe Operating Area
10 ms
0.5 ms
1 ms
10 ms
DC
100
1001
0.1
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
TJ = 25°C
0.60.40.31.1 1.2
TJ = −55°C
0.90.81.00.70.5
Figure 10. Diode Forward Voltage vs. Current
100
T
= 25°C
J(initial)
10
(A)
PEAK
I
T
1
J(initial)
= 100°C
0.1
10001010.1
0.00001
0.0001
0.001
0.01
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
100
(t) (°C/W)
JA
q
R
0.1
10
1
NTTFS5C460NL
50% Duty Cycle
20%
10%
5%
2%
1%
Single Pulse
0.01
0.010.00110.00010.10.00001100.000001
PULSE TIME (sec)
1001000
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
DeviceMarkingPackageShipping
NTTFS5C460NLTAG60NLWDFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1500 / Tape & Reel
†
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
0.05
E2
G
0.10 C
0.10 C
8X
C
A0.10B
C
4X
E3
1234
TOP VIEW
SIDE VIEW
b
L
14
8
BOTTOM VIEW
D1
78
D2
2X
C
0.20
D
A
B
2X
56
E
E1
0.20 C
c
A
DETAIL A
e/2
K
M
5
L1
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
4X
q
A1
6X
e
DETAIL A
C
SEATING
PLANE
0.75
DATE 23 APR 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
DIM MINNOM
MILLIMETERS
A0.700.75
A10.00−−−
b0.230.30
c0.150.20
D
D12.953.05
D21.982.11
E
E12.953.05
E21.471.60
E30.230.300.40
e0.65 BSC
G0.300.41
K0.650.80
L0.300.43
L10.060.13
M1.401.50
q0 −−−
3.30 BSC
3.30 BSC
_
MAX
0.80
0.05
0.40
0.25
3.15
2.24
3.15
1.73
0.51
0.95
0.56
0.20
1.60
12
_
INCHES
MINNOM
0.028 0.030
0.000−−−
0.009 0.012
0.006 0.008
0.130 BSC
0.116 0.120
0.078 0.083
0.130 BSC
0.116 0.120
0.058 0.063
0.009 0.0120.016
0.026 BSC
0.012 0.016
0.026 0.032
0.012 0.017
0.002 0.005
0.055 0.059
0 −−−
_
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.020
0.037
0.022
0.008
0.063
12
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
0.57
8X
0.650.42
PITCH
2.30
4X
0.66
3.60
_
GENERIC
MARKING DIAGRAM*
1
XXXXX
AYWWG
G
XXXXX = Specific Device Code
A= Assembly Location
Y= Year
WW= Work Week
G= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
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98AON30561E
WDFN8 3.3X3.3, 0.65P
*For additional information on our Pb−Free strategy and soldering
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