ON Semiconductor NTB90N02, NTP90N02 Technical data

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NTB90N02, NTP90N02

Power MOSFET
90 Amps, 24 Volts

N−Channel D2PAK and TO−220

Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.

Typical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

(BR)DSS

24 V

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R

TYP

DS(on)

5.0 m @ 10 V

7.5 m @ 4.5 V

ID MAXV

90 A

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage

− Continuous

Drain Current

− Continuous @ T

− Single Pulse (t

Total Power Dissipation @ TA = 25°C

Derate above 25°C

Operating and Storage Temperature TJ, T

Single Pulse Drain−to−Source Avalanche

Energy − Starting T
(V

= 28 Vdc, VGS = 10 Vdc, L = 5.0 mH,

DD

I

= 17 A, RG = 25 )

L(pk)

Thermal Resistance

Junction−to−Case
Junction−to−Ambient (Note 1)

Maximum Lead Temperature for Soldering Pur­poses, 1/8″ from case for 10 seconds

1. When surface mounted to an FR4 board using 1″ pad size,

(Cu Area 1.127 in

2. When surface mounted to an FR4 board using minimum recommended pad

size, (Cu Area 0.412 in

*Chip current capability limited by package.

= 25°C unless otherwise noted)

J

Rating

= 25°C

A

= 10 s)

p

= 25°C

J

2

).

2

).

Symbol Value Unit

D

stg

JC
JA

L

24 Vdc

20

0.66WW/°C

+150

1.55

Vdc

90*

200

85

−55

733 mJ

70

260 °C

°C

to

°C/W

A
A

R
R

V

I

E

DSS

GS

I

D

DM

P

AS




T

1

Gate

2

3

4

Drain

NTx90N02
LLYWW

1

Drain

4

1

TO−220AB

CASE 221A

Style 5

MARKING DIAGRAMS

& PIN ASSIGNMENTS

NTx90N02
LLYWW

3
Source

2

NTx90N02 = Device Code
x = P or B
LL = Location Code
Y = Year
WW = Work Week

1

Gate

2

3

2

D

PAK

CASE 418B

Style 2

4

Drain

2

Drain

4

3
Source

N−Channel

D

G

S

 Semiconductor Components Industries, LLC, 2003

October, 2003 − Rev. 1

ORDERING INFORMATION

Device Package Shipping

NTP90N02 TO−220AB 50 Units/Rail
NTB90N02 D2PAK 50 Units/Rail
NTB90N02T4 D2PAK 800/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

1 Publication Order Number:

NTB90N02/D

†

NTB90N02, NTP90N02

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 3)

(VGS = 0 Vdc, ID = 250 Adc)

Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current

= 24 Vdc, VGS = 0 Vdc)

(V

DS

(V

= 24 Vdc, VGS = 0 Vdc, TJ = 150°C)

DS

Gate−Body Leakage Current (VGS =  20 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage (Note 3)

(V

= VGS, ID = 250 Adc)

DS

Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)

= 10 Vdc, ID = 90 Adc)

(V

GS

= 4.5 Vdc, ID = 40 Adc)

(V

GS

(V

= 10 Vdc, ID = 20 Adc)

GS

= 4.5 Vdc, ID = 20 Adc)

(V

GS

Forward Transconductance (Note 3) (VDS = 15 Vdc, ID = 10 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

(VDS = 20 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Transfer Capacitance C

SWITCHING CHARACTERISTICS (Note 4)

(V

Turn−On Delay Time
Rise Time

= 20 Vdc, ID = 20 Adc,

DD

VGS = 4.5 Vdc, RG = 2.5 )

Turn−Off Delay Time t
Fall Time t
Gate Charge (VDS = 20 Vdc, ID = 20 Adc,

VGS = 4.5 Vdc) (Note 3)

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (IS = 2.3 Adc, VGS = 0 Vdc)

(IS = 40 Adc, VGS = 0 Vdc) (Note 3)

(I

= 2.3 Adc, VGS = 0 Vdc, TJ = 150°C)

S

Reverse Recovery Time (IS = 2.3 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/s) (Note 3)

Reverse Recovery Stored Charge Q

3. Pulse Test: Pulse Width ≤300 s, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

C

C

t

d(on)

d(off)

Q

Q
Q

V

t
t
t

FS

iss
oss
rss

t

SD

rr

a

b
RR

24

−

−

−

27
25

−

−

−

−

1.0
10

− − ±100 nAdc

1.0

−

−

−

−

−

1.9

−3.8

5.0

7.5

5.0

7.5

3.0

−

5.8

9.0

5.8

9.0

− 25 − mhos

− 2120 −

− 900 −

− 360 −

− 16 −

r

− 90 −

− 28 −

f

T
1
2

− 60 −

− 29 −

− 8.0 −

− 20 −

−

−

−

0.75

1.2

0.65

1.0

−

−

− 40 −

− 21 −

− 18 −

− 0.036 − C

Vdc

mV/°C

Adc

Vdc

mV/°C

m

pF

ns

nC

Vdc

ns

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2

NTB90N02, NTP90N02

100

9 V

90
80
70
60

50

8 V

4.6 V

4.8 V

5 V

6.5 V

40

30

20

, DRAIN CURRENT (AMPS)

D

I

10

0

0.5 43.5

0

V

, DRAIN−TO−SOURCE VOLTAGE (V)

DS

Figure 1. On−Region Characteristics

0.07

0.06

0.05

0.04

4.4 V

5.2 V
6 V

TJ = 25°C

21.51

2.5 3

4.2 V

4 V

3.8 V

3.6 V

3.4 V

3.2 V

VGS = 3.0 V

ID = 10 A
T

= 25°C

J

160
150
140

VDS ≥ 24 V

130
120
110
100

90
80
70

TJ = 25°C

60
50
40

TJ = 125°C

30
20

, DRAIN CURRENT (AMPS)

10

D

I

0

23 6

V

TJ = −55°C

45

, GATE−TO−SOURCE VOLTAGE (V)

GS

Figure 2. Transfer Characteristics

0.015
TJ = 25°C

0.01

VGS = 4.5 V

0.03

0.02

0.01

, DRAIN−TO−SOURCE RESISTANCE ()

0

DS(on)

R

0

26810

4

VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 3. On−Resistance versus

Gate−To−Source Voltage

0.015

0.0125

ID = 90 A
V

= 4.5 V

DS

0.001

0.0075

0.005

0.0025

0

−50 100750−25 125 150

, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

5025

TJ, JUNCTION TEMPERATURE (°C)

DS(on)

R

Figure 5. On−Resistance Variation with

Temperature

ID = 10 A
V

= 10 V

DS

VGS = 10 V

0.005

, DRAIN−TO−SOURCE RESISTANCE ()

0

55

DS(on)

R

60 65 70 75 80

85 90

ID, DRAIN CURRENT (A)

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

1000

VGS = 0 V

100

TJ = 125°C

TJ = 100°C

10

1

, LEAKAGE (nA)

DSS

I

0.1

0.01
41612820

TJ = 25°C

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 6. Drain−To−Source Leakage

Current versus Voltage

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3

NTB90N02, NTP90N02

5000

4000

VGS = 0 V

TJ = 25°C

3000

C

iss

2000

C

oss

C, CAPACITANCE (pF)

1000

C

rss

0

−8 −6 −4 −2

0 2 4 6 8 1012141618202224

VGSV

DS

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)

Figure 7. Capacitance Variation Figure 8. Gate−to−Source and

1000

VDD = 20 V
I

= 20 A

D

= 10 V

V

GS

t

d(off)

t

d(on)

t

r

t

f

10 100

RG, GATE RESISTANCE ()

100

t, TIME (ns)

10

1

1

10

Q

8

V

D

6

Q

1

4

T

V

GS

Q

2

2

, GATE−TO−SOURCE VOLTAGE (V)

GS

V

0

010

20 30 40 50

Q

, TOTAL GATE CHARGE (nC)

g

ID = 1.0 A
T

= 25°C

J

Drain−to−Source Voltage versus Total Charge

90

VGS = 0 V

80

T

= 25°C

J

70
60
50
40
30
20

, SOURCE CURRENT (AMPS)

S

I

10

0

0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00
VSD, SOURCE−TO−DRAIN VOLTAGE (V)

28
24
20
16
12
8
4

0

, DRAIN−TO−SOURCE VOLTAGE (V)

DS

−V

Figure 9. Resistive Switching Time Variation

versus Gate Resistance

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Figure 10. Diode Forward Voltage versus

Current

4

NTB90N02, NTP90N02

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that

t  QI

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following:

tr Q2 R210(VGG V
tf Q2 R2V

GSP

GSP

)

where:

VGG= the gate drive voltage, which varies from

zero to V

RG= the gate drive resistance and Q2 and V

GG

GSP

are read from the gate charge curve.

During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.

The equations are:

t

d(on)

 RGC

In [VGG(VGG V

iss

GSP

)]

The capacitance (C

) is read from the capacitance curve

iss

at a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

t

d(off)

 RGC

In (VGGV

iss

GSP

)

INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection

0.33

8.38

0.42

10.66

17.02

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0.63

interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.

0.08

2.032

1.016

0.12

3.05

5

0.24

6.096

0.04

inches

mm

NTB90N02, NTP90N02

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1 : 1 registration. This is not the case with the DPAK

2

and D

PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 11 shows a
typical stencil for the DPAK and D

2

PAK packages. The

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.

SOLDER PASTE
OPENINGS

STENCIL

Figure 11. Typical Stencil for DPAK and

2

D

PAK Packages

• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied
during cooling.

* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.

* * Due to shadowing and the inability to set the wave
height to incorporate other surface mount components, the

2

D

PAK is not recommended for wave soldering.

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6

NTB90N02, NTP90N02

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 12 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.

200°C

150°C

100°C

STEP 1

PREHEAT

ZONE 1
“RAMP”

DESIRED CURVE FOR HIGH

STEP 2

VENT

“SOAK”

MASS ASSEMBLIES

150°C

100°C

HEATING

ZONES 2 & 5

STEP 3

“RAMP”

The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177−189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

160°C

140°C

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

170°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

STEP 6

VENT

STEP 7

COOLING

205° TO 219°C

PEAK AT
SOLDER

JOINT

5°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

TIME (3 TO 7 MINUTES TOTAL) T

Figure 12. Typical Solder Heating Profile

MAX

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7

−T−

SEATING
PLANE

−B−

G

NTB90N02, NTP90N02

PACKAGE DIMENSIONS

D2PAK

CASE 418B−04

ISSUE H

NOTES:

C

E

V

4

W

A

231

S

K

W

J

3 PL

D

0.13 (0.005) T

M

M

B

H

1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.

DIM MIN MAX MIN MAX

A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
F 0.310 0.350 7.87 8.89
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
L 0.052 0.072 1.32 1.83

M 0.280 0.320 7.11 8.13

N 0.197 REF 5.00 REF
P 0.079 REF 2.00 REF
R 0.039 REF 0.99 REF
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

TO−220

CASE 221A−09

ISSUE AA

SEATING

−T−

PLANE

B

4

Q

123

F

T

A

U

C

S

H

K

Z

L

V

R
J

G

D

N

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

DIM MIN MAX MIN MAX

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73

G 0.095 0.105 2.42 2.66

H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33

Q 0.100 0.120 2.54 3.04

R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 −−− 1.15 −−−
Z −−− 0.080 −−− 2.04

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

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8

NTB90N02, NTP90N02

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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NTB90N02/D

9