ON Semiconductor NTP85N03, NTB85N03 Technical data

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NTP85N03, NTB85N03

Power MOSFET
85 Amps, 28 Volts

N−Channel TO−220 and D2PAK

Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.

Typical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

MAXIMUM RATINGS (T

Drain−to−Source Voltage V
Gate−to−Source Voltage

− Continuous

Drain Current

− Continuous @ T

− Single Pulse (t

Total Power Dissipation @ TC = 25°C

Derate above 25°C

Operating and Storage Temperature Range TJ, T

Single Pulse Drain−to−Source Avalanche

Energy − Starting T
(V

= 28 Vdc, VGS = 10 Vdc, L = 5.0 mH,

DD

I

= 17 A, RG = 25 )

L(pk)

Thermal Resistance

Junction−to−Case
Junction−to−Ambient (Note 1)

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

1. When surface mounted to an FR4 board using 1″ pad size,

(Cu Area 1.127 in

*Chip current capability limited by package.

= 25°C unless otherwise noted)

J

Rating

= 25°C

C

= 10 s)

p

= 25°C

J

2

).

Symbol Value Unit

D

stg

JC
JA

L

28 Vdc

20

85*

190

80

0.66WW/°C

−55
to

+150

733 mJ

1.55
70

260 °C

R
R

V

I

E

DSS

GS

I

D

DM

P

AS





T

Vdc

Adc
Apk

°C

°C/W

1

Gate

2

R

DS(on)

3

4

Drain

NTx85N03
LLYWW

1

Drain

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85 AMPERES

28 VOLTS

= 6.1 m (Typ.)

N−Channel

D

G

4

S

1

TO−220AB

CASE 221A

Style 5

MARKING DIAGRAMS

& PIN ASSIGNMENTS

NTx85N03
LLYWW

3
Source

2

NTx85N03 = Device Code
x = P or B
LL = Location Code
Y = Year
WW = Work Week

1

Gate

2

3

D2PAK

CASE 418AA

Style 2

4

Drain

3

2

Drain

Source

4

 Semiconductor Components Industries, LLC, 2003

October, 2003 − Rev. 1

ORDERING INFORMATION

Device Package Shipping

NTP85N03 TO−220AB 50 Units/Rail
NTB85N03 D2PAK 50 Units/Rail
NTB85N03T4 D2PAK 800/Tape & Reel

1 Publication Order Number:

NTP85N03/D

NTP85N03, NTB85N03

)

f = 1.0 MHz)

(

(V

DD

= 15 Vdc, I

D

Adc

)

V

GS

Vdc) (Note 2)

)

dIS/dt = 100 A/s) (Note 2)

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 2)

(VGS = 0 Vdc, ID = 250 Adc)

Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current

= 28 Vdc, VGS = 0 Vdc)

(V

DS

(V

= 28 Vdc, VGS = 0 Vdc, TJ = 150°C)

DS

Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (Note 2)

Gate Threshold Voltage (Note 2)

(V

= VGS, ID = 250 Adc)

DS

Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 2)

= 10 Vdc, ID = 40 Adc)

(V

GS

= 4.5 Vdc, ID = 40 Adc)

(V

GS

(V

= 10 Vdc, ID = 10 Adc)

GS

Forward Transconductance (Note 2) (VDS = 15 Vdc, ID = 10 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

(VDS = 24 Vdc, VGS = 0 Vdc,

f = 1.0 MHz

Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 3)

Turn−On Delay Time
Rise Time
Turn−Off Delay Time

V

= 15 Vdc, I

= 15 Adc,

= 15

VGS = 10 Vdc, RG = 3.3 )

,

Fall Time t
Gate Charge

(VDS = 24 Vdc, ID = 40 Adc,

= 4.5

V

= 4.5 Vdc) (Note 2

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (IS = 2.3 Adc, VGS = 0 Vdc)

(IS = 40 Adc, VGS = 0 Vdc) (Note 2)

(I

= 2.3 Adc, VGS = 0 Vdc, TJ = 150°C)

S

Reverse Recovery Time

(IS = 2.3 Adc, VGS = 0 Vdc,

dI

/dt = 100 A/s) (Note 2

Reverse Recovery Stored Charge Q

2. Pulse Test: Pulse Width ≤300 s, Duty Cycle ≤ 2%.

3. Switching characteristics are independent of operating junction temperatures.

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

C
C
C

t

d(on)

t

d(off)

Q

Q
Q

V

t
t
t

FS

iss
oss
rss

t

SD

rr

a

b
RR

28

−

−

−

30.6
25

−

−

−

−

1.0
10

− − ±100 nAdc

1.0

−

−

−

−

1.9

−3.8

6.1

9.2

7.0

3.0

−

6.8

−

−

− 20 − mhos

− 2150 −

− 680 −

− 260 −

− 10 −

r

− 22 −

− 32 −

f

T
1
2

− 30 −

− 29 −

− 8.0 −

− 18 −

−

−

−

0.75

1.2

0.65

1.0

−

−

− 39 −

− 21 −

− 18 −

− 0.043 − C

Vdc

mV/°C

Adc

Vdc

mV/°C

m

pF

ns

nC

Vdc

ns

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2

NTP85N03, NTB85N03

50

VGS = 10 V

40

8 V

6 V

30

5 V

4.5 V

20

, DRAIN CURRENT (AMPS)

10

D

I

0

0321

4 V

V

, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

DS

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.07

0.06

0.05

0.04

2.8 V

3.8 V

3 V

80

TJ = 25°C

VDS ≥ 10 V

70
60

3.6 V

3.4 V

3.2 V

43

5

50
40

TJ = 25°C

30

TJ = 100°C

20

, DRAIN CURRENT (AMPS)

D

I

10

0

2564

TJ = −55°C

0.015

ID = 10 A
T

= 25°C

J

TJ = 25°C

0.01
VGS = 4.5 V

0.03

0.02

0.01

, DRAIN−TO−SOURCE RESISTANCE ()

0

DS(on)

0

R

42

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus

Gate−to−Source V oltage

0.01
ID = 40 A

V

= 10 V

DS

0.0075

0.005

0.0025

0

−50 50250−25 75 125100

, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

0.005

, DRAIN−TO−SOURCE RESISTANCE ()

6810

DS(on)

R

0

1000

100

, LEAKAGE (nA)

DSS

10

I

1

150

VGS = 10 V

5152010 30

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

VGS = 0 V

TJ = 125°C

TJ = 100°C

41281620

DS(on)

R

Figure 5. On−Resistance Variation with

Temperature

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Figure 6. Drain−to−Source Leakage Current

versus V oltage

3

NTP85N03, NTB85N03

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following:
tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GG

GSP

− V

)

GSP

)]

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

5000
4500
4000
3500
3000

2500
2000
1500

C, CAPACITANCE (pF)

1000

500

0

−15

−10

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE

Figure 7. Capacitance Variation

0

(VOLTS)

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4

10

VGS = 0
T

= 25°C

J

C

iss

C

oss

C

rss

155−5 20

25