ON Semiconductor NTP60N06, NTB60N06 Technical data

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NTP60N06, NTB60N06

Power MOSFET

60 V, 60 A, N−Channel

2

TO−220 and D

PAK

Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.

Features

• Pb−Free Packages are Available

T ypical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

MAXIMUM RATINGS (T

Drain−to−Source Voltage V
Drain−to−Gate Voltage (RGS = 10 M) V
Gate−to−Source Voltage

− Continuous

− Non−Repetitive (t

Drain Current

− Continuous @ T

− Continuous @ T

− Single Pulse (t

Total Power Dissipation @ TA = 25°C

Derate above 25°C

Total Power Dissipation @ T
Operating and Storage Temperature Range TJ, T

Single Pulse Drain−to−Source Avalanche

Energy − Starting T

= 75 Vdc, VGS = 10 Vdc, L = 0.3 mH

(V

DD

I

= 55 A, VDS = 60 Vdc)

L(pk)

Thermal Resistance

− Junction−to−Case

− Junction−to−Ambient (Note 1)

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.

1. When surface mounted to an FR4 board using minimum recommended pad

size, (Cu Area 0.412 in

= 25°C unless otherwise noted)

J

Rating Symbol Value Unit

stg

60 Vdc
60 Vdc

20
30

60

42.3
180

150

1.0

2.4

−55 to
+175

454 mJ

1.0

62.5
260 °C

Vdc

Adc

Apk

W

W/°C

W

°C

°C/W

10 ms)

p

= 25°C

A

= 100°C

A

10 s)

p

= 25°C

J

2

).

= 25°C (Note 1)

A

V
V

E

R
R

DSS
DGR

GS
GS

I
I

I

DM

P

AS





T

D
D

D

JC
JA

L

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60 VOLTS, 60 AMPERES

R

DS(on)

G

4

1

2

3

4

2

3

NTx60N06 = Device Code
x = P or B
A = Assembly Location
Y = Year
WW = Work Week

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.

= 14 m

N−Channel

D

TO−220

CASE 221A

STYLE 5

2

D

PAK

CASE 418B

STYLE 2

S

DIAGRAMS

1

Gate

Gate

MARKING

4

Drain

NTx60N06

AYWW

3
Source

2

Drain

4

Drain

NTx60N06

AYWW

2

1

Drain

3
Source

 Semiconductor Components Industries, LLC, 2004

October, 2004 − Rev. 3

1 Publication Order Number:

NTP60N06/D

NTP60N06, NTB60N06

)

f = 1.0 MHz)

(V

DD

30 Vdc, I

D

Adc

)

V

GS

Vdc) (Note 2)

)

dIS/dt = 100 A/s) (Note 2)

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 2)

= 0 Vdc, ID = 250 Adc)

(V

GS

Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current

(V

= 60 Vdc, VGS = 0 Vdc)

DS

= 60 Vdc, VGS = 0 Vdc, TJ = 150°C)

(V

DS

Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (Note 2)

Gate Threshold Voltage (Note 2)

(V

= VGS, ID = 250 Adc)

DS

Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 2)

= 10 Vdc, ID = 30 Adc)

(V

GS

Static Drain−to−Source On−Voltage (Note 2)

(V

= 10 Vdc, ID = 60 Adc)

GS

= 10 Vdc, ID = 30 Adc, TJ = 150°C)

(V

GS

Forward Transconductance (Note 2) (VDS = 8.0 Vdc, ID = 12 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz

Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 3)

Turn−On Delay Time
Rise Time
Turn−Off Delay Time

V

(V

= 30 Vdc, ID = 60 Adc,

DD

= 10 Vdc, RG = 9.1 ) (Note 2)

GS

60

,

Fall Time t
Gate Charge

(VDS = 48 Vdc, ID = 60 Adc,

= 10 Vdc) (Note 2

= 10

V

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage

(IS = 60 Adc, VGS = 0 Vdc) (Note 2)

= 45 Adc, VGS = 0 Vdc, TJ = 150°C)

(I

S

Reverse Recovery Time

(IS = 60 Adc, VGS = 0 Vdc,
dI

/dt = 100 A/s) (Note 2

Reverse Recovery Stored Charge Q

2. Pulse Test: Pulse Width ≤300 s, Duty Cycle ≤ 2%.

3. Switching characteristics are independent of operating junction temperatures.

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

60

−

−

−

72.3

69.8

−

−

−

−

1.0
10

− − ±100 nAdc

2.0

−

2.85

8.0

4.0

−

Vdc

mV/°C

Adc

Vdc

mV/°C

m

− 11.5 14

V

DS(on)

C
C
C

t

d(on)

t

d(off)

V

FS

iss
oss
rss

−

−

− 35 − mhos

− 2300 3220 pF

− 660 925

− 144 300

0.715

1.43

1.01

−

− 25.5 50 ns

t

r

− 180.7 360

− 94.5 200

f

Q

T

Q

1

Q

2

SD

t

rr

t

a

t

b
RR

− 142.5 300

− 62 81 nC

− 10.8 −

− 29.4 −

−

−

0.99

0.87

1.05

−

− 64.9 −

− 44.1 −

− 20.8 −

− 0.146 − C

Vdc

Vdc

ns

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2

NTP60N06, NTB60N06

120

VGS = 10 V

9 V

100

8 V

80

60

40

, DRAIN CURRENT (AMPS)

20

D

I

0

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

0.026

0.022

0.018

VDS = 10 V

7 V

TJ = 100°C

6 V

5.5 V

5 V

4.5 V

4

120

VDS ≥ 10 V

100

80

60

40

, DRAIN CURRENT (AMPS)

20

D

I

53210

0.026

0.022

0.018

TJ = 100°C

0

VGS = 15 V

TJ = 25°C

TJ = −55°C

7

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

TJ = 100°C

86543

0.014

0.01

, DRAIN−TO−SOURCE RESISTANCE ()

0.006

DS(on)

R

TJ = 25°C

TJ = −55°C

40200

ID, DRAIN CURRENT (AMPS)

80 100

Figure 3. On−Resistance versus Gate−to−Source

Voltage

2.2
ID = 30 A

2

V

= 10 V

GS

1.8

1.6

1.4

1.2

1

0.8

0.6

DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

DS(on),

R

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

150

12060

1751251007550250−25−50

0.014
TJ = 25°C

0.01

40200

TJ = −55°C

80 100

, DRAIN−TO−SOURCE RESISTANCE ()

0.006

DS(on)

R

0

ID, DRAIN CURRENT (AMPS)

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

10,000

1000

, LEAKAGE (nA)

DSS

I

100

10

VGS = 0 V

TJ = 150°C

TJ = 125°C

TJ = 100°C

100

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

20 60

30 40 50

Figure 6. Drain−to−Source Leakage Current

versus V oltage

12060

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3

NTP60N06, NTB60N06

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following:
tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GG

GSP

− V

)

GSP

)]

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

6400
5600
4800

4000
3200
2400
1600

C, CAPACITANCE (pF)

C

iss

C

rss

800

0

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

510

V

Figure 7. Capacitance Variation

VGS = 0 VVDS = 0 V

C

rss

0 5 10 15 2520

V

GS

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DS

4

TJ = 25°C

C

iss

C

oss

NTP60N06, NTB60N06

12

Q

10

, GATE−TO−SOURCE VOLTAGE (VOLTS)

GS

V

8

Q

1

6

4

2

0

10 5030 60

0

20 7040
, TOTAL GATE CHARGE (nC)

Q

G

T

V

GS

Q

2

ID = 60 A
T

Figure 8. Gate−to−Source and Drain−to−Source

Voltage versus Total Charge

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

60

VGS = 0 V

50

T

= 25°C

J

40

30

= 25°C

J

TJ = 150°C

1000

VDS = 30 V
I

= 60 A

D

V

= 10 V

GS

t

r

t

100

t, TIME (ns)

10

1 10 100

f

t

d(off)

t

d(on)

RG, GATE RESISTANCE ()

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

20

10

, SOURCE CURRENT (AMPS)

S

I

0

0.48 0.56 0.64 0.72 0.8 0.88

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T

) of 25°C.

C

Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”

Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I

) nor rated voltage (V

DM

) is exceeded and the

DSS

transition time (tr,tf) do not exceed 10 s. In addition the total
power averaged over a complete switching cycle must not
exceed (T

J(MAX)

− TC)/(R

).

JC



A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For

TJ = 25°C

0.960.4

reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.

Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I

), the energy rating is specified at rated

DM

continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum e ner gy a t
currents below rated continuous I

can safely be assumed to

D

equal the values indicated.

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5

NTP60N06, NTB60N06

SAFE OPERATING AREA

1000

VGS = 20 V
SINGLE PULSE

= 25°C

T

C

100

10

, DRAIN CURRENT (AMPS)

D

I

1

0.1 1
V

DS

R
THERMAL LIMIT
PACKAGE LIMIT

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1.0
D = 0.5

0.2

0.1

0.1

0.05

0.02

(NORMALIZED)

SINGLE PULSE

0.01

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

0.01

100 s

DS(on)

LIMIT

500

10 s

400

300

200

1 ms

10 ms

dc

10 175

100

100

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN−TO−SOURCE

0

AS

25 50 75 100 125

E

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

P

(pk)

R



(t) = r(t) R

JC



JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN

t

1

t

2

DUTY CYCLE, D = t1/t

READ TIME AT t
T

− TC = P

J(pk)

2

(pk)

1

R

(t)



JC

1.0 100.10.010.0010.00010.00001

t, TIME (s)

Figure 13. Thermal Response

ID = 55 A

150

di/dt

I

S

t

rr

t

t

a

b

TIME

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

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NTP60N06, NTB60N06

ORDERING INFORMATION

Device Package Shipping

NTP60N06 TO−220 50 Units/Rail
NTP60N06G TO−220

(Pb−Free)
NTB60N06 D2PAK 50 Units/Rail
NTB60N06G D2PAK

(Pb−Free)
NTB60N06T4 D2PAK 800 Tape & Reel
NTB60N06T4G D2PAK

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

50 Units/Rail

50 Units/Rail

800 Tape & Reel

†

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7

NTP60N06, NTB60N06

PACKAGE DIMENSIONS

TO−220

CASE 221A−09

ISSUE AA

SEATING

−T−

PLANE

B

4

Q

123

F

T

A

U

C

S

H

K

Z

L

V

R
J

G

D

N

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

DIM MIN MAX MIN MAX

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88

F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93

J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27

L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39

T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 −−− 1.15 −−−

Z −−− 0.080 −−− 2.04

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

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8

NTP60N06, NTB60N06

PACKAGE DIMENSIONS

D2PAK

CASE 418B−04

ISSUE J

−T−

SEATING
PLANE

−B−

G

C

E

V

4

W

A

231

S

K

W

J

D

3 PL

0.13 (0.005) T

M

M

B

H

NOTES:

1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.

DIM MIN MAX MIN MAX

A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
F 0.310 0.350 7.87 8.89
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
L 0.052 0.072 1.32 1.83
M 0.280 0.320 7.11 8.13
N 0.197 REF 5.00 REF
P 0.079 REF 2.00 REF
R 0.039 REF 0.99 REF
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

SOLDERING FOOTPRINT*

8.38

0.33

10.66

0.42

1.016

0.04

5.08

0.20

3.05

0.12

17.02

0.67

SCALE 3:1



inches

mm

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.



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NTP60N06, NTB60N06

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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