ON Semiconductor NTP18N06L, NTB18N06L Technical data

查询NTB18N06L供应商

NTP18N06L, NTB18N06L

Power MOSFET
15 Amps, 60 Volts,
Logic Level

N−Channel TO−220 and D2PAK

Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.

Typical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

MAXIMUM RATINGS (T

Drain−to−Source Voltage V
Drain−to−Gate Voltage (RGS = 10 m) V
Gate−to−Source Voltage

− Continuous

− Non−Repetitive (t

Drain Current

− Continuous @ T

− Continuous @ T

− Single Pulse (t

Total Power Dissipation @ TC = 25°C

Derate above 25°C

Operating and Storage Temperature Range TJ, T

Single Pulse Drain−to−Source Avalanche

Energy − Starting T

(V

= 25 Vdc, VGS = 5.0 Vdc, VDS = 60 Vdc,

DD

= 11 A, L = 1.0 mH, RG = 25 )

I

L(pk)

Thermal Resistance

− Junction−to−Case

− Junction−to−Ambient

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

= 25°C unless otherwise noted)

J

Rating

 10 ms)

p

= 25°C

C

= 100°C

C

 10 s)

p

= 25°C

J

Symbol Value Unit

stg

60 Vdc
60 Vdc

10
20

15

8.0
45

48.4

0.32

−55 to
+175

61 mJ

3.1

72.5
260 °C

Vdc

Adc
Adc

A

pk

Watts

W/°C

°C

°C/W

V

E

R
R

DSS
DGR

GS

I
I

I

DM

P

AS





T

D
D

D

JC
JA

L

1

2

3

NTx18N06L
LLYWW

1

Gate

http://onsemi.com

15 AMPERES

60 VOLTS

R

DS(on)

G

4

TO−220AB

CASE 221A

STYLE 5

MARKING DIAGRAMS

& PIN ASSIGNMENTS

4

Drain

2

Drain

= 100 m

N−Channel

D

3
Source

NTx18N06L = Device Code
x = B or P
LL = Location Code
Y = Year
WW = Work Week

S

1

NTx18N06L
LLYWW

1

Gate

2

3

D2PAK

CASE 418AA

STYLE 2

4

Drain

2

Drain

3
Source

4

 Semiconductor Components Industries, LLC, 2003

October, 2003 − Rev. 3

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.

1 Publication Order Number:

NTP18N06L/D

NTP18N06L, NTB18N06L

)

f = 1.0 MHz)

R

G

9.1 ) (Note 1)
)

V

GS

Vdc) (Note 1)

dIS/dt = 100 A/s) (Note 1)

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 1)

(V

= 0 Vdc, ID = 250 Adc)

GS

Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current

= 0 Vdc, VDS = 60 Vdc)

(V

GS

= 0 Vdc, VDS = 60 Vdc, TJ = 150°C)

(V

GS

Gate−Body Leakage Current (VGS = ±15 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (Note 1)

Gate Threshold Voltage (Note 1)

= V

(V

DS

ID = 250 Adc)

GS,

Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 1)

= 5.0 Vdc, ID = 7.5 Adc)

(V

GS

Static Drain−to−Source On−Voltage (Note 1)

(V

= 5.0 Vdc, ID = 15 Adc)

GS

= 5.0 Vdc, ID = 7.5 Adc, TJ = 150°C)

(V

GS

Forward Transconductance (Note 1) (VDS = 7.0 Vdc, ID = 6.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 2)

Turn−On Delay Time

(V

= 30 Vdc, ID = 15 Adc,

Rise Time
Turn−Off Delay Time

DD

VGS = 5.0 Vdc,

= 9.1 ) (Note 1)

R

G

Fall Time
Gate Charge

(VDS = 48 Vdc, ID = 15 Adc,

V

= 5.0 Vdc) (Note 1

= 5.0

SOURCE−DRAIN DIODE CHARACTERISTICS

Diode Forward On−Voltage

(IS = 15 Adc, VGS = 0 Vdc) (Note 1)

(I

= 15 Adc, VGS = 0 Vdc, TJ = 150°C)

S

Reverse Recovery Time

(IS = 15 Adc, VGS = 0 Vdc,

/dt = 100 A/s) (Note 1)

dI

S

Reverse Recovery Stored

Charge

1. Pulse Test: Pulse Width =300 s, Duty Cycle = 2%.

2. Switching characteristics are independent of operating junction temperature.

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

60

−

−

−

70

63.2

−

−

−

−

1.0
10

− − ±100 nAdc

1.0

−

1.6

4.2

2.0

−

Vdc

mV/°C

Adc

Vdc

mV/°C

m

− 85 100

V

DS(on)

C
C
C

t

d(on)

t

d(off)

V

Q

FS

iss
oss
rss

−

−

− 9.4 − mhos

− 310 440

− 106 150

− 37 70

1.46

1.2

1.8

−

− 11 20

t

r

− 121 210

− 11 40

t

f

Q

t

Q

1

Q

2

SD

t

rr

t

a

t

b
RR

− 42 80

− 7.3 20

− 1.9 −

− 4.3 −

−

−

0.96

0.83

1.2

−

− 35 −

− 23 −

− 12 −

− 0.043 − C

Vdc

pF

ns

nC

Vdc

ns

http://onsemi.com

2

NTP18N06L, NTB18N06L

32

24

16

8

, DRAIN CURRENT (AMPS)

D

I

0

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

8 V

V

GS

Figure 1. On−Region Characteristics

0.32
VGS = 5 V

0.24

TJ = 100°C

0.16

TJ = 25°C

0.08

TJ = −55°C

= 10 V

6 V

5 V

4.5 V

4 V

3.5 V
3 V

6420

8

32

VDS ≥ 10 V

24

16

8

, DRAIN CURRENT (AMPS)

D

I

0

TJ = 25°C

TJ = 100°C

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = −55°C

543261

7

Figure 2. Transfer Characteristics

0.32
VGS = 10 V

0.24

0.16

0.08

TJ = 100°C

TJ = 25°C

, DRAIN−TO−SOURCE RESISTANCE ()

0

DS(on)

R

ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus

2

ID = 7.5 A
V

= 5 V

GS

1.8

1.6

1.4

1.2

1

0.8

0.6

DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

TJ, JUNCTION TEMPERATURE (°C)

DS(on),

R

Figure 5. On−Resistance Variation with

1680

24

Gate−to−Source V oltage

Temperature

TJ = −55°C

1680

, DRAIN CURRENT (AMPS)

I

D

24

32

32

, DRAIN−TO−SOURCE RESISTANCE ()

DS(on)

R

0

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

10,000

1501251007550250−25−50

175

VGS = 0 V

1000

100

, LEAKAGE (nA)

DSS

I

10

1

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

TJ = 150°C

TJ = 100°C

100

20 60

4030 50

Figure 6. Drain−to−Source Leakage Current

versus V oltage

http://onsemi.com

3

NTP18N06L, NTB18N06L

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
rudimentary analysis of the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
times may be approximated by the following:

tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V

GSP

GSP

where
VGG = the gate drive voltage, which varies from zero to V
RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(V

iss

In (VGG/V

iss

) can be made from a

G(AV)

. Therefore, rise and fall

SGP

)

− V

GSP

)]

GG

GSP

)

GG

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

1200

1000

C

iss

800

C

600

rss

400

C, CAPACITANCE (pF)

200

0

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

55

10 0 10 15 20 25

VGS = 0 VVDS = 0 V

C

rss

V

Figure 7. Capacitance Variation

V

GS

DS

http://onsemi.com

4

TJ = 25°C

C

C

iss

oss