ON Semiconductor NTP18N06L, NTB18N06L Technical data

查询NTB18N06L供应商

NTP18N06L, NTB18N06L

Power MOSFET
15 Amps, 60 Volts,
Logic Level

N−Channel TO−220 and D2PAK

Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.

Typical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

MAXIMUM RATINGS (T

Drain−to−Source Voltage V
Drain−to−Gate Voltage (RGS = 10 m) V
Gate−to−Source Voltage

− Continuous

− Non−Repetitive (t

Drain Current

− Continuous @ T

− Continuous @ T

− Single Pulse (t

Total Power Dissipation @ TC = 25°C

Derate above 25°C

Operating and Storage Temperature Range TJ, T

Single Pulse Drain−to−Source Avalanche

Energy − Starting T

(V

= 25 Vdc, VGS = 5.0 Vdc, VDS = 60 Vdc,

DD

= 11 A, L = 1.0 mH, RG = 25 )

I

L(pk)

Thermal Resistance

− Junction−to−Case

− Junction−to−Ambient

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

= 25°C unless otherwise noted)

J

Rating

 10 ms)

p

= 25°C

C

= 100°C

C

 10 s)

p

= 25°C

J

Symbol Value Unit

stg

60 Vdc
60 Vdc

10
20

15

8.0
45

48.4

0.32

−55 to
+175

61 mJ

3.1

72.5
260 °C

Vdc

Adc
Adc

A

pk

Watts

W/°C

°C

°C/W

V

E

R
R

DSS
DGR

GS

I
I

I

DM

P

AS





T

D
D

D

JC
JA

L

1

2

3

NTx18N06L
LLYWW

1

Gate

http://onsemi.com

15 AMPERES

60 VOLTS

R

DS(on)

G

4

TO−220AB

CASE 221A

STYLE 5

MARKING DIAGRAMS

& PIN ASSIGNMENTS

4

Drain

2

Drain

= 100 m

N−Channel

D

3
Source

NTx18N06L = Device Code
x = B or P
LL = Location Code
Y = Year
WW = Work Week

S

1

NTx18N06L
LLYWW

1

Gate

2

3

D2PAK

CASE 418AA

STYLE 2

4

Drain

2

Drain

3
Source

4

 Semiconductor Components Industries, LLC, 2003

October, 2003 − Rev. 3

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.

1 Publication Order Number:

NTP18N06L/D

NTP18N06L, NTB18N06L

)

f = 1.0 MHz)

R

G

9.1 ) (Note 1)
)

V

GS

Vdc) (Note 1)

dIS/dt = 100 A/s) (Note 1)

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 1)

(V

= 0 Vdc, ID = 250 Adc)

GS

Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current

= 0 Vdc, VDS = 60 Vdc)

(V

GS

= 0 Vdc, VDS = 60 Vdc, TJ = 150°C)

(V

GS

Gate−Body Leakage Current (VGS = ±15 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (Note 1)

Gate Threshold Voltage (Note 1)

= V

(V

DS

ID = 250 Adc)

GS,

Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 1)

= 5.0 Vdc, ID = 7.5 Adc)

(V

GS

Static Drain−to−Source On−Voltage (Note 1)

(V

= 5.0 Vdc, ID = 15 Adc)

GS

= 5.0 Vdc, ID = 7.5 Adc, TJ = 150°C)

(V

GS

Forward Transconductance (Note 1) (VDS = 7.0 Vdc, ID = 6.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 2)

Turn−On Delay Time

(V

= 30 Vdc, ID = 15 Adc,

Rise Time
Turn−Off Delay Time

DD

VGS = 5.0 Vdc,

= 9.1 ) (Note 1)

R

G

Fall Time
Gate Charge

(VDS = 48 Vdc, ID = 15 Adc,

V

= 5.0 Vdc) (Note 1

= 5.0

SOURCE−DRAIN DIODE CHARACTERISTICS

Diode Forward On−Voltage

(IS = 15 Adc, VGS = 0 Vdc) (Note 1)

(I

= 15 Adc, VGS = 0 Vdc, TJ = 150°C)

S

Reverse Recovery Time

(IS = 15 Adc, VGS = 0 Vdc,

/dt = 100 A/s) (Note 1)

dI

S

Reverse Recovery Stored

Charge

1. Pulse Test: Pulse Width =300 s, Duty Cycle = 2%.

2. Switching characteristics are independent of operating junction temperature.

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

60

−

−

−

70

63.2

−

−

−

−

1.0
10

− − ±100 nAdc

1.0

−

1.6

4.2

2.0

−

Vdc

mV/°C

Adc

Vdc

mV/°C

m

− 85 100

V

DS(on)

C
C
C

t

d(on)

t

d(off)

V

Q

FS

iss
oss
rss

−

−

− 9.4 − mhos

− 310 440

− 106 150

− 37 70

1.46

1.2

1.8

−

− 11 20

t

r

− 121 210

− 11 40

t

f

Q

t

Q

1

Q

2

SD

t

rr

t

a

t

b
RR

− 42 80

− 7.3 20

− 1.9 −

− 4.3 −

−

−

0.96

0.83

1.2

−

− 35 −

− 23 −

− 12 −

− 0.043 − C

Vdc

pF

ns

nC

Vdc

ns

http://onsemi.com

2

NTP18N06L, NTB18N06L

32

24

16

8

, DRAIN CURRENT (AMPS)

D

I

0

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

8 V

V

GS

Figure 1. On−Region Characteristics

0.32
VGS = 5 V

0.24

TJ = 100°C

0.16

TJ = 25°C

0.08

TJ = −55°C

= 10 V

6 V

5 V

4.5 V

4 V

3.5 V
3 V

6420

8

32

VDS ≥ 10 V

24

16

8

, DRAIN CURRENT (AMPS)

D

I

0

TJ = 25°C

TJ = 100°C

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = −55°C

543261

7

Figure 2. Transfer Characteristics

0.32
VGS = 10 V

0.24

0.16

0.08

TJ = 100°C

TJ = 25°C

, DRAIN−TO−SOURCE RESISTANCE ()

0

DS(on)

R

ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus

2

ID = 7.5 A
V

= 5 V

GS

1.8

1.6

1.4

1.2

1

0.8

0.6

DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

TJ, JUNCTION TEMPERATURE (°C)

DS(on),

R

Figure 5. On−Resistance Variation with

1680

24

Gate−to−Source V oltage

Temperature

TJ = −55°C

1680

, DRAIN CURRENT (AMPS)

I

D

24

32

32

, DRAIN−TO−SOURCE RESISTANCE ()

DS(on)

R

0

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

10,000

1501251007550250−25−50

175

VGS = 0 V

1000

100

, LEAKAGE (nA)

DSS

I

10

1

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

TJ = 150°C

TJ = 100°C

100

20 60

4030 50

Figure 6. Drain−to−Source Leakage Current

versus V oltage

http://onsemi.com

3

NTP18N06L, NTB18N06L

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
rudimentary analysis of the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
times may be approximated by the following:

tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V

GSP

GSP

where
VGG = the gate drive voltage, which varies from zero to V
RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(V

iss

In (VGG/V

iss

) can be made from a

G(AV)

. Therefore, rise and fall

SGP

)

− V

GSP

)]

GG

GSP

)

GG

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

1200

1000

C

iss

800

C

600

rss

400

C, CAPACITANCE (pF)

200

0

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

55

10 0 10 15 20 25

VGS = 0 VVDS = 0 V

C

rss

V

Figure 7. Capacitance Variation

V

GS

DS

http://onsemi.com

4

TJ = 25°C

C

C

iss

oss

NTP18N06L, NTB18N06L

6

Q

T

Q

2

, GATE−TO−SOURCE VOLTAGE (VOLTS)

GS

V

Q

1

4

V

GS

2

0

0

2648

, TOTAL GATE CHARGE (nC)

Q

G

Figure 8. Gate−T o−Source and Drain−To−Source

Voltage versus Total Charge

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

16

VGS = 0 V

12

ID = 15 A
T

= 25°C

J

1000

VDS = 30 V
I

= 15 A

D

= 5 V

V

GS

100

t, TIME (ns)

10

1

1 10 100

t

r

t

f

t

d(off)

t

d(on)

RG, GATE RESISTANCE ()

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

8

4

, SOURCE CURRENT (AMPS)

S

I

0

0.3
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

TJ = 150°C

0.4 0.5 1

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”

Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I

) nor rated voltage (V

DM

transition time (t

r,tf

) do not exceed 10 s. In addition the total

) is exceeded and the

DSS

power averaged over a complete switching cycle must not
exceed (T

J(MAX)

− TC)/(R

).

JC



A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For

TJ = 25°C

0.6 0.7 0.8 0.9

reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.

Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I

), the energy rating is specified at rated

DM

continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum e ner gy a t
currents below rated continuous I

can safely be assumed to

D

equal the values indicated.

http://onsemi.com

5

NTP18N06L, NTB18N06L

SAFE OPERATING AREA

100

VGS = 15 V
SINGLE PULSE

= 25°C

T

C

10

10 s

100 s

1 ms

1

, DRAIN CURRENT (AMPS)

D

I

R

DS(on)

THERMAL LIMIT

10 ms

LIMIT

PACKAGE LIMIT

0.1

0.1 1 100
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V

DS

10 175

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1.0
D = 0.5

0.2

0.1

0.1

0.05

dc

70

60

50

40

30

20

10

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN−TO−SOURCE

0

AS

25 50 75 100 125

E

T

, STARTING JUNCTION TEMPERATURE (°C)

J

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

ID = 11 A

150

0.01

r(t), TRANSIENT THERMAL RESISTANCE

0.02

0.01
SINGLE PULSE

0.00001
t, TIME (s)

Figure 13. Thermal Response

di/dt

I

S

t

rr

t

t

a

b

TIME

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

1100.10.010.0010.00010.000001

http://onsemi.com

6

NTP18N06L, NTB18N06L

INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection

0.33

8.38

0.42

10.66

17.02

0.63

interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.

0.24

6.096

0.04

1.016

0.12

3.05

inches

mm

http://onsemi.com

7

NTP18N06L, NTB18N06L

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1 : 1 registration. This is not the case with the DPAK

2

and D

PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 15 shows a
typical stencil for the DPAK and D

2

PAK packages. The

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.

SOLDER PASTE
OPENINGS

STENCIL

Figure 15. Typical Stencil for DPAK and

2

D

PAK Packages

• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied
during cooling.

* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.

* * Due to shadowing and the inability to set the wave
height to incorporate other surface mount components, the

2

D

PAK is not recommended for wave soldering.

http://onsemi.com

8

NTP18N06L, NTB18N06L

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.

200°C

150°C

100°C

STEP 1

PREHEAT

ZONE 1
“RAMP”

DESIRED CURVE FOR HIGH

STEP 2

VENT

“SOAK”

MASS ASSEMBLIES

150°C

100°C

HEATING

ZONES 2 & 5

STEP 3

“RAMP”

The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177−189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

160°C

140°C

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

170°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

STEP 6

VENT

STEP 7

COOLING

205° TO 219°C

PEAK AT
SOLDER

JOINT

5°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

TIME (3 TO 7 MINUTES TOTAL) T

Figure 16. Typical Solder Heating Profile

MAX

http://onsemi.com

9

NTP18N06L, NTB18N06L

Ordering Information

Device Package Shipping

NTP18N06L TO−220AB 50 Units/Rail
NTB18N06L D2PAK 50 Units/Rail
NTB18N06LT4 D2PAK 800/Tape & Reel
NTB18N06LT4G Pb FREE D2PAK 800/Tape & Reel

http://onsemi.com

10

NTP18N06L, NTB18N06L

PACKAGE DIMENSIONS

TO−220

CASE 221A−09

ISSUE AA

SEATING

−T−

PLANE

B

4

Q

123

F

T

A

U

H

K

Z

L

V

G

D

N

C

S

R
J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

DIM MIN MAX MIN MAX

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88

F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93

J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27

L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39

T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 −−− 1.15 −−−

Z −−− 0.080 −−− 2.04

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

http://onsemi.com

11

−T−

SEATING
PLANE

VARIABLE
CONFIGURATION
ZONE

−B−

G

NTP18N06L, NTB18N06L

PACKAGE DIMENSIONS

D2PAK

CASE 418AA−01

ISSUE O

C

E

V

4

W

A

231

S

K

W

J

3 PL

D

M

0.13 (0.005) T

M

B

U

NOTES:

1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.036 0.51 0.92
E 0.045 0.055 1.14 1.40
F 0.310 −−− 7.87 −−−
G 0.100 BSC 2.54 BSC
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
M 0.280 −−− 7.11 −−−
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

M

F

VIEW W−W VIEW W−W VIEW W−W

123

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

M

F

M

F

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [e-mail]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

http://onsemi.com

12

ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your
local Sales Representative.

NTP18N06L/D