ON Semiconductor NTMS5P02, NVMS5P02 User Manual

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Page 1

NTMS5P02, NVMS5P02

MOSFET – Power, Single,

P-Channel, Enhancement Mode, SOIC-8

-5.4 A, -20 V

Features

• High Density Power MOSFET with Ultra Low R

Providing Higher Efficiency

• Miniature SOIC−8 Surface Mount Package − Saves Board Space

• Diode Exhibits High Speed with Soft Recovery

• I

Specified at Elevated Temperature

DSS

• Drain−to−Source Avalanche Energy Specified

• Mounting Information for the SOIC−8 Package is Provided

• These Devices are Pb−Free and are RoHS Compliant

• NVMS Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable

Applications

• Power Management in Portable and Battery−Powered Products, i.e.:

Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones

DS(on)

DSS

−20 V

SOIC−8 CASE 751 STYLE 13

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DS(ON)

26 mW @ −4.5 V

Single P−Channel

MARKING DIAGRAM &

PIN ASSIGNMENT

TYP ID MAX

−5.4 A

DD DD

E5P02x

AYWW G

NC S S G

June, 2019 − Rev. 3

E5P02 = Specific Device Code x = Blank or S A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

Device Package

NTMS5P02R2G SOIC−8

(Pb−Free)

NVMS5P02R2G SOIC−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D

1 Publication Order Number:

Shipping

2500 / Tape & Reel

NTMS5P02R2/D

†

Page 2

NTMS5P02, NVMS5P02

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Drain−to−Gate Voltage (RGS = 1.0 mW)

Gate−to−Source Voltage − Continuous V

= 25°C unless otherwise noted)

Rating

Symbol Value Unit

−20 V

±10 V

DSS

DGR

Thermal Resistance −

Junction−to−Ambient (Note 1) Total Power Dissipation @ T Continuous Drain Current @ 25°C

= 25°C

Continuous Drain Current @ 70°C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4)

2.5

−7.05

−5.62

1.2

−4.85

−28

°C/W

A A

Thermal Resistance −

Junction−to−Ambient (Note 2) Total Power Dissipation @ T Continuous Drain Current @ 25°C

= 25°C

Continuous Drain Current @ 70°C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4)

1.47

−5.40

−4.30

0.7

−3.72

−20

°C/W

A A

Thermal Resistance −

Junction−to−Ambient (Note 3) Total Power Dissipation @ T Continuous Drain Current @ 25°C

= 25°C

Continuous Drain Current @ 70°C Maximum Operating Power Dissipation

P Maximum Operating Drain Current Pulsed Drain Current (Note 4)

Operating and Storage Temperature Range TJ, T

Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C

= −20 Vdc, VGS = −5.0 Vdc, Peak IL = −8.5 Apk, L = 10 mH, RG = 25 W)

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

JA D

stg

159

0.79

°C/W

−3.95

−3.15

0.38

−2.75

−12

−55 to +150 °C

360 mJ

260 °C

A A

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t ≤ 10 seconds.

2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t = steady state.

3. Minimum FR−4 or G−10 PCB, t = Steady State.

4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

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Page 3

NTMS5P02, NVMS5P02

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted) (Note 5)

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

= 0 Vdc, ID = −250 mAdc)

Temperature Coefficient (Positive)

Zero Gate Voltage Drain Current

= −16 Vdc, VGS = 0 Vdc, TJ = 25°C)

= −16 Vdc, VGS = 0 Vdc, TJ = 125°C)

= −20 Vdc, VGS = 0 Vdc, TJ = 25°C)

Gate−Body Leakage Current

= −10 Vdc, VDS = 0 Vdc)

Gate−Body Leakage Current

= +10 Vdc, VDS = 0 Vdc)

ON CHARACTERISTICS

Gate Threshold Voltage

= VGS, ID = −250 mAdc)

Temperature Coefficient (Negative)

Static Drain−to−Source On−State Resistance

= −4.5 Vdc, ID = −5.4 Adc)

= −2.5 Vdc, ID = −2.7 Adc)

Forward Transconductance (VDS = −9.0 Vdc, ID = −5.4 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance

Output Capacitance C

(VDS = −16 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Reverse Transfer Capacitance C

SWITCHING CHARACTERISTICS (Notes 6 & 7)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

(VDD = −16 Vdc, ID = −1.0 Adc,

= −4.5 Vdc,

= 6.0 W)

Fall Time t

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

(VDD = −16 Vdc, ID = −5.4 Adc,

= −4.5 Vdc,

= 6.0 W)

Fall Time t

Total Gate Charge

Gate−Source Charge Q

Gate−Drain Charge Q

(VDS = −16 Vdc,

= −4.5 Vdc,

= −5.4 Adc)

BODY−DRAIN DIODE RATINGS (Note 6)

Diode Forward On−Voltage (IS = −5.4 Adc, VGS = 0 V)

= −5.4 Adc, VGS = 0 Vdc, TJ = 125°C)

Reverse Recovery Time

(IS = −5.4 Adc, VGS = 0 Vdc,

/dt = 100 A/ms)

Reverse Recovery Stored Charge Q

5. Handling precautions to protect against electrostatic discharge is mandatory.

6. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%.

7. Switching characteristics are independent of operating junction temperature.

Symbol Min Ty p Max Unit

(BR)DSS

DSS

GSS

−20

−

−15

−

−0.2

−

−1.0

−10

−

Vdc

mV/°C

mAdc

nAdc

− − −100

GSS

nAdc

− − 100

GS(th)

DS(on)

d(on)

d(off)

d(on)

d(off)

iss

oss

rss

tot

−0.65

−

−0.9

2.9

0.026

0.037

−1.25

−

0.033

0.048

− 15 − Mhos

− 1375 1900 pF

− 510 900

− 200 380

− 18 35

− 25 50

− 70 125

− 55 100

− 22 −

− 70 −

− 65 −

− 90 −

− 20 35

− 4.0 −

− 7.0 −

−

−0.95

−0.72

−1.25

−

− 40 75

− 20 −

− 0.03 −

Vdc

mV/°C

Vdc

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Page 4

NTMS5P02, NVMS5P02

−8 V

, DRAIN CURRENT (AMPS)

−I

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

0.08

0.06

0.04

−2.3 V

−4.5 V

−3.7 V

−3.1 V

−2.7 V

−2.5 V

−2.1 V

−1.9 V

−1.7 V

= −1.3 V

ID = −5.4 A

= 25°C

TJ = 25°C

VDS ≥ −10 V

, DRAIN CURRENT (AMPS)

−I

21.751.51.2510.750.50.250

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

25°C

100°C

TJ = −55°C

2.5

321.51

Figure 2. Transfer Characteristics

0.05

TJ = 25°C

0.04

0.03

VGS = −2.5 V

VGS = −2.7 V

0.02

, DRAIN−TO−SOURCE RESISTANCE (W)

DS(on)

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 3. On−Resistance versus

1.6

ID = −5.4 A

1.4

1.2

0.8

0.6

, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

= −4.5 V

TJ, JUNCTION TEMPERATURE (°C)

Gate−To−Source Voltage

VGS = −4.5 V

0.02

, DRAIN−TO−SOURCE RESISTANCE (W)

0.01

8 10

106420

DS(on)

−ID, DRAIN CURRENT (AMPS)

642

Figure 4. On-Resistance versus Drain Current

and Gate Voltage

10,000

VGS = 0 V

TJ = 150°C

1000

TJ = 125°C

121062

1501251007550250−25−50

, LEAKAGE (nA)

DSS

−I

100

48 201814 16

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

128

DS(on)

Figure 5. On−Resistance Variation with

Temperature

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Figure 6. Drain−To−Source Leakage Current

versus Voltage

Page 5

NTMS5P02, NVMS5P02

4000

iss

3000

VGS = 0 VVDS = 0 V

rss

2000

C, CAPACITANCE (pF)

1000

−V

rss

510

−V

10 0 155

GATE−TO−SOURCE OR

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

1000

VDD = −16 V

= −5.4 A

= −4.5 V

100

t, TIME (ns)

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time Variation

versus Gate Resistance

TJ = 25°C

iss

oss

d(off)

d(on)

−V

ID = −5.4 A

= 25°C

, GATE−TO−SOURCE VOLTAGE (VOLTS)

−V

, TOTAL GATE CHARGE (nC)

12 16 20 24

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

VGS = 0 V

= 25°C

, SOURCE CURRENT (AMPS)

−I

0.2 0.4 0.5 0.6

−V

, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

0.7 0.8 1

Figure 10. Diode Forward Voltage versus Current

−V

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

0.90.3

100

, DRAIN CURRENT (AMPS)

0.1

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

VGS = 20 V SINGLE PULSE TC = 25°C

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1 ms

10 ms

100

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di/dt

TIME

0.25 I

Figure 12. Diode Reverse Recovery Waveform

Page 6

0.1

0.01

THERMAL RESISTANCE

Rthja(t), EFFECTIVE TRANSIENT

0.001

1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01

D = 0.5

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

NTMS5P02, NVMS5P02

TYPICAL ELECTRICAL CHARACTERISTICS

Normalized to qja at 10s.

0.0163 W 0.0652 W 0.1988 W 0.6411 W 0.9502 W

Chip

t, TIME (s)

Figure 13. Thermal Response

72.416 F1.9437 F0.5541 F0.1668 F0.0307 F

Ambient

1.0E+02 1.0E+03

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Page 7

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 1:1

−Y−

−Z−

−X−

0.25 (0.010) Z

SOLDERING FOOTPRINT*

7.0

0.275

0.25 (0.010)

SXS

SEATING PLANE

0.10 (0.004)

1.52

0.060

4.0

0.155

CASE 751−07

SOIC−8 NB

ISSUE AK

X 45

MARKING DIAGRAM*

XXXXX ALYWX

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

XXXXX ALYWX

(Pb−Free)

DATE 16 FEB 2011

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050

M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

INCHES

GENERIC

XXXXXX

AYWW

Discrete

XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

XXXXXX

AYWW

Discrete

(Pb−Free)

0.6

0.024

1.270

0.050

SCALE 6:1

inches

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

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Page 8

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

SOIC−8 NB

CASE 751−07

ISSUE AK

STYLE 11:

STYLE 15:

STYLE 3:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

STYLE 7:

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

STYLE 19:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

STYLE 23:

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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Page 9

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

. ON Semiconductor reserves the right to make changes without further notice to any products herein.

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ON Semiconductor NTMS5P02, NVMS5P02 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual