ON Semiconductor NTMS4937N User Manual

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NTMS4937N

MOSFET – Power,

N-Channel, SO-8

30 V, 13.6 A

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Applications

• DC−DC Converters

• Points of Loads

• Power Load Switch

• Motor Controls

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R

Power Dissipation R (Note 1)

Continuous Drain Current R

Power Dissipation R (Note 2)

Continuous Drain Current R (Note 1)

Power Dissipation

, t v 10 s(Note 1)

Pulsed Drain Current

Operating Junction and Storage Temperature TJ,

Source Current (Body Diode) I

Single Pulse Drain−to−Source Avalanche Energy (T

= 25°C, VDD = 30 V, VGS = 10 V,

= 13 Apk, L = 1.0 mH, RG = 25 W)

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

THERMAL RESISTANCE MAXIMUM RATINGS

Junction−to−Ambient – Steady State (Note 1)

Junction−to−Ambient – t v 10 s (Note 1)

Junction−to−Foot (Drain)

Junction−to−Ambient – Steady State (Note 2)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise stated)

Parameter

Steady

(Note 1)

(Note 2)

, t v 10 s

Parameter Symbol Value Unit

State

Steady

State

Steady

State

Steady

State

Steady

State

TA = 25°C, tp = 10 ms

Symbol Value Unit

DSS

TA = 25°C

TA = 70°C 9.0

TA = 25°C P

TA = 25°C

TA = 70°C 6.9

TA = 25°C P

TA = 25°C

TA = 70°C 11

TA = 25°C P

stg

30 V

±20 V

11.2

1.36 W

8.6

0.81 W

13.6

2.0 W

112 A

−55 to 150

2.1 A

84.5 mJ

260 °C

91.9

61.1

22.6

154.7

°C

°C/W

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(BR)DSS

30 V

DS(ON)

6.5 mW @ 10 V

8.7 mW @ 4.5 V

N−Channel

MAX ID MAX

13.6 A

MARKING DIAGRAM/

PIN ASSIGNMENT

SO−8 CASE 751 STYLE 12

4937N = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

Source Source Source

AYWWG

4937N

Gate

Top View

Drain Drain Drain Drain

ORDERING INFORMATION

Device Package Shipping

NTMS4937NR2G SO−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

2500/Tape & Reel

†

June, 2019− Rev. 0

1 Publication Order Number:

NTMS4937N/D

NTMS4937N

1. Surfacemounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).

2. Surfacemounted on FR4 board using the minimum recommended pad size.

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NTMS4937N

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise specified)

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

Drain−to−Source Breakdown Voltage Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

(BR)DSS/TJ

DSS

GSS

VGS = 0 V, ID = 250 mA

VGS = 0 V, VDS = 24 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient

Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V, ID = 7.5 A 5.4 6.5 mW

VGS = 4.5 V, ID = 6.5 A 7.1 8.7

Forward Transconductance g

VDS = 1.5 V, ID = 7.5 A 27.3 S

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

iss

oss

rss

G(TOT)

G(TH)

G(TOT)

VGS = 0 V, f = 1.0 MHz, VDS = 25 V

VGS = 4.5 V, VDS = 15 V, ID = 7.5 A

VGS = 10 V, VDS = 15 V, ID = 7.5 A 38.5 nC

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(on)

d(off)

VGS = 10 V, VDS = 15 V,

= 1.0 A, RG = 6.0 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

VGS = 0 V, IS = 2.0 A

VGS = 0 V, dIS/dt = 100 A/ms,

= 2.0 A

PACKAGE PARASITIC VALUES

Source Inductance

Drain Inductance L

Gate Inductance L

Gate Resistance R

TA = 25°C

3. Pulse Test: pulse width = 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

30 V

13.1 mV/°C

TJ = 25°C 1.0 mA

TJ = 125°C 10

1.0 2.5 V

5.1 mV/°C

2563

715

17.4

4.1

6.6

3.3

12.3

3.6

33.8

38.9

TJ = 25°C 0.72 1.0

TJ = 125°C 0.56

18.8

21.2

38 nC

0.66

0.2

1.5

0.4 1.0

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NTMS4937N

TYPICAL PERFORMANCE CURVES

10V

4.5 V

4 V

3.6 V

3.2 V

3 V

DRAIN CURRENT (AMPS)

0 1.0 2.0 3.0

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.050

0.040

0.030

0.020

TJ = 25°C

2.8 V

2.6 V

2.4 V

2.2 V

TJ = 25°C

= 7.5 A

VDS ≥ 10 V

48 44 40 36 32 28 24 20 16 12

DRAIN CURRENT (AMPS)

5.04.0 1.5 2.5 3.5

TJ = 125°C

TJ = 25°C

TJ = −55°C

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.008 TJ = 25°C

0.007

VGS = 4.5 V

0.006

0.010

DRAIN−TO−SOURCE RESISTANCE (W)

0.000 2579

DS(on),

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

46 810

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

1.8 ID = 7.5 A

= 10 V

1.6

1.4

1.2

DRAIN−TO−SOURCE

1.0

DS(on),

0.8

RESISTANCE (NORMALIZED)

0.6

−50 −25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (°C)

0.005

DRAIN−TO−SOURCE RESISTANCE (W)

0.004 49

DS(on),

ID, DRAIN CURRENT (AMPS)

VGS = 10 V

14 29

19 24

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

100000

VGS = 0 V

10000

TJ = 150°C

, LEAKAGE (nA)

1000

DSS

100

51015202530

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

TJ = 125°C

Figure 5. On−Resistance Variation with

Temperature

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Figure 6. Drain−to−Source Leakage Current

vs. Voltage

NTMS4937N

TYPICAL PERFORMANCE CURVES

3500

3000

iss

2500

2000

1500

1000

oss

C, CAPACITANCE (pF)

500

0510

rss

15 25

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation Figure 8. Gate−To−Source and

1000

VDD = 15 V

= 1 A

= 10 V

100

t, TIME (ns)

1 10 100

RG, GATE RESISTANCE (OHMS)

TJ = 25°C

VGS = 0 V

d(off)

d(on)

, GATE-TO-SOURCE VOLTAGE (VOLTS)

52515 35

020

Drain−To−Source Voltage vs. Total Charge

VGS = 0 V

= 25°C

1.5

0.5

, SOURCE CURRENT (AMPS)

0.550.5 0.6 0.7

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

10 30

QG, TOTAL GATE CHARGE (nC)

0.65 0.75

VGS = 10 V I

= 7.5 A

= 25°C

0.8

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

1000

100

VGS = 20 V SINGLE PULSE TC = 25°C

, DRAIN CURRENT (AMPS)

0.1

0.01

0.01 10 100

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

0.1

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

10 ms

100 ms

1 ms

10 ms

AVALANCHE ENERGY (mJ)

25 50 75 100

EAS, SINGLE PULSE DRAIN−TO−SOURCE

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Figure 10. Diode Forward Voltage vs. Current

ID = 13 A

150125

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 1:1

−Y−

−Z−

−X− A

0.25 (0.010) Z

SOLDERING FOOTPRINT*

7.0

0.275

SXS

0.25 (0.010)

SEATING PLANE

0.060

0.155

0.10 (0.004)

1.52

4.0

SOIC−8 NB

CASE 751−07

ISSUE AK

X 45

MARKING DIAGRAM*

XXXXX ALYWX

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

XXXXX ALYWX

(Pb−Free)

DATE 16 FEB 2011

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

INCHES

GENERIC

XXXXXX

AYWW

Discrete

XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

XXXXXX

AYWW

Discrete

(Pb−Free)

0.6

0.024

1.270

0.050

SCALE 6:1

inches

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

SOIC−8 NB

CASE 751−07

ISSUE AK

STYLE 3:

STYLE 7:

STYLE 11:

STYLE 15:

STYLE 19:

STYLE 23:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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ON Semiconductor NTMS4937N User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual