ON Semiconductor NTMS4802N User Manual

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Page 1

NTMS4802N

MOSFET – Power,

N-Channel, SO-8

30 V, 18 A

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• This is a Pb−Free Device

Applications

• DC−DC Converters

• Synchronous MOSFET

• Printers

to Minimize Conduction Losses

DS(on)

(BR)DSS

30 V

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MAX ID MAX

DS(ON)

4.0 mW @ 10 V

5.5 mW @ 4.5 V

N−Channel

18 A

MAXIMUM RATINGS (T

Parameter

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R

Power Dissipation R (Note 1)

Continuous Drain Current R

Power Dissipation R (Note 2)

Continuous Drain Current R (Note 1)

Power Dissipation R

Pulsed Drain Current

Operating Junction and Storage Temperature TJ,

Source Current (Body Diode) I

Single Pulse Drain−to−Source Avalanche Energy (T

= 25°C, VDD = 30 V, VGS = 10 V,

= 29 Apk, L = 1.0 mH, RG = 25 W)

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

(Note 1)

(Note 2)

, t v 10 s

, t v 10 s(Note 1)

= 25°C unless otherwise stated)

TA = 25°C

TA = 70°C 12

Steady

State

TA = 25°C, tp = 10 ms

TA = 25°C P

TA = 25°C

TA = 70°C 8.9

TA = 25°C P

TA = 25°C

TA = 70°C 15

TA = 25°C P

Symbol Value Unit

DSS

stg

30 V

±20 V

1.66 W

11.1

0.91 W

2.5 W

60 A

−55 to 150

2.5 A

420 mJ

260 °C

°C

MARKING DIAGRAM/

PIN ASSIGNMENT

SO−8 CASE 751 STYLE 12

4802N = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

Source Source Source

AYWWG

4802N

Gate

Top View

Drain Drain Drain Drain

ORDERING INFORMATION

Device Package Shipping

NTMS4802NR2G SO−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

2500/Tape & Reel

†

June, 2019 − Rev. 0

1 Publication Order Number:

NTMS4802N/D

Page 2

NTMS4802N

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Ambient – Steady State (Note 1)

Junction−to−Ambient – t v 10 s (Note 1)

Junction−to−Foot (Drain)

Junction−to−Ambient – Steady State (Note 2)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surfacemounted on FR4 board using 1 in sq pad size.

2. Surfacemounted on FR4 board using the minimum recommended pad size.

75.5

50.5

138

°C/W

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise specified)

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

Drain−to−Source Breakdown Voltage Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

(BR)DSS/TJ

DSS

GSS

VGS = 0 V, VDS = 24 V

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient

Drain−to−Source On Resistance R

Forward Transconductance g

GS(TH)

GS(TH)/TJ

DS(on)

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

iss

oss

rss

G(TOT)

G(TH)

G(TOT)

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(on)

d(off)

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

VGS = 0 V, ID = 250 mA

30 V

26 mV/°C

TJ = 25°C 1.0 mA

TJ = 85°C 10

VDS = 0 V, VGS = ±20 V ±100 nA

VGS = VDS, ID = 250 mA

1.0 2.5 V

7.0 mV/°C

VGS = 10 V, ID = 18 A 3.2 4.0 mW

VGS = 4.5 V, ID = 15 A 4.3 5.5

VDS = 1.5 V, ID = 18 A 55 S

5300

VGS = 0 V, f = 1.0 MHz, VDS = 25 V

880

460

6.5

VGS = 4.5 V, VDS = 15 V, ID = 18 A

VGS = 10 V, VDS = 15 V, ID = 18 A 75 nC

VGS = 10 V, VDS = 15 V,

= 1.0 A, RG = 6.0 W

TJ = 25°C 0.7 1.0

VGS = 0 V, IS = 2.5 A

TJ = 125°C 0.6

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Page 3

NTMS4802N

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

Parameter UnitMaxTypMinTest ConditionSymbol

DRAIN−SOURCE DIODE CHARACTERISTICS

Reverse Recovery Time

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

VGS = 0 V, dIS/dt = 100 A/ms,

= 2.5 A

PACKAGE PARASITIC VALUES

Source Inductance

Drain Inductance L

Gate Inductance L

Gate Resistance R

TA = 25°C

3. Pulse Test: pulse width = 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

40 nC

0.66 nH

0.20 nH

1.5 nH

1.0 1.5

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Page 4

NTMS4802N

TYPICAL PERFORMANCE CURVES

VGS = 3.4 to 10 V

TJ = 25°C

3.2 V

3.0 V

DRAIN CURRENT (AMPS)

01234 6

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

2.8 V

2.6 V

2.4 V

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.04

TJ = 25°C

= 10 A

0.03

0.02

VDS ≥ 10 V

DRAIN CURRENT (AMPS)

1 2 2.5 3.5

1.5 3

TJ = 100°C

TJ = 25°C

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.006 TJ = 25°C

0.005

0.004

VGS = 4.5 V

TJ = −55°C

0.01

DRAIN−TO−SOURCE RESISTANCE (W)

DS(on),

3456 8

2910

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

2.0 ID = 18 A

1.8

1.6

= 10 V

0.003

DRAIN−TO−SOURCE RESISTANCE (W)

0.002

DS(on),

1000000

100000

525

DRAIN CURRENT (AMPS)

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

VGS = 0 V

1.4

1.2

1.0

DRAIN−TO−SOURCE

0.8

DS(on),

0.6

RESISTANCE (NORMALIZED)

0.4

−50 −25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (°C)

10000

, LEAKAGE (nA)

DSS

1000

100

369

12 15 18 21 24 27 30

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VGS = 10 V

353010 15 20

TJ = 150°C

TJ = 100°C

Figure 5. On−Resistance Variation with

Temperature

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Figure 6. Drain−to−Source Leakage Current

vs. Voltage

Page 5

NTMS4802N

TYPICAL PERFORMANCE CURVES

8000

7000

6000

iss

5000

4000

3000

2000

C, CAPACITANCE (pF)

oss

1000

rss

0510

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation Figure 8. Gate−To−Source and

1000

VDD = 15 V

= 1 A

= 10 V

100

TJ = 25°C

VGS = 0 V

15 25

d(off)

d(on)

, GATE-TO-SOURCE VOLTAGE (VOLTS)

20 40

10 30 50 70

QG, TOTAL GATE CHARGE (nC)

Drain−To−Source Voltage vs. Total Charge

VGS = 0 V

= 25°C

ID = 18 A

= 25°C

60 80

t, TIME (ns)

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

100

VGS = 20 V SINGLE PULSE TC = 25°C

0.1

, DRAIN CURRENT (AMPS)

0.01

0.1 10 100

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

100 ms

1 ms

10 ms

100 ms

, SOURCE CURRENT (AMPS)

0.2

0.40.3 0.5 0.8

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

450

400

350

300

250

200

150

100

AVALANCHE ENERGY (mJ)

EAS, SINGLE PULSE DRAIN−TO−SOURCE

25 50 75 100

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

0.6

0.7

ID = 29 A

150125

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Page 6

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 1:1

−Y−

−Z−

−X− A

0.25 (0.010) Z

SOLDERING FOOTPRINT*

7.0

0.275

0.25 (0.010)

SEATING PLANE

SXS

0.10 (0.004)

1.52

0.060

4.0

0.155

SOIC−8 NB

CASE 751−07

ISSUE AK

X 45

MARKING DIAGRAM*

XXXXX ALYWX

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

XXXXX ALYWX

(Pb−Free)

DATE 16 FEB 2011

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

INCHES

GENERIC

XXXXXX

AYWW

Discrete

XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

XXXXXX

AYWW

Discrete

(Pb−Free)

0.6

0.024

1.270

0.050

SCALE 6:1

inches

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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Page 7

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

SOIC−8 NB

CASE 751−07

ISSUE AK

STYLE 3:

STYLE 7:

STYLE 11:

STYLE 15:

STYLE 19:

STYLE 23:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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Page 8

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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ON Semiconductor NTMS4802N User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual