Page 1
NTMFD5C680NL
MOSFET – Power, Dual,
N-Channel
60 V, 28 mW, 26 A
Features
• Small Footprint (5x6 mm) for Compact Design
• Low R
• Low Q
to Minimize Conduction Losses
DS(on)
and Capacitance to Minimize Driver Losses
G
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (T
Parameter
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain
Current R
(Notes 1, 2, 3)
Power Dissipation
R
q
JC
Continuous Drain
Current R
(Notes 1, 2, 3)
Power Dissipation
R
q
JA
Pulsed Drain Current
Operating Junction and Storage Temperature TJ, T
Source Current (Body Diode) I
Single Pulse Drain−to−Source Avalanche
Energy (I
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
q
JC
(Notes 1, 2)
q
JA
(Notes 1 & 2)
= 5 A)
L(pk)
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
= 25°C unless otherwise noted)
J
Symbol Value Unit
TC = 25°C
Steady
State
Steady
State
TA = 25°C, t
TC = 100°C 13
TC = 25°C
TC = 100°C 9.5
TA = 25°C
TA = 100°C 5.3
TA = 25°C
TA = 100°C 1.5
= 10 ms
p
P
P
I
E
R
q
R
q
2
, 2 oz. Cu pad.
DSS
GS
I
D
D
I
D
D
DM
S
AS
T
L
JC
JA
stg
60 V
±20 V
26
19
7.5
3.0
57 A
−55 to
+ 175
33 A
47 mJ
260 °C
3.74
49
A
W
A
W
°C
°C/W
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G1
V
(BR)DSS
60 V
R
DS(ON)
28 mW @ 10 V
41 mW @ 4.5 V
Dual N−Channel
D1
S1
MAX ID MAX
26 A
D2
G2
S2
MARKING
DIAGRAM
D1
D1
1
DFN8 5x6
(SO8FL)
CASE 506BT
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
S1
G1
S2
G2
XXXXXX
AYWZZ
D2
D1
D1
D2
D2
D2
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
May, 2019 − Rev. P3
1 Publication Order Number:
NTMFD5C680NL/D
Page 2
NTMFD5C680NL
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
V
V
Temperature Coefficient
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
(BR)DSS
(BR)DSS
T
J
DSS
GSS
VGS = 0 V, ID = 250 mA
/
VGS = 0 V,
V
= 60 V
DS
TJ = 25 °C 10
TJ = 125°C 100
VDS = 0 V, VGS = 20 V 100 nA
60 V
29
mV/°C
mA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient V
V
GS(TH)/TJ
Drain−to−Source On Resistance R
Forward Transconductance g
GS(TH)
DS(on)
FS
VGS = VDS, ID = 13 mA
VGS = 10 V ID = 5 A 23 28
VGS = 4.5 V ID = 5 A 33 41
VDS = 15 V, ID = 10 A 50 S
1.2 2.2 V
−4.3 mV/°C
mW
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
Plateau Voltage V
C
ISS
OSS
RSS
G(TOT)
G(TOT)
G(TH)
GS
GD
GP
VGS = 0 V, f = 1 MHz, VDS = 25 V
VGS = 4.5 V, VDS = 48 V; ID = 10 A 2.0
VGS = 10 V, VDS = 48 V; ID = 10 A 5.0
VGS = 4.5 V, VDS = 48 V; ID = 10 A
350
150
6
0.8
1.2
0.8
3.0 V
pF
nC
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
d(ON)
Rise Time t
Turn−Off Delay Time t
d(OFF)
Fall Time t
r
f
VGS = 4.5 V, VDS = 48 V,
= 5 A, RG = 1.0 W
I
D
6.4
25
19
23
ns
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
RR
a
b
RR
VGS = 0 V,
I
= 5 A
S
VGS = 0 V, dIS/dt = 10 A/ms,
I
= 5 A
S
TJ = 25°C 0.9 1.2
TJ = 125°C 0.8
17
8
9
7 nC
V
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
Page 3
NTMFD5C680NL
TYPICAL CHARACTERISTICS
30.0
25.0
20.0
15.0
10.0
, DRAIN CURRENT (A)
D
I
5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
VGS = 4.5 V to 10 V
..
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
55
50
45
40
35
TJ = 25°C
I
D
= 5 A
3.6 V
3.4 V
3.2 V
3.0 V
2.8 V
2.6 V
50
VDS = 10 V
45
40
35
30
25
20
15
, DRAIN CURRENT (A)
D
10
I
5
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
45
TJ = 25°C
40
35
30
TJ = 25°C
TJ = 125°C
VGS = 4.5 V
TJ = −55°C
30
25
20
, DRAIN−TO−SOURCE RESISTANCE (mW)
15
345678910
DS(on)
R
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2.2
VGS = 10 V
2
= 5 A
I
D
1.8
1.6
1.4
1.2
1
, NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
0.8
DS(on)
R
0.6
−50 −25 0 25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
25
20
, DRAIN−TO−SOURCE RESISTANCE (mW)
15
5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
DS(on)
R
Figure 4. On−Resistance vs. Drain Current and
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
, LEAKAGE (nA)
1.E+00
DSS
I
1.E−01
1.E−02
5 1525354555
Figure 6. Drain−to−Source Leakage Current
VGS = 10 V
Gate Voltage
TJ = 150°C
TJ = 125°C
TJ = 85°C
TJ = 25°C
vs. Voltage
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3
Page 4
NTMFD5C680NL
TYPICAL CHARACTERISTICS
1.E+03
1.E+02
1.E+01
C, CAPACITANCE (pF)
VGS = 0 V
= 25°C
T
J
f = 1 MHz
1.E+00
0 102030405060
VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge
100
t
r
t
f
t
10
d(off)
10
VDS = 48 V
9
= 25°C
T
C
ISS
C
OSS
J
8
I
= 10 A
D
7
6
5
4
Q
GS
3
Q
GD
2
C
RSS
1
, GATE−TO−SOURCE VOLTAGE (V)
GS
0
V
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
10
VGS = 0 V
t, TIME (ns)
t
d(on)
VGS = 4.5 V
= 48 V
V
DS
I
= 10 A
1
1 10 100
D
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
1000
100
1 ms
10
1
, DRAIN CURRENT (A)
D
I
10 ms
R
DS(on)
Limit
Thermal Limit
Package Limit
0.1
0.1 1 10 100 1000
VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s)
TC = 25°C
≤ 10 V
V
GS
Single Pulse
10 ms
0.5 ms
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
TJ = 125°C
, SOURCE CURRENT (A)
S
I
1
TJ = 25°C
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
TJ = −55°C
Figure 10. Diode Forward Voltage vs. Current
100
10
, (A)
PEAK
I
TJ (initial) = 100°C
1
0.1
0.00001 0.001 0.010.0001
Figure 12. I
PEAK
TJ (initial) = 25°C
vs. Time in Avalanche
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4
Page 5
NTMFD5C680NL
TYPICAL CHARACTERISTICS
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device Marking Package Shipping
NTMFD5C680NLT1G 5C680L DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1500 / Tape & Reel
†
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5
Page 6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
1
SCALE 2:1
PIN ONE
IDENTIFIER
NOTE 7
0.10 C
0.10 C
NOTE 4
DETAIL B
M
1234
TOP VIEW
SIDE VIEW
D3
e
14
N
8
4X
G
K1
BOTTOM VIEW
D
D1
78
D2
5
56
2X
DETAIL A
4X
4X
b1
0.20 C
A
E1
A
L
8X
B
2X
0.20 C
E
c
SEATING
C
PLANE
NOTE 6
K
DETAIL B
ALTERNATE
CONSTRUCTION
E2
b
C
A0.10 B
0.05
C
NOTE 3
CASE 506BT
ISSUE E
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
4X
h
GENERIC
MARKING DIAGRAM*
A1
*This information is generic. Please refer
to device data sheet for actual part
marking.
1
XXXXXX
AYWZZ
XXXXXX= Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
SOLDERING FOOTPRINT*
4.56
8X
0.75
4.84
2.30
DATE 26 FEB 2013
MILLIMETERS
3.70
MAX
−−−
−−−
0.42
−−−
4.90
4.10
5.90
4.15
0.55
−−−
−−−
0.61
3.50
2X
0.56
6.59
DIM MIN
A 0.90
A1 −−−
b 0.33
b1 0.33 0.42
c 0.20
D 5.15 BSC
D1 4.70
D2 3.90
D3 1.50 1.70
E 6.15 BSC
E1 5.70
E2 3.90
e 1.27 BSC
G 0.45
h −−−
K 0.51
K1 0.56 −−−
L 0.48
M 3.25
N 1.80 2.00
2X
2.08
4X
1.40
MAX
1.10
0.05
0.51
0.51
0.33
5.10
4.30
1.90
6.10
4.40
0.65
12
−−−
−−−
0.71
3.75
2.20
_
0.70
4X
1.00
1.27
PITCH
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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© Semiconductor Components Industries, LLC, 2019
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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