ON Semiconductor NTMD5838NL User Manual

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NTMD5838NL

MOSFET – Power, Dual,

N-Channel, SO-8

40 V, 8.9 A, 20 mW

Features

• Low R

• Low Capacitance

• Optimized Gate Charge

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R (Note 1)

Power Dissipation R

Continuous Drain Current R (Note 1)

Power Dissipation R

Pulsed Drain Current

Operating Junction and Storage Temperature

Source Current (Body Diode) I

Single Pulse Drain−to−Source Avalanche Energy (L = 0.1 mH)

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

THERMAL RESISTANCE MAXIMUM RATINGS

Junction−to−Ambient Steady State (Notes 1 & 3)

Junction−to−Ambient − t ≤10 s (Note 1)

Junction−to−Ambient Steady State (Note 2)

1. Surface−mounted on FR4 board using 1 sq−in pad

2. Surface−mounted on FR4 board using 0.155 in sq (100mm

3. Both channels receive equivalent power dissipation

DS(on)

Compliant

= 25°C unless otherwise stated)

Parameter

TA = 25°C

(Note 1)

(Cu area = 1.127 in sq [2 oz] including traces).

1 W applied on each channel: T

Steady

State

t ≤10 s

Parameter Symbol Value Unit

TA = 70°C 5.9

TA = 25°C

TA = 70°C 1.3

TA = 25°C

TA = 70°C 7.1

TA = 25°C

TA = 70°C 1.9

tp = 10 ms

= 2 W * 58°C/W + 25°C = 141°C

Symbol Value Unit

DSS

TJ, T

STG

EAS 20 mJ

IAS 21 A

40 V

±20 V

7.4

2.1

8.9

3.0

35 A

−55 to +150

7.0 A

260 °C

106

) pad size.

°C

°C/W

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(BR)DSS

40 V

MAX ID MAX

DS(ON)

20 mW @ 10 V

36.5 mW @ 4.5 V

N−CHANNEL MOSFET

8.9 A

MARKING DIAGRAM/

PIN ASSIGNMENT

D1 D1 D2D2

SO−8

CASE 751

STYLE 11

A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

D5838N

AYWW

S1 G1 S2 G2

(Top View)

ORDERING INFORMATION

Device Package Shipping

NTMD5838NLR2G SO−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

2500/Tape & Reel

†

May, 2019 − Rev. 1

1 Publication Order Number:

NTMD5838NL/D

NTMD5838NL

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise specified)

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

Drain−to−Source Breakdown Voltage Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

VGS = 0 V, ID = 250 mA

VGS = 0 V,

= 40 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 4)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient V

Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V, ID = 7 A 16.2 20

VGS = 4.5 V, ID = 7 A 25.0 36.5

Forward Transconductance g

VDS = 15 V, ID = 7 A 4.0 S

CHARGES, CAPACITANCES & GATE RESISTANCE

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Plateau Voltage V

Gate Resistance R

ISS

OSS

RSS

G(TOT)

G(TH)

VGS = 0 V, f = 1 MHz, VDS = 20 V

VGS = 10 V, VDS = 20 V; ID = 7 A 17

VGS = 4.5 V, VDS = 20 V; ID = 7 A

SWITCHING CHARACTERISTICS (Note 5)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

d(OFF)

VGS = 4.5 V, VDS = 20 V,

= 7 A, RG = 2.5 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

VGS = 0 V,

= 7 A

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 7 A

4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

5. Switching characteristics are independent of operating junction temperatures.

40 V

TJ = 25 °C 1.0

TJ = 125°C 100

1.0 1.8 3.0 V

6.0 mV/°C

785

123

8.6 11

0.8

2.8

4.0

3.2 V

1.8

4.0

TJ = 25°C 0.84 1.2

TJ = 125°C 0.7

6.0

10 nC

mV/°C

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NTMD5838NL

TYPICAL PERFORMANCE CURVES

10 V

5.5 V

7.5 V

4.4 V

TJ = 25°C

4 V

DRAIN CURRENT (A)

3.6 V

3 V

012345

, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 1. On−Region Characteristics

0.06 TJ = 25°C

= 7 A

0.05

0.04

0.03

VDS ≥ 5 V

TJ = 125°C

DRAIN CURRENT (A)

TJ = 25°C

TJ = −55°C

2345

VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 2. Transfer Characteristics

0.035

TJ = 25°C

0.025

0.015

VGS = 4.5 V

VGS = 10 V

0.02

DRAIN−TO−SOURCE RESISTANCE (W)

0.01

DS(on),

2345678910

VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

1.6 VGS = 4.5 V

= 7 A

1.4

1.2

DRAIN−TO−SOURCE

0.8

DS(on),

RESISTANCE (NORMALIZED)

0.6

−50 −25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

DRAIN−TO−SOURCE RESISTANCE (W)

0.005 2 6 10 14 18

DS(on),

DRAIN CURRENT (A)

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

100000

VGS = 0 V

10000

, LEAKAGE (nA)

1000

DSS

TJ = 150°C

TJ = 125°C

100

5152535

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

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NTMD5838NL

TYPICAL PERFORMANCE CURVES

1200

TJ = 25°C

1000

800

iss

VGS = 0 V

600

400

C, CAPACITANCE (pF)

200

rss

010203040

oss

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 7. Capacitance Variation

1000

VDS = 20 V

= 7 A

= 4.5 V

100

d(on)

t, TIME (ns)

d(off)

, GATE−TO−SOURCE (V)

012345678910

VGS = 10 V

= 7 A

= 25°C

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate−To−Source and

Drain−To−Source Voltage vs. Total Charge

VGS = 0 V

= 25°C

, SOURCE CURRENT (A)

, DRAIN−TO−SOURCE (V)

1 10 100

RG, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

100

VGS = 10 V

0.1 SINGLE PULSE

0.01

TC = 25°C

DS(on)

LIMIT

, DRAIN CURRENT (A)

THERMAL LIMIT

0.001

PACKAGE LIMIT

0.1 1 10 100

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1 ms

10 ms

100 ms

10 ms

0.2 0.4 0.6 0.8 1 VSD, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 10. Diode Forward Voltage vs. Current

ID = 20 A

EAS, SINGLE PULSE DRAIN−TO−

SOURCE AVALANCHE ENERGY (mJ)

25 50 75 100 125 150

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

http://onsemi.com

R(t) (°C/W)

100

0.1

NTMD5838NL

TYPICAL PERFORMANCE CURVES

D = 0.5

0.2

0.1

0.05

0.02

0.01

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

SINGLE PULSE

t, TIME (s)

Figure 13. Thermal Response

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 1:1

−Y−

−Z−

−X−

0.25 (0.010) Z

SOLDERING FOOTPRINT*

7.0

0.275

0.25 (0.010)

SEATING PLANE

SXS

0.060

0.10 (0.004)

1.52

4.0

0.155

CASE 751−07

SOIC−8 NB

ISSUE AK

X 45

MARKING DIAGRAM*

XXXXX ALYWX

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

XXXXX ALYWX

(Pb−Free)

DATE 16 FEB 2011

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050

M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

INCHES

GENERIC

XXXXXX

AYWW

Discrete

XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

XXXXXX

AYWW

Discrete

(Pb−Free)

0.6

0.024

1.270

0.050

SCALE 6:1

inches

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

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STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

SOIC−8 NB

CASE 751−07

ISSUE AK

STYLE 3:

STYLE 7:

STYLE 11:

STYLE 15:

STYLE 19:

STYLE 23:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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ON Semiconductor NTMD5838NL User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual