Datasheet NSTB1005DXV5T1, NSTB1005DXV5T5 Datasheet (ON Semiconductor)

NSTB1005DXV5T1, NSTB1005DXV5T5
Preferred Devices
Dual Common Base−Collector Bias Resistor Transistors
NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminates these individual components by integrating them into a single device. The NSTB1005DXV5T1 contains two complementary BR T devices are housed i n the SOT−553 package which is ideal for low power surface mount applications where board space is at a premium.
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Available in 8 mm, 7 inch Tape and Reel
Lead Free
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312
R1
Q1
45
CASE 463B
R2
Q2
R2
R1
5
1
SOT−553
MAXIMUM RATINGS (T
and Q2, − minus sign for Q1 (PNP) omitted)
Rating
Collector-Base Voltage V Collector-Emitter Voltage V Collector Current I
= 25°C unless otherwise noted, common for Q
A
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
T
= 25°C
A
Derate above 25°C Thermal Resistance −
Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation
T
= 25°C
A
Derate above 25°C Thermal Resistance −
Junction-to-Ambient
Junction and Storage Temperature TJ, T
1. FR−4 @ Minimum Pad
Symbol Value Unit
CBO CEO
C
Symbol Max Unit
P
D
R
JA
Symbol Max Unit
P
D
R
JA
stg
50 Vdc 50 Vdc
100 mAdc
357 (Note 1)
2.9 (Note 1)mWmW/°C
350 (Note 1) °C/W
500 (Note 1)
4.0 (Note 1)
250 (Note 1) °C/W
−55 to +150 °C
mW
mW/°C
1
MARKING DIAGRAM
5
UC D
1
UC = Specific Device Code D = Date Code
ORDERING INFORMATION
Device Package Shipping
NSTB1005DXV5T1 SOT−553 4 mm pitch
4000/Tape & Reel
NSTB1005DXV5T5 SOT−553 2 mm pitch
8000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Preferred devices are recommended choices for future use and best overall value.
Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 0
1 Publication Order Number:
NSTB1005DXV5/D
NSTB1005DXV5T1, NSTB1005DXV5T5
ELECTRICAL CHARACTERISTICS (T
Characteristic
= 25°C unless otherwise noted)
A
Symbol Min Typ Max Unit
Q1 TRANSISTOR: PNP − OFF CHARACTERISTICS
Collector−Base Cutoff Current (V
= 50 V, IE = 0) I
CB
Collector−Emitter Cutoff Current (VCE = 50 V, IB = 0) I Emitter−Base Cutoff Current I Collector−Base Breakdown Voltage (IC = 10 A, IE = 0) V Collector−Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
CBO CEO
EBO (BR)CBO (BR)CEO
100 nAdc
500 nAdc
0.1 mAdc 50 Vdc 50 Vdc
ON CHARACTERISTICS
DC Current Gain h Collector−Emitter Saturation Voltage (IC = 10 mA, IE = 0.3 mA) V Output Voltage (on) (VCC = 5.0 V, VB = 3.5 V, RL = 1.0 k) V Output Voltage (off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k) V
FE
CE(sat)
OL OH
80 140
0.25 Vdc
0.2 Vdc
4.9 Vdc
Input Resistor R1 32.9 47 61.1 k
Resistor Ratio R1/R
0.8 1.0 1.2
2
Q2 TRANSISTOR: NPN − OFF CHARACTERISTICS
Collector-Base Cutoff Current (VCB = 50 V, IE = 0) I Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) I Emitter-Base Cutoff Current (VEB = 6.0, IC = 5.0 mA) I
CBO CEO EBO
100 nAdc
500 nAdc
0.1 mAdc
ON CHARACTERISTICS
Collector-Base Breakdown Voltage (I Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
= 10 A, IE = 0) V
C
(BR)CBO (BR)CEO
DC Current Gain (VCE = 10 V, IC = 5.0 mA) h Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) V Output Voltage (on) (VCC = 5.0 V, V Output Voltage (off) (VCC = 5.0 V, V
= 2.5 V, RL = 1.0 k) V
B
= 0.5 V, RL = 1.0 k) V
B
CE(SAT)
FE
OL OH
50 Vdc 50 Vdc 80 140
0.25 Vdc
0.2 Vdc
4.9 Vdc Input Resistor R1 33 47 61 k Resistor Ratio R1/R2 0.8 1.0 1.2
250
200
150
100
R
= 833°C/W
50
, POWER DISSIPATION (MILLIWATTS)
D
P
0
−50 0 50 100 150
JA
T
, AMBIENT TEMPERATURE (°C)
A
Figure 1. Derating Curve
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2
NSTB1005DXV5T1, NSTB1005DXV5T5
TYPICAL ELECTRICAL CHARACTERISTICS − PNP TRANSISTOR
1
IC/IB = 10
0.1
, MAXIMUM COLLECTOR VOLTAGE (VOLTS)
0.01
CE(sat)
V
0 40
20
I
, COLLECTOR CURRENT (mA)
C
Figure 2. V
CE(sat)
4
3
2
T
=−25°C
A
75°C
versus I
C
f = 1 MHz l
= 0 V
E
= 25°C
T
A
25°C
1000
VCE = 10 V
T
=75°C
A
25°C
100
−25°C
, DC CURRENT GAIN (NORMALIZED)
FE
h
10
50
1 10 100
IC, COLLECTOR CURRENT (mA)
Figure 3. DC Current Gain
100
75°C
10
1
25°C
T
=−25°C
A
, CAPACITANCE (pF)
ob
1
C
0
010203040
, REVERSE BIAS VOLTAGE (VOLTS)
V
R
Figure 4. Output Capacitance Figure 5. Output Current versus Input Voltage
100
VO = 0.2 V
10
1
, INPUT VOLTAGE (VOLTS)
in
V
0.1
0
Figure 6. Input Voltage versus Output Current
0.1
, COLLECTOR CURRENT (mA)
C
0.01
I
50
0.001
0
1 2 3 4 5
Vin, INPUT VOLTAGE (VOLTS)
T
=−25°C
A
25°C
75°C
10 20 30 40 50
, COLLECTOR CURRENT (mA)
I
C
VO = 5 V
6 7 8 9 10
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NSTB1005DXV5T1, NSTB1005DXV5T5
TYPICAL ELECTRICAL CHARACTERISTICS — NPN TRANSISTOR
0.1
, MAXIMUM COLLECTOR VOLTAGE (VOLTS)
0.01
CE(sat)
V
0.8
0.6
10
IC/IB = 10
1
1000
VCE = 10 V
T
=75°C
A
25°C
−25°C
T
=−25°C
A
25°C
75°C
0
Figure 7. V
20 40
I
, COLLECTOR CURRENT (mA)
C
versus I
CE(sat)
C
50
1
f = 1 MHz I
= 0 mA
E
= 25°C
T
A
100
, DC CURRENT GAIN
FE
h
10
1 100
, COLLECTOR CURRENT (mA)
I
C
10
Figure 8. DC Current Gain
100
75°C
10
25°C
T
=−25°C
A
1
0.4
, CAPACITANCE (pF)
ob
C
0.2
0
010203040
, REVERSE BIAS VOLTAGE (VOLTS)
V
R
Figure 9. Output Capacitance
100
VO = 0.2 V
10
1
, INPUT VOLTAGE (VOLTS)
in
V
0.1 010 203040 50
Figure 11. Input Voltage versus Output Current
0.1
0.01
, COLLECTOR CURRENT (mA)
C
I
50
, COLLECTOR CURRENT (mA)
I
C
0.001
T
=−25°C
A
VO = 5 V
0246810
V
, INPUT VOLTAGE (VOLTS)
in
Figure 10. Output Current versus Input Voltage
25°C
75°C
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4
A
−X−
45
12 3
G
NSTB1005DXV5T1, NSTB1005DXV5T5
PACKAGE DIMENSIONS
SOT−553
XV5 SUFFIX
5−LEAD P ACKAGE
CASE 463B−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
B
−Y−
D
5 PL
0.08 (0.003) X
M
C
K
S
J
Y
SOLDERING FOOTPRINT*
Y14.5M, 1982.
FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
MILLIMETERS
DIMAMIN MAX MIN MAX
1.50 1.70 0.059 0.067
B 1.10 1.30 0.043 0.051 C 0.50 0.60 0.020 0.024 D 0.17 0.27 0.007 0.011 G 0.50 BSC 0.020 BSC J 0.08 0.18 0.003 0.007
0.10 0.30
K
1.50 1.70
S
INCHES
0.004 0.012
0.059 0.067
0.3
0.0118
0.45
0.0177
1.0
1.35
0.0394
0.0531
0.5
0.5
0.0197
0.0197
mm
SCALE 20:1
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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5
NSTB1005DXV5T1, NSTB1005DXV5T5
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NSTB1005DXV5/D
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