NSS40301MDR2G
Dual Matched 40 V, 6.0 A,
Low V
CE(sat)
These transistors are part of the ON Semiconductor e2PowerEdge
family of Low V
transistors. They are assembled to create a pair
CE(sat)
of devices highly matched in all parameters, including ultra low
saturation voltage V
CE(sat)
voltage.
Typical applications are current mirrors, differential amplifiers,
DC−DC converters and power management in portable and battery
powered products such as cellular and cordless phones, PDAs,
computers, printers, digital cameras and MP3 players. Other
applications are low voltage motor controls in mass storage products
such as disc drives and tape drives. In the automotive industry they can
be used in air bag deployment and in the instrument cluster. The high
current gain allows e
2
PowerEdge devices to be driven directly from
PMU’s control outputs, and the Linear Gain (Beta) makes them ideal
components in analog amplifiers.
Features
• Current Gain Matching to 10%
• Base Emitter Voltage Matched to 2 mV
• This is a Pb−Free Device
NPN Transistor
, high current gain and Base/Emitter turn on
http://onsemi.com
40 VOLTS
6.0 AMPS
NPN LOW V
CE(sat)
EQUIVALENT R
COLLECTOR
7,8
2
BASE
1
EMITTER
TRANSISTOR
DS(on)
BASE
44 mW
COLLECTOR
5,6
4
3
EMITTER
MAXIMUM RATINGS (T
Rating
Collector-Emitter Voltage V
Collector-Base Voltage V
Emitter-Base Voltage V
Collector Current − Continuous I
Collector Current − Peak I
Electrostatic Discharge ESD HBM Class 3B
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
= 25°C)
A
Symbol Max Unit
CEO
CBO
EBO
C
CM
40 Vdc
40 Vdc
6.0 Vdc
3.0 A
6.0 A
MM Class C
8
1
SOIC−8
CASE 751
STYLE 16
DEVICE MARKING
8
N40301
AYWWG
G
1
N40301 = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
NSS40301MDR2G SOIC−8
(Pb−Free)
†
2500 /
Tape & Reel
© Semiconductor Components Industries, LLC, 2008
May, 2008 − Rev. 1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1 Publication Order Number:
NSS40301MD/D
NSS40301MDR2G
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
SINGLE HEATED
Total Device Dissipation (Note 1)
= 25°C
T
A
Derate above 25°C
Thermal Resistance, Junction−to−Ambient (Note 1)
Total Device Dissipation (Note 2)
T
= 25°C
A
Derate above 25°C
Thermal Resistance, Junction−to−Ambient (Note 2)
DUAL HEATED (Note 3)
Total Device Dissipation (Note 1)
= 25°C
T
A
Derate above 25°C
Thermal Resistance, Junction−to−Ambient (Note 1)
Total Device Dissipation (Note 2)
T
= 25°C
A
Derate above 25°C
Thermal Resistance, Junction−to−Ambient (Note 2)
Junction and Storage Temperature Range TJ, T
1. FR− 4 @ 10 mm2, 1 oz. copper traces, still air.
2. FR− 4 @ 100 mm
2
, 1 oz. copper traces, still air.
3. Dual heated values assume total power is the sum of two equally powered devices.
P
D
R
q
JA
P
D
R
q
JA
P
D
R
q
JA
P
D
R
q
JA
stg
576
4.6
mW
mW/°C
217 °C/W
676
5.4
mW
mW/°C
185 °C/W
653
5.2
mW
mW/°C
191 °C/W
783
6.3
mW
mW/°C
160 °C/W
−55 to +150 °C
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2
NSS40301MDR2G
ELECTRICAL CHARACTERISTICS (T
Characteristic
= 25°C unless otherwise noted)
A
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector−Emitter Breakdown Voltage
(I
= 10 mAdc, IB = 0)
C
Collector−Base Breakdown Voltage
(I
= 0.1 mAdc, IE = 0)
C
Emitter−Base Breakdown Voltage
(I
= 0.1 mAdc, IC = 0)
E
Collector Cutoff Current
(V
= 40 Vdc, IE = 0)
CB
Emitter Cutoff Current
(V
= 6.0 Vdc)
EB
V
(BR)CEO
V
(BR)CBO
V
(BR)EBO
I
CBO
I
EBO
40 − −
40 − −
6.0 − −
− − 0.1
− − 0.1
ON CHARACTERISTICS
DC Current Gain (Note 4)
(I
= 10 mA, VCE = 2.0 V)
C
= 500 mA, VCE = 2.0 V)
(I
C
(I
= 1.0 A, VCE = 2.0 V)
C
(I
= 2.0 A, VCE = 2.0 V)
C
(I
= 2.0 A, VCE = 2.0 V) (Note 5)
C
Collector−Emitter Saturation Voltage (Note 4)
(I
= 0.1 A, IB = 0.010 A)
C
= 1.0 A, IB = 0.100 A)
(I
C
(I
= 1.0 A, IB = 0.010 A)
C
(I
= 2.0 A, IB = 0.200 A)
C
Base −Emitter Saturation Voltage (Note 4)
(I
= 1.0 A, IB = 0.01 A)
C
Base −Emitter Turn−on Voltage (Note 4)
(I
= 0.1 A, VCE = 2.0 V)
C
= 0.1 A, VCE = 2.0 V) (Note 6)
(I
C
Cutoff Frequency
(I
= 100 mA, VCE = 5.0 V, f = 100 MHz)
C
h
h
FE(1)/hFE(2)
V
CE(sat)
V
BE(sat)
V
BE(on)
V
BE(1) −
f
FE
200
200
180
180
0.9
−
−
−
−
400
350
340
320
0.99
0.008
0.044
0.080
0.082
−
−
−
−
−
0.011
0.060
0.115
0.115
− 0.780 0.900
V
BE(2)
T
−
−
0.650
0.3
0.750
2.0
100 − −
Input Capacitance (VEB = 0.5 V, f = 1.0 MHz) Cibo − 320 450 pF
Output Capacitance (VCB = 3.0 V, f = 1.0 MHz) Cobo − 40 50 pF
SWITCHING CHARACTERISTICS
Delay (V
= 30 V, IC = 750 mA, IB1 = 15 mA) t
CC
Rise (VCC = 30 V, IC = 750 mA, IB1 = 15 mA) t
Storage (VCC = 30 V, IC = 750 mA, IB1 = 15 mA) t
Fall (VCC = 30 V, IC = 750 mA, IB1 = 15 mA) t
d
r
s
f
− − 100 ns
− − 100 ns
− − 780 ns
− − 110 ns
4. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle ≤ 2%.
5. h
FE(1)/hFE(2)
6. V
BE(1)
is the ratio of one transistor compared to the other transistor within the same package. The smaller hFE is used as numerator.
− V
is the absolute difference of one transistor compared to the other transistor within the same package.
BE(2)
Vdc
Vdc
Vdc
mAdc
mAdc
V
V
V
mV
MHz
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3
NSS40301MDR2G
TYPICAL CHARACTERISTICS
0.16
IC/IB = 10
0.14
0.12
0.10
0.08
0.06
, COLLECTOR−EMITTER
0.04
SATURATION VOLTAGE (V)
CE(sat)
0.02
V
0
IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)
Figure 1. Collector Emitter Saturation Voltage
vs. Collector Current
700
150°C (2.0 V)
600
500
25°C (5.0 V)
400
25°C (2.0 V)
300
, DC CURRENT GAIN
−55°C (5.0 V)
FE
h
−55°C (2.0 V)
200
100
IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)
150°C (5.0 V)
Figure 3. DC Current Gain vs. Collector
Current
150°C
25°C
−55°C
1010.10.010.001
, COLLECTOR−EMITTER
V
1010.10.010.001
, BASE−EMITTER
BE(sat)
V
0.30
0.25
0.20
0.15
0.10
SATURATION VOLTAGE (V)
0.05
CE(sat)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
SATURATION VOLTAGE (V)
0.3
0.2
IC/IB = 100
150°C
25°C
−55°C
0
1010.10.010.001
Figure 2. Collector Emitter Saturation Voltage
vs. Collector Current
IC/IB = 10
−55°C
25°C
150°C
1010.10.010.001
Figure 4. Base Emitter Saturation Voltage vs.
Collector Current
VOLTAGE (V)
, BASE−EMITTER TURN−ON
BE(on)
V
1.0
0.9
VCE = +2.0 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
IC, COLLECTOR CURRENT (A) Ib, BASE CURRENT (A)
−55°C
25°C
150°C
Figure 5. Base Emitter Turn−On Voltage vs.
Collector Current
1.0
0.9
0.8
0.7
0.6
0.5
0.4
VOLTAGE (V)
0.3
, COLLECTOR−EMITTER
0.2
CE(sat)
V
0.1
1010.10.010.001
0
http://onsemi.com
4
100 mA
1 A
2 A
Figure 6. Saturation Region
3 A
0.10.010.0010.0001
NSS40301MDR2G
TYPICAL CHARACTERISTICS
400
375
350
325
300
275
250
225
, INPUT CAPACITANCE (pF)
200
ibo
C
175
150
80
70
60
50
C
(pF)
ibo
6543210
VEB, EMITTER−BASE VOLTAGE (V) Vcb, COLLECTOR−BASE VOLTAGE (V)
40
30
, OUTPUT CAPACITANCE (pF)
20
obo
C
10
C
(pF)
obo
Figure 7. Input Capacitance Figure 8. Output Capacitance
1.0
0.1
(A)
C
I
0.01
10
1 s
Thermal Limit
1 ms
10 ms
100 ms
40
35302520151050
0.001
Single Pulse Test at TA = 25°C
(Vdc)
V
CE
Figure 9. Safe Operating Area
10
1001.00.10.01
http://onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
8
1
SCALE 1:1
B
−Y−
−Z−
−X−
A
58
1
4
G
H
D
0.25 (0.010) Z
M
SOLDERING FOOTPRINT*
7.0
0.275
S
Y
0.25 (0.010)
C
SEATING
PLANE
SXS
0.10 (0.004)
1.52
0.060
4.0
0.155
CASE 751−07
M
M
Y
N
SOIC−8 NB
ISSUE AK
K
X 45
_
M
J
MARKING DIAGRAM*
8
XXXXX
ALYWX
1
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
8
XXXXX
ALYWX
G
1
IC
IC
(Pb−Free)
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
____
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
INCHES
GENERIC
8
XXXXXX
AYWW
1
Discrete
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
8
XXXXXX
AYWW
1
Discrete
(Pb−Free)
G
0.6
0.024
1.270
0.050
SCALE 6:1
ǒ
inches
mm
Ǔ
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
SOIC−8 NB
CASE 751−07
ISSUE AK
STYLE 3:
STYLE 7:
STYLE 11:
STYLE 15:
STYLE 19:
STYLE 23:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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