NSS35200MR6T1G
35 V, 5 A, Low V
CE(sat)
PNP Transistor
ON Semiconductor’s e2PowerEdge family of low V
transistors are miniature surface mount devices featuring ultra low
saturation voltage (V
) and high current gain capability. These
CE(sat)
are designed for use in low voltage, high speed switching applications
where affordable efficient energy control is important.
Typical application are DC−DC converters and power management
in portable and battery powered products such as cellular and cordless
phones, PDAs, computers, printers, digital cameras and MP3 players.
Other applications are low voltage motor controls in mass storage
products such as disc drives and tape drives. In the automotive
industry they can be used in air bag deployment and in the instrument
cluster. The high current gain allows e
2
PowerEdge devices to be
driven directly from PMU’s control outputs, and the Linear Gain
(Beta) makes them ideal components in analog amplifiers.
Features
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant*
CE(sat)
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35 VOLTS
5.0 AMPS
PNP LOW V
CE(sat)
EQUIVALENT R
6
CASE 318G
3
BASE
TRANSISTOR
DS(on)
4
5
3
2
1
TSOP−6
STYLE 6
COLLECTOR
1, 2, 5, 6
100 mW
MAXIMUM RATINGS (T
Rating Symbol Max Unit
Collector-Emitter Voltage V
Collector-Base Voltage V
Emitter-Base Voltage V
Collector Current − Continuous I
Collector Current − Peak I
Electrostatic Discharge ESD HBM Class 3
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
= 25°C)
A
CEO
CBO
EBO
C
CM
−35 Vdc
−55 Vdc
−5.0 Vdc
−2.0 Adc
−5.0 A
MM Class C
4
EMITTER
MARKING DIAGRAM
M G
VS8
G
VS8 = Device Code
M = Date Code*
G = Pb−Free Package
(*Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
Device
NSS35200MR6T1G TSOP−6
SNSS35200MR6T1G TSOP−6
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Package Shipping
3,000 /
(Pb−Free)
(Pb−Free)
Tape & Reel
3,000 /
Tape & Reel
†
© Semiconductor Components Industries, LLC, 2013
September, 2013 − Rev. 5
1 Publication Order Number:
NSS35200MR6/D
NSS35200MR6T1G
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation
T
= 25°C
A
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient
Total Device Dissipation
T
= 25°C
A
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient
Thermal Resistance,
Junction−to−Lead #1
Total Device Dissipation
(Single Pulse < 10 sec.)
Junction and Storage Temperature Range TJ, T
1. FR− 4 @ Minimum Pad.
2. FR− 4 @ 1.0 X 1.0 inch Pad.
3. Refer to Figure 8.
PD (Note 1)
R
q
JA
PD (Note 2)
R
q
JA
P
(Notes 2 & 3) 1.75
(Note 1)
(Note 2)
R
q
JL
Dsingle
stg
625
5.0
mW
mW/°C
°C/W
200
1.0
8.0
W
mW/°C
°C/W
120
°C/W
80
W
−55 to +150 °C
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2
NSS35200MR6T1G
ELECTRICAL CHARACTERISTICS (T
Characteristic
= 25°C unless otherwise noted)
A
Symbol Min Typical Max Unit
OFF CHARACTERISTICS
Collector−Emitter Breakdown Voltage
(I
= −10 mAdc, IB = 0)
C
Collector−Base Breakdown Voltage
(I
= −0.1 mAdc, IE = 0)
C
Emitter−Base Breakdown Voltage
(I
= −0.1 mAdc, IC = 0)
E
Collector Cutoff Current
(VCB = −35 Vdc, IE = 0)
Collector−Emitter Cutoff Current
(V
= −35 Vdc)
CES
Emitter Cutoff Current
(V
= −4.0 Vdc)
EB
V
(BR)CEO
V
(BR)CBO
V
(BR)EBO
I
CBO
I
CES
I
EBO
−35 −45 −
−55 −65 −
−5.0 −7.0 −
− −0.03 −0.1
− −0.03 −0.1
− −0.01 −0.1
ON CHARACTERISTICS
DC Current Gain (Note 4)
(I
= −1.0 A, VCE = −1.5 V)
C
(IC = −1.5 A, VCE = −1.5 V)
(IC = −2.0 A, VCE = −3.0 V)
Collector−Emitter Saturation Voltage (Note 4)
(I
= −0.8 A, IB = −0.008 A)
C
(IC = −1.2 A, IB = −0.012 A)
(IC = −2.0 A, IB = −0.02 A)
Base −Emitter Saturation Voltage (Note 4)
(I
= −1.2 A, IB = −0.012 A)
C
Base −Emitter Turn−on Voltage (Note 4)
(I
= −2.0 A, VCE = −3.0 V)
C
Cutoff Frequency
(I
= −100 mA, VCE = −5.0 V, f = 100 MHz)
C
Input Capacitance (VEB = −0.5 V, f = 1.0 MHz) Cibo − 600 650 pF
Output Capacitance (VCB = −3.0 V, f = 1.0 MHz) Cobo − 85 100 pF
Turn−on Time (VCC = −10 V, IB1 = −100 mA, IC = −1 A, RL = 3 W)
Turn−off Time (VCC = −10 V, IB1 = IB2 = −100 mA, IC = 1 A, RL = 3 W)
4. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle ≤ 2%.
h
V
CE(sat)
V
BE(sat)
V
BE(on)
FE
100
100
100
−
−
−
200
200
200
−0.125
−0.175
−0.260
−
400
−
−0.15
−0.20
−0.31
− −0.68 −0.85
− −0.81 −0.875
f
T
t
on
t
off
100 − −
− 35 − nS
− 225 − nS
Vdc
Vdc
Vdc
mAdc
mAdc
mAdc
V
V
V
MHz
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3
NSS35200MR6T1G
1
IC/IB = 100
0.1
, COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
CE(sat)
V
0.01
0.001 0.01 0.1 1 10
TA = −55°C
TA = 25°C
IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (AMPS)
TA = 150°C
Figure 1. Collector Emitter Saturation Voltage
versus Collector Current
1000
TA = 150°C
TA = 25°C
TA = −55°C
100
, DC CURRENT GAIN
FE
h
10
0.001 0.01 0.1 1 10
IC, COLLECTOR CURRENT (A)
VCE = 1.5 V
Figure 3. DC Current Gain versus
Collector Current
0.25
IC/IB = 50
0.20
0.15
0.10
, COLLECTOR−EMITTER
0.05
SATURATION VOLTAGE (V)
CE(sat)
V
0
0.01
0.1 1.00.001
Figure 2. Collector Emitter Saturation Voltage
versus Collector Current
1.1
1
0.9
0.8
0.7
0.6
0.5
, BASE−EMITTER
0.4
0.3
BE(sat)
V
0.2
SATURATION VOLTAGE (V)
0.1
TA = −55°C
TA = 25°C
TA = 150°C
0
0.001 0.01 0.1 1 10
I
, COLLECTOR CURRENT (A)
C
Figure 4. Base Emitter Saturation Voltage
versus Collector Current
100°C
25°C
−55°C
IC/IB = 100
1.2
VCE = 3 V
1.1
1
0.9
TA = −55°C
0.8
0.7
TA = 25°C
0.6
0.5
0.4
, BASE−EMITTER ON VOLTAGE (V)
BE(ON)
V
TA = 150°C
0.3
0.2
0.001 0.01 0.1 1 10
IC, COLLECTOR CURRENT (A) VR, REVERSE VOLTAGE (V)
Figure 5. Base Emitter Turn−On Voltage
versus Collector Current
1000
100
C, CAPACITANCE (pF)
10
0.1 1 10
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4
C
ibo
C
obo
Figure 6. Capacitance
NSS35200MR6T1G
1.0
0.1
RESISTANCE
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
10
1.0
0.1
, COLLECTOR CURRENT (AMPS)
C
I
SINGLE PULSE AT T
0.01
0.1 1.0
1 ms10 ms100 ms1 s
DC
= 25°C
amb
10 100
V
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
CE
Figure 7. Safe Operating Area
100 ms
r(t), NORMALIZED TRANSIENT THERMAL
0.001
SINGLE PULSE
0.00001 0.01 0.1 1.0
0.0001 0.001
t, TIME (sec)
Figure 8. Normalized Thermal Response
10
100 1000
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
D
456
E1
NOTE 5
0.05
A1
23
1
e
E
b
A
DETAIL Z
c
CASE 318G−02
H
L
M
DETAIL Z
TSOP−6
ISSUE V
L2
GAUGE
PLANE
SEATING
C
PLANE
DATE 12 JUN 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
DIMAMIN NOM MAX
A1 0.01 0.06 0.10
b 0.25 0.38 0.50
c 0.10 0.18 0.26
D 2.90 3.00 3.10
E 2.50 2.75 3.00
E1
e 0.85 0.95 1.05
L 0.20 0.40 0.60
L2
M
MILLIMETERS
0.90 1.00 1.10
1.30 1.50 1.70
0.25 BSC
0° 10°
−
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
3.20
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
6X
0.95
0.95
PITCH
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
GENERIC
MARKING DIAGRAM*
XXXAYWG
G
1
XXX = Specific Device Code
A =Assembly Location
Y = Year
XXX = Specific Device Code
M = Date Code
G = Pb−Free Package
W = Work Week
G = Pb−Free Package
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
XXX MG
G
1
STANDARDIC
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