ON Semiconductor NSP4201MR6 User Manual

NSP4201MR6

ESD and Surge Protection
Device

Low Clamping Voltage Surge Protection
Diode Array

The NSP4201MR6 surge protector is designed to protect high speed

data lines from ESD, EFT, and lightning surges.

Features

• Protection for the Following IEC Standards:

IEC 61000−4−2 (ESD) ±30 kV (Contact)
IEC 61000−4−5 (Lightning) 25 A (8/20 ms)

• Low Clamping Voltage

• Low Leakage

• UL Flammability Rating of 94 V−0

• SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

• High Speed Communication Line Protection

• USB 1.1 and 2.0 Power and Data Line Protection

• Digital Video Interface (DVI)

• Monitors and Flat Panel Displays

MAXIMUM RATINGS (T

Rating

Peak Power Dissipation
8/20 ms @ T

Operating Junction Temperature Range T
Storage Temperature Range T
Lead Solder Temperature −

Maximum (10 Seconds)
IEC 61000−4−2 Air (ESD)

IEC 61000−4−2 Contact (ESD)
IEC 61000−4−4 (5/50 ns) EFT 40 A

Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.

1. Non−repetitive current pulse per Figure 1 (Pin 5 to Pin 2)

= 25°C (Note 1)

A

See Application Note AND8308/D for further description of
survivability specs.

= 25°C unless otherwise noted)

J

Symbol Value Unit

P

pk

J

stg

T

L

ESD ±30

500 W

−40 to +125 °C

−55 to +150 °C

260 °C

kV

±30

www.onsemi.com

6

1

TSOP−6

CASE 318G

MARKING DIAGRAM

42 MG

G

42 = Specific Device Code
M = Date Code
G = Pb−Free Package

(Note: Microdot may be in either location)

*Date Code orientation may vary

depending upon manufacturing location.

PIN CONFIGURATION AND SCHEMATIC

I/O 1

V

N

I/O 3

2

6 I/O

5 V

4 I/O

P

ORDERING INFORMATION

Device Package Shipping

NSP4201MR6T1G TSOP−6

(Pb−Free)

SZNSP4201MR6T1G TSOP−6

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

3000 / Tape &

Reel

3000 / Tape &

Reel

© Semiconductor Components Industries, LLC, 2017

June, 2017 − Rev. 1

1 Publication Order Number:

NSP4201MR6/D

NSP4201MR6

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

I
V

V

RWM

V

V

P

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

ELECTRICAL CHARACTERISTICS (T

Reverse Working Voltage V
Breakdown Voltage V
Reverse Leakage Current I
Clamping Voltage

= 8/20 ms per Figure 1)

(t

p

Junction Capacitance C
Junction Capacitance C

2. Surge protection devices are normally selected according to the working peak reverse voltage (V
than the DC or continuous peak operating voltage level.

3. V

Maximum Reverse Peak Pulse Current

PP

Clamping Voltage @ I

C

PP

Working Peak Reverse Voltage

I

Maximum Reverse Leakage Current @ V

R

Breakdown Voltage @ I

BR

I

Test Current

T

I

Forward Current

F

Forward Voltage @ I

F

Peak Power Dissipation

pk

T

F

C Capacitance @ VR = 0 and f = 1.0 MHz

=25°C unless otherwise specified)

J

Parameter

Symbol Conditions Min Typ Max Unit

RWM

V

(Note 2) 5.0 V
IT=1 mA, (Note 3) 6.0 V

BR

V

R

C

RWM

IPP = 1 A, Any I/O to GND 8.5
IPP = 5 A, Any I/O to GND 9.0
IPP = 8 A, Any I/O to GND 10
IPP = 25 A, Any I/O to GND 12
VR = 0 V, f=1 MHz between I/O Pins and GND 3.0 5.0 pF

J

VR = 0 V, f=1 MHz between I/O Pins 1.5 3.0 pF

J

is measured at pulse test current IT.

BR

V

VCV

RWM

BR

RWM

Uni−Directional Surge Protection

= 5 V 1.0

I

I

F

I

V

R

F

I

T

I

PP

), which should be equal or greater

RWM

V

mA

V

100

90
80
70
60
50

t

r

PEAK VALUE I

HALF VALUE I

@ 8 ms

RSM

PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms

/2 @ 20 ms

RSM

40
30
20

% OF PEAK PULSE CURRENT

10

0

t

P

020406080

t, TIME (ms)

Figure 1. IEC61000−4−5 8/20 ms Pulse Waveform

www.onsemi.com

20
18
16
14
12
10

I/O−GND

8
6
4

CLAMPING VOLTAGE (V)

2
0

05

10 15 20 25

PEAK PULSE CURRENT (A)

Figure 2. Clamping Voltage vs. Peak Pulse Current

(t

= 8/20 ms per Figure 1)

p

2

30

NSP4201MR6

100

80

60

40

VOLTAGE (V)

20

0

−20

−20 0 20 40 60 80 100 120 140
TIME (ns)

Figure 3. IEC61000−4−2 +8 kV Contact Clamping

Voltage

IEC 61000−4−2 Spec.

Test Volt-

Level

age (kV)

1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8

First Peak

Current

(A)

Current at

30 ns (A)

Current at

60 ns (A)

20

0

−20

−40

VOLTAGE (V)

−60

−80

−100

−20 0 20 40 60 80 100 120 140
TIME (ns)

Figure 4. IEC61000−4−2 −8 kV Contact Clamping

Voltage

IEC61000−4−2 Waveform

I

peak

100%

90%

I @ 30 ns

I @ 60 ns

Figure 5. IEC61000−4−2 Spec

ESD Gun

Surge Protection

Oscilloscope

50 W

Cable

Figure 6. Diagram of ESD Test Setup

The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger

10%

tP = 0.7 ns to 1 ns

50 W

systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.

www.onsemi.com

3