ON Semiconductor NLA9306 User Manual

Voltage-Level Translator,

Dual Bidirectional I

C-bus

and SMBus

NLA9306

The NLA9306 is a dual bidirectional I2C−bus and SMBus

voltage−level translator with an enable (EN) input.

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Features

• 2−bit Bidirectional Translator for SDA and SCL Lines in

Mixed−Mode I

• Standard−Mode, Fast−Mode, and Fast−Mode Plus I

C−Bus Applications

C−Bus and

SMBus Compatible

• Less Than 1.5 ns Maximum Propagation Delay to Accommodate

Standard−Mode and Fast−Mode I

C−Bus Devices and Multiple

Masters

• Allows Voltage Level Translation Between:

♦ 1.0 V V

1.2 V V

♦

1.8 V V

2.5 V V

♦

3.3 V V

♦

and 1.8 V, 2.5 V, 3.3 V or 5 V V

ref(1)

and 1.8 V, 2.5 V, 3.3 V or 5 V V

ref(1)

and 3.3 V or 5 V V

ref(1)

and 5 V V and 5 V V

bias(ref)(2)

• Provides Bidirectional Voltage Translation With No Direction Pin

• Low 3.5 W ON−State Connection Between Input and Output Ports

Provides Less Signal Distortion

• Open−Drain I

• 5 V Tolerant I

C−Bus I/O Ports (SCL1, SDA1, SCL2 and SDA2)

C−Bus I/O Ports to Support Mixed−Mode Signal

Operation

• High−Impedance SCL1, SDA1, SCL2 and SDA2 Pins for

EN = LOW

• Lock−Up Free Operation

• Flow Through Pinout for Ease of Printed−Circuit Board Trace

Routing

• Packages Offered:

♦ US8, UQFN8, UDFN8

• ESD Performance: 2000 V Human Body Model

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

MARKING

DIAGRAMS

US8

US SUFFIX

CASE 493

UQFN8

XXXX = Specific Device Code A = Assembly Location L = Lot Code Y = Year W = Work Week M = Date Code G = Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.

MU SUFFIX

CASE 523AN

UDFN8

1.45 x 1.0

CASE 517BZ

XXXX ALYW

XX MG

X M

March, 2021 − Rev. 2

1 Publication Order Number:

NLA9306/D

NLA9306

Function Description

The NLA9306 is a dual bidirectional I2C−bus and SMBus voltage−level translator with an enable (EN) input, and is operational from 1.0 V to 3.6 V (V (V

bias(ref)(2)

) and 1.8 V to 5.5 V

ref(1)

The NLA9306 allows bidirectional voltage translations between 1.0 V and 5 V without the use of a direction pin. The low ON−state resistance (R

) of the switch allows

connections to be made with minimal propagation delay. When EN is HIGH, the translator switch is on, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high−impedance state exists between ports.

The NLA9306 is not a bus buffer that provides both level translation and physical capacitance isolation to either side of the bus when both sides are connected. The NLA9306 only isolates both sides when the device is disabled and provides voltage level translation when active.

The NLA9306 can be used to run two buses, one at 400 kHz operating frequency and the other at 100 kHz operating frequency. If the two buses are operating at different frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other bus is required. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the translator.

As with the standard I

C−bus system, pull−up resistors are

required to provide the logic HIGH levels on the translator’s

bus. The NLA9306 has a standard open−collector configuration of the I

C−bus. The size of these pull−up resistors depends on the system, but each side of the translator must have a pull−up resistor. The device is designed to work with Standard−mode, Fast−mode and Fast mode Plus I

C−bus devices in addition to SMBus devices. The maximum frequency is dependent on the RC time constant, but generally supports > 2 MHz.

When the SDA1 or SDA2 port is LOW, the clamp is in the ON−state and a low resistance connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on the SDA2 port, when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain pull−up supply voltage (V

) by the pull−up resistors.

pu(D)

This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel.

All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower voltage devices, and at the same time protects less ESD−resistant devices.

FUNCTIONAL DIAGRAM

VREF1

SCL1

Figure 1. Logic Diagram

VREF2

NLA9306

GND

SCL2

SDA2SDA1

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NLA9306

PIN ASSIGNMENTS

GND

VREF1

SCL1

SDA1

NLA9306

VREF2

SCL2

SDA2

GND

VREF1

SCL1

Figure 2. US8 Pinouts Figure 3. UQFN8 Pinout (Top Thru View)

NLA9306

SDA1

VREF2

SCL2

SDA2

Table 1. PIN DESCRIPTION

Pin Description

GND Ground

VREF1 Low−voltage side reference supply voltage for SCL1 and SDA1

SCL1 Serial clock, low−voltage side; connect to VREF1 through a pull−up resistor

SDA1 Serial data, low−voltage side; connect to VREF1 through a pull−up resistor

SDA2 Serial data, high−voltage side; connect to VREF2 through a pull−up resistor

SCL2 Serial clock, high−voltage side; connect to VREF2 through a pull−up resistor

VREF2 High−voltage side reference supply voltage for SCL2 and SDA2

EN Switch enable input; connect to VREF2 and pull−up through a high resistor

GND

VREF1

SCL1

VREF2

SCL2

SDA2SDA1

Figure 4. UDFN8 Pinout (Top Thru View)

Table 2. FUNCTION TABLE

Input EN (Note 1) Function

Low Disconnect

High SCL1 = SCL2; SDA1 = SDA2

1. EN is controlled by the V

bias(ref)(2)

logic levels and should be at least 1 V higher than V

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for best translator operation.

ref(1)

NLA9306

Table 3. MAXIMUM RATINGS

Symbol Parameter Value Unit

ref(1)

bias(ref)(2)

I/O

STG

MSL Moisture Sensitivity Level 1

ESD

LATCHUP

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.

3. Tested to ANSI / ESDA / JEDEC JS−001−2017.

4. JEDEC recommends that ESD qualification to EIA / JESD22−A115−A (Machine Model) be discontinued per JEDEC / JEP172A.

5. Tested to EIA / JESD22−C101−F.

6. Tested to EIA / JESD78 Class II.

Reference Voltage (Note 2) −0.5 to +7.0 V

Reference Bias Voltage (Note 3) −0.5 to +7.0 V

Input Voltage −0.5 to +7.0 V

Input / Output Pin Voltage −0.5 to +7.0 V

DC Channel Current 128 mA

DC Input Diode Current VIN < GND −50 mA

Storage Temperature Range −65 to +150 °C

Lead Temperature, 1 mm from Case for 10 Seconds TL = 260 °C

Junction Temperature Under Bias TJ = 150 °C

Thermal Resistance (Note 2)

qJA = 150

°C/W

Power Dissipation in Still Air at 85°C PD = 833 mW

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

ESD Withstand Voltage Human Body Mode (Note 3) Machine Model (Note 4) Charged Device Model (Note 5)

> 2000

N/A

> 1000

Latchup Performance Above VCC and Below GND at 125°C (Note 6) ±100 mA

Table 4. RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

ref(1)

bias(ref)(2)

I/O

I(EN)

sw(pass)

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

7. V

(ref)(1)

Reference Voltage (1) (Note 7) VREF1 0 5.5 V

Reference Bias Voltage (2) (Note 7) VREF2 0 5.5 V

Input / Output Pin Voltage SCL1, SDA1, SCL2, SDA2 0 5.5 V

Control Pin Input Voltage EN 0 5.5 V

Pass Switch Current 0 64 mA

Operating Free−Air Temperature −55 +125 °C

≤ V

bias(ref)(2)

−1 V for best results in level shifting applications.

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