N-Channel Logic Level
Enhancement Mode Field
Effect Transistor
NDS331N
General Description
These N−Channel logic level enhancement mode power field effect
transistors are produced using ON Semiconductor’s proprietary, high
cell density, DMOS technology. This very high density process is
especially tailored to minimize on−state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMCIA cards, and other battery
powered circuits where fast switching, and low in−line power loss are
needed in a very small outline surface mount package.
Features
• 1.3 A, 20 V
♦ R
♦ R
= 0.21 @ VGS = 2.7 V
DS(on)
= 0.16 @ VGS = 4.5 V
DS(on)
• Industry Standard Outline SOT−23 Surface Mount Package Using
Poprietary SUPERSOTt−3 Design for Superior Thermal and
Electrical Capabilities
• High Density Cell Design for Extremely Low R
DS(on)
• Exceptional On−Resistance and Maximum DC Current Capability
• This is a Pb−Free Device
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D
G
S
SOT−23/SUPERSOT−23, 3 LEAD, 1.4x2.9
CASE 527AG
MARKING DIAGRAM
&Y
331 &G
&Y= Binary Calendar Year Coding Scheme
331= Specific Device Code
&G= Date Code
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1Publication Order Number:
S
†
3000 /
Tape & Reel
NDS331N/D
NDS331N
ABSOLUTE MAXIMUM RATINGS T
Symbol
V
V
DSS
GSS
I
D
Drain−Source Voltage20V
Gate−Source Voltage − Continuous±8V
Maximum Drain Current – Continuous (Note 1a)1.3
= 25°C unless otherwise noted.
A
ParameterRatingsUnit
A
Maximum Drain Current – Pulsed10
P
Maximum Power Dissipation (Note 1a)0.5
D
W
Maximum Power Dissipation (Note 1b)0.46
TJ, T
Operating and Storage Temperature Range−55 to +150°C
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Forward TransconductanceVDS = 5 V, ID = 1.3 A−3.5−S
FS
DYNAMIC CHARACTERISTICS
C
C
C
Input Capacitance
iss
Output Capacitance−85−pF
oss
Reverse Transfer Capacitance−28−pF
rss
VDS = 10 V, VGS = 0 V, f = 1.0 MHz
−162−pF
SWITCHING CHARACTERISTICS (Note 2)
t
D(on)
t
t
D(off)
t
Q
Q
Q
Turn–On Delay Time
Turn–On Rise Time−2540ns
r
Turn–Off Delay Time−1020ns
Turn–Off Fall Time−520ns
f
Total Gate Charge
g
Gate–Source Charge−0.3−nC
gs
Gate–Drain Charge−1−nC
gd
VDD = 5 V, ID = 1 A, VGS = 5 V,
= 6
R
GEN
VDS = 5 V, ID = 1.3 A, VGS = 4.5 V
−520ns
−3.55nC
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain–Source Diode Forward Current−−0.42A
I
S
I
SM
V
Maximum Pulsed Drain−Source Diode Forward Current−−10A
Drain–Source Diode Forward Voltage VGS = 0 V, IS = 0.42 A (Note 2)−0.81.2V
SD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Figure 11. Switching Test CircuitFigure 12. Switching Waveforms
50%
90%
t
off
90%
10%
t
f
Inverted
5
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5
NDS331N
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
8
V
= 5.0 V
DS
6
TJ = −55°C
4
125°C
2
, Transconductance (Siemens)
FS
g
0
02
ID, Drain Current (A)
Figure 13. Transconductance Variation with Drain
Current and Temperature
1
0.8
0.6
1a
1b
0.4
0.2
Steady−State Power Dissipation (W)
0
00.2
2oz Copper Mounting Pad Area (in2)
4.5″x5″ FR−4 Board
= 25°C
T
A
Still Air
25°C
0.4
50
This Area is Limited by r
DS(on)
10
100 s
1 ms
1
10 ms
, Drain Current (A)
D
I
0.1
0.01
Single Pulse
= Max Rated
T
J
R
= 270°C/W
JA
T
= 25°C
A
Curve Bent to
Measured Date
40.111031
, Drain to Source Voltage (V)
V
DS
100 ms
60
Figure 14. Maximum Safe Operating Area
1.8
1.6
1.4
1a
1.2
1b
, Steady−State Drain Current (A)
D
I
1
00.10.20.30.30.1
2oz Copper Mounting Pad Area (in
4.5″x5″ FR−4 Board
= 25°C
T
A
Still Air
V
= 2.7 V
GS
2
)
0.4
Figure 15. SUPERSOT−3 Maximum Steady−State
Power Dissipation versus Copper Mounting Pad Area
2
1
0.1
0.01
, Normalized Thermal Impedance
JA
Z
0.001
10
Duty Cycle−Descending Order
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
−4
10
−3
10
−2
10
−1
t, Rectangular Pulse Duration (s)
Figure 17. Transient Thermal Response Curve
NOTE: Thermal characterization performed using the conditions described in
Note 1b. Response will change depending on the circuit board design.
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Figure 16. Maximum Steady−State Drain
Current versus Copper Mounting Pad Area
P
DM
t
1
t
NOTES:
Z
(t)= r(t) x R
JA
R
= 270°C/W
JA
Peak T
= PDM x Z
J
Duty Cycle, D = t1 / t
110100
6
2
JA
(t) + T
A
JA
2
1000
NDS331N
SUPERSOT is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23/SUPERSOTt−23, 3 LEAD, 1.4x2.9
CASE 527AG
ISSUE A
DATE 09 DEC 2019
GENERIC
MARKING DIAGRAM*
XXXMG
G
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
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