ON Semiconductor NCV7510 Technical data

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NCV7510

FlexMOS Programmable Peak and Hold PWM MOSFET Predriver

The NCV7510 high side MOSFET predriver is a fully programmable automotive grade product for driving solenoids or other unipolar actuators. The product is optimized for common−rail diesel fuel injection applications and includes an additional synchronous clamp MOSFET predriver. Peak and hold currents, peak dwell time and other features are programmable via the device’s SPI port. Load current is continuously sampled and compared to the programmable 7−bit peak/hold DAC values while the load self−modulates to maintain the desired currents at each of the peak and hold points. Passive fault diagnostics monitor and protect the MOSFET s when a fault is detected. Fault data is available via SPI and an open−drain FAULT output provides immediate fault notification to a host controller.

The FlexMOS family of products offers application scalability through choice of external MOSFETs.

Features

• 4 MHz 16−Bit SPI Communication

• 3.3 / 5.0 V Compatible Inputs

• Bootstrap for High Side MOSFET

• Synchronous Clamp Drive

• Cross Conduction Suppression

• Self−Protection

− Overcurrent and Overvoltage

− Antisaturation

• Fault Diagnostics

− Short to Battery/GND

− Open Circuit / Shorted Load

− Overvoltage

• Open−Drain FAULT Output

• Programmable

− Peak / Hold Current PWM Thresholds

− Overcurrent and Overvoltage

− Antisaturation Thresholds

− Peak Dwell Time

• NCV Prefix for Automotive and Other Applications Requiring Site

and Control Changes

Benefits

• Scalable by Choice of MOSFETs

• Reduced Load Power Consumption

• Low Host Controller Overhead

• Low Standby Current

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MARKING DIAGRAM

SO−20L DW SUFFIX CASE 751D

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

PIN CONNECTIONS

120

ENA

CONTROL

PCLK

CSB

SCLK

LOOP

FAULT

OCP

ORDERING INFORMATION

Device Package Shipping

NCV7510DW SO−20L 37 Units/Rail NCV7510DWR2 SO−20L

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

NCV7510

AWLYYWW

DRN GATE SRC CLAMP PGND SNS+ SNS− DGND

1000 Tape & Reel

†

 Semiconductor Components Industries, LLC, 2005

January, 2005 − Rev. 0

1 Publication Order Number

NCV7510/D

NCV7510

ENA

CONTROL

FAULT

CSB

SCLK

PCLK

LOOP

DRN

POROVSD

16−BIT

SPI

8−BIT

TIMER

DIAGNOSTICS

VREF

FET

DRIVE

CONTROL

FAULT

7−BIT

DAC

HYSTERETIC

MUX

CONTROL

CLAMP

DRIVE

GATE

DRIVE

ANTISAT

DETECTION

OVER

CURRENT

SENSE

AMP

CLAMP

GATE

SRC

OCP

SNS+

SNS−

Figure 1. Block Diagram

PGNDDGND

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SPI

HOST CONTROLLER

ENA

CONTROL

PCLK

CSB

SCLK

LOOP

FAULT

NCV7510

DRN

GATE

SRC

CLAMP

PGND

NCV7510

SNS+

SNS−

DGND

BAT

D2D3

RLIM

BOOT

NTD32N06

MMBZ9V1

NTD32N06

BULK2

D5 D6

FILTER

BULK1

INJECTOR 1

INJECTOR 2

INJECTOR 3

INJECTOR 4

RSNS

NTD32N06

OCP

VDD

RPU

Figure 2. Application Diagram

+5V

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NCV7510

PACKAGE PIN DESCRIPTIONS

PACKAGE PIN# PIN SYMBOL FUNCTION

1 ENA Logic input for Enable. 2 CONTROL Logic input for PWM cycle control. 3 PCLK Logic input for clock or logic level control of Dwell timer. 4 CSB Logic input for active low chip select. 5 SCLK SPI clock input. 6 SI SPI serial data input. 7 SO SPI serial data output. 8 LOOP Control loop state output.

9 FAULT Open−drain fault output. 10 OCP Overcurrent program input. 11 V 12 DGND Supply return; device substrate. 13 SNS− Current sense negative input. 14 SNS+ Current sense positive input. 15 PGND High current supply return; CLAMP antisaturation reference node. 16 CLAMP Clamp MOSFET gate drive output. 17 SRC HS and CLAMP MOSFET antisaturation diagnostic input. 18 GATE HS MOSFET gate drive output. 19 DRN HS MOSFET drain antisaturation / overvoltage diagnostic input. 20 V

Logic supply voltage input; CLAMP predriver voltage.

Bootstrapped GATE predriver voltage.

ENA

CONTROL

PCLK

CSB

SCLK

LOOP

FAULT

OCP

120

DRN GATE SRC CLAMP

PGND SNS+ SNS− DGND

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NCV7510

Pin Function Descriptions

ENA: CMOS input with hysteresis logically ANDed with the CONTROL input to command the predriver outputs. This input has an active pulldown current source.

CONTROL: CMOS input with hysteresis logically ANDed with the ENA input to command the predriver outputs. This input has an active pulldown current source.

PCLK: Buffered CMOS input with hysteresis. This input controls which DAC register pair is selected for load current comparison. The input is programmed via Auxiliary register ($01) bit D

to respond to a clock signal (AUX D3=0 default

at POR) or a logic level (AUX D3=1.) The pin presents a 12 pF maximum load to the controller.

CSB: CMOS input with hysteresis. This input is the active−low chip select input that enables serial data transfer between the host controller and the device. This input has an active pullup current source.

SCLK: Buffered CMOS input with hysteresis. This input is the synchronizing clock input for serial data transfer between the micro controller and the device. The pin presents a 12 pF maximum load to the controller.

SI: Buffered CMOS input with hysteresis. This pin is the data input to the device’s SPI shift register. Serial data received at this input is transferred from the host controller to the shift register under the control of the CSB and SCLK inputs. The pin presents a 12 pF maximum load to the controller. This input has an active pulldown current source.

SO: The CMOS compatible line driver at this pin is the data output from the device’s SPI shift register. Serial data transmitted at this output is transferred from the shift register to the host controller under the control of the CSB and SCLK inputs. The pin is capable of driving 200 pF at 4 MHz and is HI−Z when the CSB input is high.

LOOP: The CMOS compatible driver at this pin reflects the state of the control loop. A logic low indicates that load current is less than the programmed DAC reference.

FAULT: An open−drain low voltage NMOS output at this pin provides immediate fault indication to a connected host controller. An external resistor is normally connected between this pin and V

DGND: Device substrate voltage and VDD return path for mixed signal functions. This pin is the circuit common reference point.

OCP: This analog comparator input supplies a reference voltage to the device’s overcurrent fault detection. When the voltage at this pin is less than 4.5 V, the applied voltage is the overcurrent reference voltage. When the voltage is greater than 4.5 V, an internal 3.0 V overcurrent reference is used.

The voltage at this pin must not exceed V

. Applying

approximately VDD + 1.4 V will place the NCV7510 in test mode and suspend normal operation. The user is advised to avoid activating the test mode.

: +5.0 Vpower supply input. The voltage at this pin

initiates power−on reset, supplies power to internal mixed−signal functions and supplies gate charge to the external CLAMP MOSFET. A low ESR external bulk capacitor connected between VDD and PGND is recommended to supply transient gate charge. Several internal reference voltages are derived from V

SNS−: The inverting input to the analog current sense amplifier. This input should be Kelvin connected directly to the external current sense resistor’s negative terminal.

SNS+: The noninverting input to the analog current sense amplifier. This input should be Kelvin connected directly to the external current sense resistor’s positive terminal.

PGND: Return path for the GATE and CLAMP predriver transient currents and the lower input to the CLAMP antisaturation detection comparator. This pin should be star−connected to the CLAMP MOSFET’s source and the external V

bulk charge capacitor’s negative terminal.

CLAMP: External CLAMP MOSFET predrive output. This output switches the CLAMP MOSFET’s gate between V

and PGND.

SRC: Lower input to the GATE antisaturation detection comparator and upper input to the CLAMP antisaturation detector.

GATE: External HS MOSFET predrive output. This output switches the HS MOSFET’s gate between V

and PGND.

DRN: Upper input to the GATE antisaturation detection comparator, overvoltage detection input, and powerup interlock input. This pin should be connected directly to the HS MOSFET’s drain terminal.

VB: Bootstrap or boost input voltage. This input supplies gate charge to the external HS MOSFET.

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NCV7510

MAXIMUM RATINGS (Voltages are with respect to device substrate.)

Rating

DC Supply Voltage (Note 1)

VDRN Peak Transient Voltage (Note 2) VDRN VB Pin Voltage V GATE Pin Voltage V VB to GATE Differential Voltage VB − V SRC Pin Voltage V Logic Level Input/Output Voltage

(SO, SI, SCLK, CSB, ENA, CONTROL, PCLK, FAULT, LOOP) Sense Amplifier Input Voltage

Overcurrent Comparator Input Voltage V Junction Temperature Tj 150 °C Storage Temperature Range T Peak Reflow Soldering Temperature: Lead−free (60 to 150 seconds at 217 °C) (Note 3) 265 peak °C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. Reverse VDRN protection must be included in the application circuit.

2. VDRN transient voltage suppression must be included in the application circuit.

3. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D, and Application Note AND8003/D.

Symbol Value Unit

VDRN −0.3 to 45 V

V V

GATE

SRC

I/O

SNS+ SNS−

OCP

stg

(PK)

GATE

−0.3 to 7.0 V 45 V

−2.0 to 50 V

−2.0 to 50 V 50 V

−2.0 to 45 V

−0.3 to 7.0 V

−0.3 to 45 V

−0.3 to 7.0 V

−65 to 150 °C

ATTRIBUTES

Characteristic Value Unit

ESD Capability (All Pins) Human Body Model Charged Device Model

Moisture Sensitivity (Note 3) MSL 1 Package Thermal Resistance

Junction–to–Ambient, R Junction–to–Case, R



> 3.0 > 1.0

9.0

kV kV

°C/W °C/W

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NCV7510

ELECTRICAL CHARACTERISTICS (5 V < V

)

(Note 4

< 26 V, 4.75 V < VDD < 5.25 V, −40°C < TJ < 125°C, unless otherwise specified.)

DRN

Characteristic Conditions Min Typ Max Unit

DRN Input

Input Current

= 12.8 V, VDD = 0 V

DRN

= 26 V, VDD =5.25 V

DRN

– –

0.5

−

5.0

2.0

A

Power−On Lockout Threshold VDD = 0 V, GATE predriver locked out – 0.7 1.5 V Over−Voltage Lockout GATE predriver disabled, CLAMP predriver active

28 32 36 V

Auxiliary Register Bit 6 = 1

Over−Voltage Hysteresis 0.1 0.8 2.0 V

VB Input

Input Bias Current

= 24 V – 0.7 1.5 mA

VDD Supply

Operating Current

= 14 V 3.5 7.0 mA

DRN

Power−On Reset Threshold Predrivers disabled, VDD rising 3.0 3.5 4.4 V Power−On Reset Hysteresis − 0.25 − V

Digital I/O

High ENA, CONTROL, SI, SCLK, CSB, PCLK 2.2 – – V

VIN Low ENA, CONTROL, SI, SCLK, CSB, PCLK – – 0.8 V VIN Hysteresis ENA, CONTROL, SI, SCLK, CSB, PCLK 0.6 1.2 V Input Pulldown Current ENA, CONTROL, SI: V Input Pullup Current CSB: V SO Low Voltage I SO High Voltage I LOOP Low Voltage I LOOP High Voltage I LOOP Output Response Delay

(See Figure 3)

SINK SOURCE SINK SOURCE

LOOP(HL)

LOOP(LH)

FAULT Low Voltage FAULT Active, I

= 0 V −25 – – A

= 1 mA – – 0.4 V

= 1 mA V

= 0.1 mA – – 0.5 V

= 0.1 mA V ; C

LOOP

; C

LOOP

FAULT

= V

= 50 pF

= 0.5 mA – 0.1 0.5 V

– – 25 A

− 1.0 – – V

– –

0.5

1.2

s s

PCLK Input

Input Capacitance

(Note 5) – – 12 pF Clock Frequency Auxiliary Register Bit 3 = 0 (Note 5) 0 – 20 MHz DAC Reference Select Delay Auxiliary Register Bit 3 = 1 (Note 5) – – 3.0 s

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