ON Semiconductor NCV7380 Technical data

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NCV7380

Advance Information

LIN Transceiver

The NCV7380 is a physical layer device for a single wire data link capable of operating in applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor which uses the network. The NCV7380 is designed to work in systems developed for LIN 1.3 or LIN 2.0. The IC furthermore can be used in ISO9141 systems.

Because of the very low current consumption of the NCV7380 in recessive state, it’s suitable for ECU applications with low standby current requirements, whereby no sleep/wake−up control from the microprocessor is necessary.

Features

• Operating Voltage V

• Low Current Consumption of Typ. 24 A

• LIN−Bus Transceiver:

♦ Slew Rate Control for Good EMC Behavior ♦ Fully Integrated Receiver Filter ♦ BUS Input Voltage −27 V to 40 V ♦ Integrated Termination Resistor for LIN Slave Nodes (30 k) ♦ Baud Rate up to 20 kBaud ♦ Will Work in Systems Designed for either LIN 1.3 or LIN 2.0

• Compatible to ISO9141 Functions

• High EMI Immunity

• Bus Terminals Protect Against Short−Circuits and Transients in the

Automotive Environment

• Bus Pin High Impedance During Loss of Ground and Undervoltage

Conditions

• Thermal Overload Protection

• High Signal Symmetry for use in RC–Based Slave Nodes up to 2%

Clock Tolerance when Compared to the Master Node

• 4.0 kV ESD Protection on all Pins

• NCV Prefix for Automotive and Other Applications Requiring Site

and Change Control

= 6.0 to 18 V

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MARKING DIAGRAM

RxD

VCC

TxD

ORDERING INFORMATION

Device Package Shipping†

NCV7380D SO−8 95 Units/Rail NCV7380DR2 SO−8 2500 Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

SO−8

D SUFFIX

CASE 751

A = Assembly Location L = Wafer Lot Y = Year W = Work Week

PIN CONNECTIONS

18 2 3 4

(Top View)

V7380 ALYW

VS BUS

GND

This document contains information on a new product. Specifications and information herein are subject to change without notice.

 Semiconductor Components Industries, LLC, 2004

May, 2004 − Rev. P3

1 Publication Order Number:

NCV7380/D

NCV7380

VCC

TxD

RxD

Internal Supply

and

References

POR

15 K

Biasing &

Bandgap

SLEW RATE

CONTROL

Receive

Comparator

Thermal

Shutdown

30 K

BUS Driver

BUS

GND

Input Filter

Figure 1. Block Diagram

P ACKAGE PIN DESCRIPTION

Pin Symbol Description

1 RXD Receive data from BUS to microprocessor, LOW in dominant state. 2 NC No connection. 3 VCC 5.0 V supply input. 4 TXD Transmit data from microprocessor to BUS, LOW in dominant state. 5 GND Ground 6 BUS LIN bus pin, LOW in dominant state. 7 VS Battery input voltage. 8 NC No connection.

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NCV7380

Electrical Specification

All voltages are referenced to ground (GND). Positive currents flow into the IC.

The maximum ratings given in the table below are limiting values that do not lead to a permanent damage of

OPERATING CONDITIONS

Characteristic Symbol Min Max Unit

Battery Supply Voltage (Note 1) V Supply Voltage V Operating Ambient Temperature T

MAXIMUM RATINGS

Rating Symbol Condition Min Max Unit

Battery Supply Voltage V

Supply Voltage V Transient Supply Voltage V Transient Supply Voltage V Transient Supply Voltage V BUS Voltage V

Transient Bus Voltage V Transient Bus Voltage V Transient Bus Voltage V DC Voltage on Pins TxD, RxD V ESD Capability of Any Pin V

Maximum Latch−Up Free Current at Any Pin I Maximum Power Dissipation P Thermal Impedance  Storage Temperature T Junction Temperature T Lead Temperature Soldering

Reflow: (SMD styles only)

1. VS is the IC supply voltage including voltage drop of reverse battery protection diode, V

18 V .

2. ISO 7637 test pulses are applied to VS via a reverse polarity diode and > 2.0 F blocking capacitor.

3. ISO 7637 test pulses are applied to BUS via a coupling capacitance of 1.0 nF.

S.tr1 S..tr2 S..tr3

BUS

BUS..tr1

BUS.tr2 BUS.tr3

ESDHB

LATCH

tot JA stg

sld

the device but exceeding any of these limits may do so. Long term exposure to limiting values may effect the reliability of the device.

t < 1 min Load Dump, t < 500 ms

− −0.3 +7.0 V ISO 7637/1 Pulse 1 (Note 2) −150 − V ISO 7637/1 Pulses 2 (Note 2) − 100 V ISO 7637/1 Pulses 3A, 3B −150 150 V t < 500 ms , Vs = 18 V −27 t < 500 ms ,Vs = 0 V −40 ISO 7637/1 Pulse 1 (Note 3) −150 − V ISO 7637/1 Pulses 2 (Note 3) − 100 V ISO 7637/1 Pulses 3A, 3B (Note 3) −150 150 V

− −0.3 7.0 V Human body model, equivalent to

discharge 100 pF with 1.5 k

− −500 500 mA At TA = 125°C − 197 mW In Free Air − 152 °C/W

− −55 +150 °C

− −40 +150 °C 60 second maximum above 183°C

−5°C/+0°C allowable conditions

DROP

6.0 18 V

4.5 5.5 V

−40 +125 °C

= 0.4 to 1.0 V , V

−0.3 40

−4.0 4.0 kV

− 240 peak °C

voltage range is 7.0 to

BAT_ECU

30 V

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NCV7380

ELECTRICAL CHARACTERISTICS (V

= 6.0 to 18 V , V

= 4.5 to 5.5 V and T

= −40 to 125°C unless otherwise noted.)

Characteristic Symbol Condition Min Typ Max Unit

GENERAL

Undervoltage Lockout V

Supply Current, Dominant I Supply Current, Dominant I Supply Current, Recessive I Supply Current, Recessive I Supply Current, Recessive I

Sr +

CC_UV

CCd

CCr

VS > 6.0 V, TxD = L, EN = H 2.75 − 4.3 V VS = 18 V , VCC = 5.5 V , TxD = L − 1.0 3.0 mA VS = 18 V , VCC = 5.5 V , TxD = L − 0.8 1.5 mA VS = 18 V , VCC = 5.5 V , TxD = Open − 10 20 A V

= 18 V , VCC = 5.5 V , TxD = Open − 14 30 A

= 12 V , VCC = 5.0 V , TxD = Open,

= 25°

− 24 − A

Thermal Shutdown Tsd (Note 4) − 155 − 180 °C Thermal Recovery T

(Note 4) − 126 140 150 °C

hys

BUS − Transmit

Short Circuit Bus Current I

BUS_LIM

= VS, Driver On − 120 200 mA

BUS

(Notes 5 and 6)

Pull Up Current Bus I

BUS_PU

BUS

= 0, V

= 12 V, Driver Off −600 − −200 A

(Notes 5 and 6)

Bus Reverse Current,

Recessive

Bus Reverse Current Loss of

Battery

Bus Current During Loss of

Ground Transmitter Dominant V oltage V Transmitter Dominant V oltage V

BUS_PAS_rec

(Notes 5 and 6)

BUS_LOG

(Notes 5 and 6)

BUS_LOG

(Notes 5 and 6)

BUSdom_DRV_1 BUSdom_DRV_2

> VS, 6.0 V < V

BUS

Driver Off

= 0 V , 0 V < V

= 12 V , 0 < V

BUS

Load = 40 mA − − 1.2 V V

= 6.0 V , Load = 500  − − 1.2 V

< 18 V ,

BUS

< 18 V − − 5.0 A

BUS

< 18 V −1.0 − 1.0 mA

− − 5.0 A

(Note 5)

Transmitter Dominant V oltage V

BUSdom_DRV_3

= 18 V , Load = 500  − − 2.0 V

(Note 5)

Bus Input Capacitance C

(Note 4) Pulse Response via 10 k

BUS

= 12 V , VS = Open

PULSE

− 25 35 pF

BUS − Receive

Receiver Dominant Voltage V

ilBUS

− 0.4 *V

− − V

(Notes 5 and 6)

Receiver Recessive Voltage V

ihBUS

− − − 0.6 *V

(Notes 5 and 6)

Center Point of Receiver

Threshold

(Notes 5 and 6)

Receiver Hysteresis V

BUS_CNT

iBUS_HYS

BUS_CNT

BUS_CNTt

= (V

ilBUS

ihBUS

and V

− V

)/2 0.487

ihBUS

) − 0.16 *V

ilBUS

0.5 *V

0.512

− V

(Notes 5 and 6)

4. No production test, guaranteed by design and qualification.

5. In accordance to LIN physical layer specification 1.3.

6. In accordance to LIN physical layer specification 2.0.

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NCV7380

ELECTRICAL CHARACTERISTICS (continued) (V

= 6.0 to 18 V, V

= 4.5 to 5.5 V and T

= −40 to 125°C unless otherwise noted.)

Characteristic Symbol Condition Min Typ Max Unit

TXD

High Level Input Voltage V Low Level Input Voltage V TxD Pull Up Resistor R

IH_TXD

Rising Edge − − 0.7*V Falling Edge 0.3*V V

= 0 V 10 15 20 k

TxD

− − V

RXD

Low Level Output Voltage V Leakage Current V

ol_rxd

leak_rxd

= 2.0 mA − − 0.9 V

RxD

= 5.5 V, Recessive −1.0 − 1.0 A

RxD

AC CHARACTERISTICS

Propagation Delay Transmitter

(Notes 9 and 11) Propagation Delay Transmitter Symmetry

trans_pdf

trans_pdr

trans_sym

Bus Loads: 1.0 K/1.0 nF,

660 /6.8 nF, 500 /10 nF

Calculate t

trans_pdf

− t

trans_pdr

− − 5.0 s

−2.0 − 2.0 s

(Notes 7 and 11) Propagation Delay Receiver

(Notes 7, 8, 9, 1 1 and 14) Propagation Delay Receiver Symmetry

rec_pdf

rec_pdr

rec_sym

= 20 pF − − 6.0 s

RxD

Calculate t

trans_pdf

− t

trans_pdr

−1.5 − 1.5 s

(Notes 7 and 8) Slew Rate Rising and Falling Edge,

High Battery (Notes 7 and 12)

SR_HB

Bus Loads: VS = 18 V ,

1.0 K/1.0 nF, 660 /6.8 nF,

1.0 2.0 3.0 V/s

500 /10 nF

Slew Rate Rising and Falling Edge,

Low Battery (Notes 7 and 12)

SR_LB

Bus Loads: VS = 7.0 V ,

1.0 K/1.0 nF, 660 /6.8 nF,

0.5 2.0 3.0 V/s

500 /10 nF

Slope Symmetry, High Battery

(Notes 7 and 12)

ssym_HB

Bus Loads: VS = 18 V ,

1.0 K/1.0 nF, 660 /6.8 nF,

−5.0 − 5.0 s

500 /10 nF, Calculate t

sdom−tsrec

Bus Duty Cycle (Notes 8 and 15) D1

Receiver Debounce Time

rec_deb

Calculate t Calculate t

BUS_rec(min) BUS_rec(max)

/100 s

0.396

−

0.581

BUS Rising and Falling Edge 1.5 − 4.0 s

(Notes 10, 13 and 14)

7. In accordance to LIN physical layer specification 1.3.

8. In accordance to LIN physical layer specification 2.0.

9. Propagation delays are not relevant for LIN protocol transmission, only symmetry.

10.No production test, guaranteed by design and qualification.

11.See Figure 2 − Input/Output Timing.

12.See Figure 7 − Slope Time Calculation.

13.See Figure 3 − Receiver Debouncing.

14.This parameter is tested by applying a square wave to the bus. The minimum slew rate for the bus rising and falling edges is 50 V/s.

15.See Figure 8 − Duty Cycle Measurement and Calculation.

s/s s/s

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