ON Semiconductor NCV7361A Technical data

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NCV7361A

Advance Information

Voltage Regulator with Integrated LIN Transceiver

The NCV7361A consists of a low drop voltage regulator,

5.0 V/50 mA and a LIN bus transceiver. The LIN transceiver is suitable for LIN bus systems compatible to “LIN−Protocol Specification” Rev. 1.3, 2.0 and SAE J2602.

The combination of voltage regulator and bus transceiver make it ideal for a powerful and inexpensive cost effective slave node in a LIN Bus system.

Features

• Operating Voltage V

• Very Low Standby Current Consumption < 110 A in Normal Mode

(< 50 A in Sleep Mode)

• LIN−Bus Transceiver:

♦ PNP−Bipolar Transistor Driver ♦ Slew Rate Control and Wave Shaping for Best EMC Behavior ♦ BUS Input Voltage −24 V to 30 V (Independent of V ♦ Wake−Up Via LIN Bus ♦ Baud Rate up to 20 kBaud ♦ Compatible to LIN Specification 1.3, 2.0 and SAE J2602 ♦ Compatible to ISO9141 Functions

• Wake−Up by LIN BUS and Startup Capable Independent of EN

Voltage Level

• Linear Low Drop Voltage Regulator:

♦ Output Voltage 5.0 V 2% ♦ Output Current Max. 50 mA ♦ Output Current Limit ♦ Overtemperature Shutdown

• Reset Time 100 ms and Reset Threshold Voltage 4.65 V

• CMOS Compatible Interface to Microcontroller

• Load Dump Protected (40 V Peak)

• Resistant Against Transient Pulses According to ISO 7637 at

Pin V

, BUS and EN

SUP

• NCV Prefix for Automotive and Other Applications Requiring Site

and Change Control

= 5.5 to 18 V

SUP

)

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MARKING DIAGRAM

8

1

V

SUP

EN

GND

BUS

ORDERING INFORMATION

Device Package Shipping

NCV7361AD SO−8 98 Units/Rail NCV7361ADR2 SO−8 2500 T ape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

SO−8

D SUFFIX

CASE 751

A = Assembly Location L = Wafer Lot Y = Year W = Work Week

PIN CONNECTIONS

18 2 3 4

(Top View)

7 6 5

7361A ALYW

1

V

OUT

RESET TxD RxD

†

This document contains information on a new product. Specifications and information herein are subject to change without notice.

 Semiconductor Components Industries, LLC, 2004

October, 2004 − Rev. P0

1 Publication Order Number:

NCV7361A/D

NCV7361A

V

SUP

EN

GND

BUS

Bandgap

Adjustment

V

SUP

Aux.

Supply

30 k

VBG

Mode

Control

Thermal

Protection

Slew Rate

Control

Amplifier

+

−

Receiver

Control

T

SHD

Current

Limitation

I

VAUX

POR UVR

Wake−Up

Control

Wake−

Filter

Rec−Filter

Driver

Control

V

OUT

MR

Reset

Generator

V

SUP

4.65 V

V

OUT

RESET Reset Timer

V

OSC

OUT

RxD

V

OUT

T

SHD

MR

Filter

TxD

MR = Master Reset T

= Thermal Shutdown

SHD

VBG = Bandgap V oltage

Figure 1. Block Diagram

P ACKAGE PIN DESCRIPTION

Pin Symbol Description

1 V

SUP

2 EN Enable input controls the regulator. Active high. 3 GND Ground 4 BUS LIN bus line. 5 RxD Receive output (push−pull to V 6 TxD Transmit input (pullup−input to V 7 RESET Reset output, active low (pullup to V 8 V

OUT

Supply voltage.

Regulator output 5.0 V/50 mA.

OUT

).

OUT

).

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2

NCV7361A

ELECTRICAL SPECIFICATIONS

All voltages are referenced to ground (GND). Positive

currents flow into the IC.

The maximum ratings (in accordance with IEC 134)

given in the table below are limiting values that do not lead

these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Correct operating of the device can’t be guaranteed if any of these limits are exceeded.

to a permanent damage of the device but exceeding any of

OPERATING CONDITIONS

Characteristic Symbol Min Max Unit

Supply Voltage V Operating Ambient Temperature T Junction Temperature T

SUP

A

J

MAXIMUM RATINGS

Rating Symbol Condition Min Max Unit

V

SUP

BUS V

Difference V

SUP−VOUT

EN V

TxD, RxD, RESET V

EN, TxD, RxD, RESET I Short Circuit of Pin V

SUP

and V

OUT

ESD Capability TxD Pin ESD ESD Capability on All Other Pins ESD Junction Temperature T Storage Temperature T Lead Temperature Soldering

Reflow: (SMD styles only)

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

V

SUP

BUS

V

SUP−VOUT

INEN

IN

I

INSH

BUSHB

J

STG

T

sld

− −1.0 30 V

T  500 ms − 40

− −24 30 V

T  500 ms − 40

− −0.3 40 V

− −0.3 V

− −25 25 mA

− −500 500 mA Human Body Model, 100 pF via 1.5 k −1.0 1.0 kV Human Body Model, 100 pF via 1.5 k −2.0 2.0 kV

HB

− − 150 °C

− −55 150 °C

60 second maximum above 183°C

−5°C/+0°C allowable conditions

5.25 18 V

−40 +125 °C

− +150 °C

+

SUP

0.3 +

OUT

0.3

− 240 peak °C

V

THERMAL RATINGS

Parameter Test Conditions Typical Value Units

SO−8 Package Min−Pad Board (Note 1) 1.0 in Pad Board (Note 2)

Junction−to−Tab (psi−JL2,  Junction−to−Ambient (R

) (Note 3) 48 43 °C/W

JL2

, JA) 183 120 °C/W

JA

1. 1 oz copper, 54 mm2 copper area, 0.062” thick FR4.

2. 1 oz copper, 714 mm2 copper area, 0.062” thick FR4.

3. psi−JL2 temperature was made at foot of lead #2.

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3

NCV7361A

ELECTRICAL CHARACTERISTICS (5.25 V  V

 18 V, −40°C  TA  125°C unless otherwise noted)

SUP

Characteristic Symbol Condition Min Typ Max Unit

V

SUP

Supply Current with V “No Load’’ (Note 4)

OUT

Supply Current, “Sleep Mode’’ I

Thermal Shutdown (Note 5) T Thermal Recovery (Note 5) T V

Undervoltage Reset “OFF” V

SUP

V

Undervoltage Reset “ON” V

SUP

V

Undervoltage Hysteresis V

SUP

Operating Voltage V

V

OUT

Output Voltage V

Drop−Out Voltage (Note 6) VD = V

SUP−VOUT

Output Current IV

Load Capacity C

I

Snl

Ssleep

JSHD

Jrec

SUVR_OFF

SUVR_ON

SUVR_HYS

SUP

OUTt

V

OUTh

V

OUTl

V

D

OUT

load

V

= V

EN

V

− 0.5 V , Pins 5 to 8 Open

SUP

V

= 12 V , VEN = 0 V , V

SUP

V

SUP

V

SUVR_OFF

5.5 V  V 0 < I

IV

= 20 mA, V

OUT

IV

= 50 mA, V

OUT

IV IV

3.0 V < V

Reference Figure 35 4.7 − − F

ENABLE (EN)

Input Voltage Low V Input Voltage High V

Hysteresis (Note 5) V Pulldown Current I

ENL ENH

ENHYS

pdEN

RESET

Output Voltage Low V

OL

I

= 1.0 mA, V

OUT

10 k RESET to V

V

SUP

Pullup Current I RESET Threshold V Master Reset Threshold (Note 5) V

pu

RES

MRes

Referred to V

4. See Figure 6 for test setup.

5. Not production tested, guaranteed by design and qualification.

6. Measured when the output voltage has dropped 100 mV from the V

SUP

= 12 V , V

− 0.5 V

BUS

>

− − 110 A

− 35 50 A

− 155 − 175 °C

− 126 − 130 °C

Ramp Up 3.1 3.5 3.9 V

SUP

Ramp Down 2.7 3.0 3.3 V

− V

SUVR_ON

0.2 − − V

5.25 12 18 V

 18 V

SUP

< 50 mA

OUT

V

> 18 V 4.90 5.0 5.25 V

SUP

= 3.3 V − V

SUP

= 3.3 V − V

SUP

= 20 mA − − 150 mV

OUT

= 50 mA − − 500 mV

OUT

< 18 V

SUP

V

= 0 V

OUT

4.90 5.0 5.10 V

SUP−VD SUP−VD

− V

50 − 150 mA

− −0.3 − 1.6 V

− 2.5 − V

SUP

+0.3

− 100 − − mV VEN > V VEN < V

= V

OUT

ENH ENL

> 5.5 V − − 0.8 V

SUP

OUT

= 0.8 V

1.0 4.0 7.0 A 70 100 130 A

− − 0.2 V

− −500 −375 −250 A , V

OUT

> 4.6 V 4.5 4.65 4.8 V

SUP

− 3.0 3.15 3.3 V

= 12 V nominal value.

SUP

V

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NCV7361A

ELECTRICAL CHARACTERISTICS (5.25 V  V

 18 V, −40°C  TA  125°C unless otherwise noted)

SUP

Characteristic Symbol Condition Min Typ Max Unit

LIN BUS INTERFACE

Receive Threshold V

Receive Center Point

V

thr_cnt

= (V

thr_rec

+ V

thr_dom

)/2

Receive Hysteresis

V

thr_hys

= V

thr_rec

− V

thr_dom

BUS Input Current (Recessive)

(Note 7) BUS Input Current (Recessive) −I BUS Input Current (Recessive) −I BUS Pullup Resistor R BUS Output Voltage (Dominant)

(Note 7) BUS Output Voltage (Recessive)

thr_rec

V

thr_dom

V

thr_cnt

V

thr_hys

I

INBUSR

INBUSR INBUSR

BUSpu

V

BUSdom

V

BUSrec

,

V

SUP

7.0 V  V

8.0  V

= V

V

SUP

V

SUP

BUS

= 0 V , V

= Open, V

 18 V

SUP

 18 V,

BUS

− 0.7 V, TxD = 4.5 V = −12 V −1.0 − − mA

BUS

= −18 V −1.0 − − mA

BUS

0.4 *V

0.475

*V

SUP

0.12 *V

SUP

− 0.6

0.5

*V

SUP

0.135

*V

SUP

*V

SUP

0.525

*V

SUP

0.15

*V

SUP

− − 20 A

V

− 20 30 47 k

7.0  V

 18 V, TxD = 0 V ,

SUP

RL = 500 

 18 V, TxD = 4.5 V 0.8 *V

SUP

− − 1.2 V

SUP

− − V

(Notes 7 and 8)

BUS Current Limit I

LIM

V

> 2.5 V, TxD = 0 V 40 − 120 mA

BUS

TxD

Pullup Resistance R

pu_TxD

Input Low Level V Input High Level V

IL

IH

− 9.5 15 21 k

− − − 1.25 V

− 3.75 − − V

RxD

Output Voltage Low V Output Voltage High V

OL OH

I

= 1.0 mA − − 0.8 V

OUT

I

= −1.0 mA 4.2 − − V

OUT

7. See Figures 7, 8, and 9 for test setup.

8. The recessive voltage on BUS should be less than 80% direct battery. The LIN protocol requires an external reverse battery diode between the battery and V

SUP

. V

SUP

= V

BAT

−0.7 V .

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5

NCV7361A

ELECTRICAL CHARACTERISTICS (7.0 V  V

 18 V, −40°C  TA  125°C unless otherwise noted)

SUP

Characteristic Symbol Condition Min Typ Max Unit

RESET AC CHARACTERISTICS

Reset Time t Reset Rise Time (Note 9) t BUS Debounce Time (Note 14) t Wake−Up Time t

Res

rr

deb_BUS

Wake_BUS

GENERAL LIN BUS INTERFACE AC CHARACTERISTICS

Transmit Propagation Delay TxD −> BUS (Notes 10 and 11 )

Symmetry of Propagation Delay BUS −> RxD (Note 10)

Receiver Propagation Delay BUS −> RxD (Notes 10 and 11)

Symmetry of Propagation Delay TxD −> BUS (Note 10)

Slew Rate BUS Rising Edge (Note 9) dV/dT

Slew Rate BUS Falling Edge (Note 9) dV/dT

t

dr_TxD

t

df_TxD

t

dsym_TxD

t

dr_RxD

t

df_RxD

t

dsym_RxD

,

rise

fall

LIN BUS PARAMETER ACCORDING T O LIN SPEC. REV. 1.3

Slope Time, Transition from Recessive to Dominant (Notes 11 and 12)

Slope Time, Transition from Dominant to Recessive (Notes 11 and 13)

Slope Time Symmetry t

Slope Time, Transition from Recessive to Dominant (Notes 11 and 12)

Slope Time, Transition from Dominant to Recessive (Notes 11 and 13)

Slope Time Symmetry t

t

sdom

t

srec

ssym

t

sdom

t

srec

ssym

9. Not production tested, guaranteed by design and qualification.

10.See Figures 2 and 3, Timing Diagrams.

11.See Figures 5, 6, 7, 8, and 9 for test setup.

12.t

= (t

sdom sdom

= (t

VBUS40% VBUS60%

13.t

14.See Figure 18.

− t

VBUS95%

− t

VBUS5%

) / 0.55.

5.25  V

RL/CL at BUS

1.0 k/1.0 nF 660 /6.8 nF

500 /10 nF

t

dr_TxD

C

L(RxD)

t

dr_RxD

20%  V

C

= 1.0 nF, R

L

20%  V

C

= 1.0 nF, R

L

V

R

= 500 /C

L

V

R

= 500 /C

L

V

R

= 500 /C

L

T

ssym

V

R

= 500 /C

L

V

R

= 500 /C

L

V

R

= 500 /C

L

T

ssym

 18 V 70 100 140 ms

SUP

 18 V 3.0 7.5 15 s

SUP

− 1.5 2.8 4.0 s

− 25 60 120 s

− − 4.0 s

− t

df_TxD

−2.0 − 2.0 s

= 50 pF − − 6.0 s

SUP

= t

SUP

= t

− t

df_RxD

 80%

BUS

= 1.0 k

L

 80%

BUS

= 1.0 k

L

= 8.0 V

= 10 nF

L

= 8.0 V

= 10 nF

L

= 8.0 V

= 10 nF

L

− t

sdom

= 18 V

= 10 nF

L

= 18 V

= 10 nF

L

= 18 V

= 10 nF

L

− t

sdom

srec

−2.0 − 2.0 s

1.0 1.7 2.5 V/s

−2.5 −1.7 −1.0 V/s

− − 12 s

−7.0 − 1.0 s

− − 18 s

−5.0 − 5.0 s

ELECTRICAL CHARACTERISTICS ( V

t

= 50 s, twH = TwL = t

Bit

; t

= t

Bit

< 100 ns, −40°C = TA = 125°C unless otherwise noted)

rise

fall

= 7.0 V to 18 V; BUS loads: 1.0 k / 1 nF; 660 / 6.8 nF; 500 / 10 nF, TxD Signal:

SUP

Characteristic Symbol Condition Min Typ Max Unit

LIN BUS PARAMETER ACCORDING T O LIN SPEC. REV. 2.0

Minimal Recessive Bit Time (Notes 15 and 16) t Maximum Recessive Bit Time (Notes 15 and 16) t

rec(min)

rec(max)

Duty Cycle 1 D Duty Cycle 2 D

15.See Timing Diagrams.

16.See Test Circuits for Dynamic and Static Characteristics.

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− 40 50 58 s

D1 = t

1

D2 = t

2

rec(min)

rec(max)

/ (2 * t

) 0.396 − −

Bit

) − − 0.581

Bit

6

NCV7361A

TIMING DIAGRAMS

TxD

BUS

RxD

V

BUS

50%

t

df_TxD

95%

100%

50%

0%

t

df_RxD

50%

Figure 2. Timing Diagram for Propagation Delay

According to LIN 1.3 and 2.0

5%

t

dr_TxD

t

dr_RxD

50%

BUS

V

BUS

100%

95%

60%

40%

5%

V

dom

t

srec

t

sdom

0%

Figure 3. Timing Diagram for Slope Times

According to LIN 1.3

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7

NCV7361A

V

SUP

BUS

V

TxD

SS

RxD

t

BIT

t

dom(max)

t

BIT

100%

t

dom(min)

74.4%

58.1%

42.2%

28.4%

0%

Figure 4. Timing Diagram for Duty Cycle According to LIN 2.0

TEST CIRCUITS

t

rec(min)

t

rec(max)

58.1%

28.4%

V

SUP

R

L

V

SUP

EN GND

BUS

V

OUT

RESET

TxD

RxD

10 F

+

50 pF

C

L

Figure 5. Test Circuit for Delay Time, Slope Time, and Duty Cycle

NCV7361A

V

SUP

EN GND

BUS

V

OUT

RESET

TxD

RxD

10 F

+

12 V

IS1

A

+

100 nF

Figure 6. T est Circuit for Supply Current I

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8

Snl

NCV7361A

TEST CIRCUITS (continued)

NCV7361A

V

BAT

V EN

SUP

V

OUT

RESET

10 F

+

100 nF

V

BUSREC

GND

BUS

TxD

RxD

Figure 7. Test Circuit for Bus Voltage “Recessive’’

(V

BUSREC

)

NCV7361A

V

SUP

V EN

SUP

V

OUT

RESET

500

GND

V

BUSD

V

BUS

TxD

RxD

Figure 8. T est Circuit for Bus Voltage “Dominant’’ V

NCV7361A

V

BAT

V EN

SUP

V

OUT

RESET

10 F

+

BUSDOM

+

100 nF

10 F 100 nF

I

INBUSR

A

Figure 9. Test Circuit for Bus Current “Recessive’’ I

13.5 V

Figure 10. T est Circuit for V

GND

BUS

TxD

RxD

INBUSR

NCV7361A

V

SUP

EN GND

BUS

Rise Time vs. Load Capacitance and Resistance

OUT

V

OUT

RESET

TxD

RxD

C

VAR

100 nF V

+

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9

V

R

L

OUT