The NCV7356 is a physical layer device for a single wire data link
capable of operating with various Carrier Sense Multiple Access
with Collision Resolution (CSMA/CR) protocols such as the Bosch
Controller Area Network (CAN) version 2.0. This serial data link
network is intended for use in applications where high data rate is not
required and a lower data rate can achieve cost reductions in both the
physical media components and in the microprocessor and/or
dedicated logic devices which use the network.
The network shall be able to operate in either the normal data rate
mode or a high−speed data download mode for assembly line and
service data transfer operations. The high−speed mode is only
intended to be operational when the bus is attached to an off−board
service node. This node shall provide temporary bus electrical loads
which facilitate higher speed operation. Such temporary loads should
be removed when not performing download operations.
The bit rate for normal communications is typically 33 kbit/s, for
high−speed transmissions like described above a typical bit rate of
83 kbit/s is recommended. The NCV7356 is designed in accordance
to the Single Wire CAN Physical Layer Specification GMW3089
V2.4 and supports many additional features like undervoltage
lockout, timeout for faulty blocked input signals, output blanking
time in case of bus ringing and a very low sleep mode current.
Features
• Fully Compatible with J2411 Single Wire CAN Specification
• 60 mA (max) Sleep Mode Current
• Operating Voltage Range 5.0 to 27 V
• Up to 100 kbps High−Speed Transmission Mode
• Up to 40 kbps Bus Speed
• Selective BUS Wake−Up
• Logic Inputs Compatible with 3.3 V and 5 V Supply Systems
• Control Pin for External Voltage Regulators (14 Pin Package Only)
• Standby to Sleep Mode Timeout
• Low RFI Due to Output Wave Shaping
• Fully Integrated Receiver Filter
• Bus Terminals Short−Circuit and Transient Proof
• Loss of Ground Protection
• Protection Against Load Dump, Jump Start
• Thermal Overload and Short Circuit Protection
• ESD Protection of 4.0 kV on CAN Pin (2.0 kV on Any Other Pin)
• Undervoltage Lock Out
• Bus Dominant Timeout Feature
• NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
• Pb−Free Packages are Available
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MARKING DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751
14
1
SOIC−14
D SUFFIX
CASE 751A
GNDGND
TxD
MODE1
RxDV
GNDGND
ORDERING INFORMATION
DevicePackageShipping
NCV7356D1GSOIC−8
NCV7356D1R2GSOIC−8
NCV7356D2SOIC−1455 Units / Rail
NCV7356D2R2SOIC−142500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
A= Assembly Location
WL, L= Wafer Lot
YY, Y= Year
WW, W = Work Week
G= Pb−Free Package
12TxDTransmit data from microprocessor to CAN.
23MODE0Operating mode select input 0.
34MODE1Operating mode select input 1.
45RxDReceive data from CAN to microprocessor.
510V
611LOADResistor load (loss of ground detection low side switch).
712CANHSingle wire CAN bus pin.
81, 7, 8, 14GNDGround
−6, 13NCNo Connection (Note 1)
−9INHControl pin for external voltage regulator (high voltage high side switch) (14 pin package only)
1. PWB terminal 13 can be connected to ground which will allow the board to be assembled with either the 8 pin package or the 14 pin package.
BAT
Battery input voltage.
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4
NCV7356
Electrical Specification
All voltages are referenced to ground (GND). Positive
currents flow into the IC. The maximum ratings given in
the table below are limiting values that do not lead to a
MAXIMUM RATINGS
RatingSymbolConditionMinMaxUnit
permanent damage of the device but exceeding any of these
limits may do so. Long term exposure to limiting values
may affect the reliability of the device.
Supply Voltage, Normal OperationV
Short−Term Supply Voltage, T ransientV
Transient Bus VoltageV
Transient Bus VoltageV
Transient Bus VoltageV
CANHTR1
CANHTR2
CANHTR3
DC Voltage on Pin LOADV
DC Voltage on Pins TxD, MODE1, MODE0, RxDV
ESD Capability of CANHV
ESDBUS
BAT.TR1
BAT.TR2
BAT.TR3
CANH
LOAD
DC
ISO 7637/1 Pulse 1 (Note 2)−50−V
ISO 7637/1 Pulses 2 (Note 2)−100V
ISO 7637/1 Pulses 3A, 3B−200200V
V
< 27 V−20
BAT
V
= 0 V−40
BAT
40
ISO 7637/1 Pulse 1 (Note 3)−50−V
ISO 7637/1 Pulses 2 (Note 3)−100V
ISO 7637/1 Pulses 3A, 3B (Note 3)−200200V
Via RT > 2.0 kW−4040V
−−0.37.0V
Human Body Model
−40004000V
V
Eq. to Discharge 100 pF with 1.5 kW
ESD Capability of Any Other PinsV
ESD
Human Body Model
−20002000V
Eq. to Discharge 100 pF with 1.5 kW
Maximum Latchup Free Current at Any PinI
LATCH
Storage TemperatureT
Junction TemperatureT
Lead Temperature Soldering
Reflow: (SMD styles only)
SOIC−14T
SOIC−860 s − 150 s above 217°C−260 peak
STG
sld
J
60 s − 150 s above 183°C−240 peak°C
−−500500mA
−−55150°C
−−40150°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
2. ISO 7637 test pulses are applied to V
3. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF.
via a reverse polarity diode and >1.0 mF blocking capacitor.
BAT
4. ESD measured per Q100−002 (EIA/JESD22−A114−A).
TYPICAL THERMAL CHARACTERISTICS
Parameter
SOIC−8
Junction−to−Lead (psi−JL7, Y
Junction−to−Ambient (R
q
SOIC−14
Junction−to−Lead (psi−JL8, Y
Junction−to−Ambient (R
Bus Falling Edge (Note 15)
Receive Delay, All Active Modes (Note 16)t
Receive Delay, All Active Modes (Note 16)t
Input Minimum Pulse Length,
All Active Modes (Note 16)
Wake−Up Filter Time Delayt
Receive Blanking Time
t
Tr
t
TWUr
t
Tf
t
TWU1f
t
THSr
t
THSf
DR
RD
t
mpDR
t
mpRD
WUF
t
rb
Min and Max Loads per Timing
2.0−6.3ms
Measurement Load Conditions
Min and Max Loads per Timing
2.0−18ms
Measurement Load Conditions
Min and Max Loads per Timing
1.8−10ms
Measurement Load Conditions
Min and Max Loads per Timing
3.0−13.7ms
Measurement Load Conditions
Min and Max Loads per Timing
0.1−1.5ms
Measurement Load Conditions
Min and Max Loads per Timing
0.04−3.0ms
Measurement Load Conditions
CANH High to Low Transition0.3−1.0ms
CANH Low to High Transition0.3−1.0ms
CANH High to Low Transition
CANH Low to High Transition
0.15
0.15
−
−
1.0
1.0
ms
See Figure 410−70ms
See Figure 50.5−6.0ms
After TxD L−H Transition
TxD Timeout Reaction Timet
TxD Timeout Reaction Timet
Delay from Normal to High−Speed and
tout
toutwu
t
dnhs
Normal and High−Speed Mode−17−ms
Wake−Up Mode−17−ms
−−−30ms
High Voltage W ake−Up Mode
Delay from High−Speed and High Voltage
t
dhsn
−−−30ms
Wake−Up to Normal Mode
Delay from Normal to Standby Modet
Delay from Sleep to Normal Modet
Delay from Standby to Sleep Mode (Note 17)t
dsby
dsnwu
dsleep
V
= 6.0 V to 27 V−−500ms
BAT
V
= 6.0 V to 27 V−−50ms
BAT
V
= 6.0 V to 27 V100250500ms
BAT
11.The maximum signal delay time for a bus rising edge is measured from Vcmos_il on the TxD input pin to the VihMax + Vgoff max level on CANH
at maximum network time constant, minimum signal delay time for a bus rising edge is measured from Vcmos_ih on the TxD input pin to 1 V
on CANH at minimum network time constant. These definitions are valid in both normal and High Voltage Wake−Up (HVWU) mode.
12.The maximum signal delay time for a bus rising edge in HVWU mode is measured from Vcmos_il on the TxD input pin to the VihWuMax + Vgoff
max level on CANH at maximum network time constant, minimum signal delay time for a bus rising edge is measured from Vcmos_ih on the
TxD input pin to 1 V on CANH at minimum network time constant.
13.Maximum signal delay time for a bus falling edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at maximum network time
constant, minimum signal delay time for a bus falling edge is measured from Vcmos_ih on the TxD input pin to the VihMax + Vgoff max level on
CANH. These definitions are valid in both normal and HVWU mode.
14.The signal delay time in high−speed mode for a bus rising edge is measured from Vcmos_il on the TxD input pin to the VihMax + Vgoff max level
on CANH at maximum high−speed network time constant.
15.The signal delay time in high−speed mode for a bus falling edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at maximum
high−speed network time constant.
16.Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling (Vcmos_il_max) / rising
(Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising
and falling edges is 50 V/ms. The low level on bus is always 0 V. For normal mode and high−speed mode testing the high level on bus is 4 V.
For HVWU mode testing the high level on bus is V
17.Tested on 14 Pin package only.
BAT
− 2 V .
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