ON Semiconductor NCV4279B Technical data

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NCV4279B
5.0 V Micropower 150 mA LDO Linear Regulator with DELAY, Adjustable RESET
,
and Monitor FLAG
The NCV4279B is a 5.0 V precision micropower voltage regulator.
The output current capability is 150 mA.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature drawing only 90 A with a 100 A load. This part is ideal for any and all battery operated microprocessor equipment.
Microprocessor control logic includes an active RESET DELAY), and a FLAG monitor which can be used to provide an early warning signal to the microprocessor of a potential impending RESET signal. The use of the FLAG monitor allows the microprocessor to finish any signal processing before the RESET shuts the microprocessor down.
The active RESET
circuit operates correctly at an output voltage as low as 1.0 V. The RESET function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits.
The reset threshold voltage can be decreased by the connection of
external resistor divider to R
ADJ
lead.
The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions.
Features
5.0 V ± 2.0% Output
Low 90 A Quiescent Current
Active RESET
Adjustable Reset
150 mA Output Current Capability
Fault Protection
+60 V Peak Transient Voltage
−15 V Reverse Voltage
Short Circuit
Thermal Overload
Early Warning through FLAG/MON Leads
Internally Fused Leads in SO−14 and SO−20L Packages
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
(with
8
14
20
SO−8
SO−14
SO−20L
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MARKING DIAGRAMS
SO−8
D SUFFIX
1
1
1
CASE 751
SO−14
D SUFFIX
CASE 751A
SO−20L DW SUFFIX CASE 751D
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week
PIN CONNECTIONS
18
V
IN
R
ADJ
114
ADJ
DELAY
NC
1
ADJ
DELAY
GND GND
NC
RESET
8
1
14
NCV4279B AWLYWW
1
20
NCV4279B
AWLYYWW
1
V
OUT
FLAGMON RESET GNDDELAY
MONR V
IN
GNDGND GNDGND GNDGND V
OUT
FLAGRESET
20
MONR V
IN
NCNC GNDGND GND GND GNDGND NCNC V
OUT
FLAG
4279B ALYW
Semiconductor Components Industries, LLC, 2003
August, 2003 − Rev. 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
1 Publication Order Number:
NCV4279B/D
NCV4279B
V
BAT
10 µF
C
DELAY
V
IN
NCV4279B
Delay
V
OUT
R
ADJ
MON
R
FLG
10 k
R
RST
10 k
10 µF
V
DD
Microprocessor
FLAG
RESET
GND
Figure 1. Application Diagram
MAXIMUM RATINGS*
V
(DC) −15 to 45 V
IN
Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) 60 V
Rating Value Unit
I/O
I/O
Operating Voltage 45 V V
(DC) 16 V
OUT
Voltage Range (RESET, FLAG) −0.3 to 10 V Input Voltage Range (MON) −0.3 to 10 V ESD Susceptibility (Human Body Model) 2.0 kV Junction Temperature, T Storage Temperature, T
J
S
−40 to +150 °C
−55 to 150 °C
Package Thermal Resistance, SO−8:
Junction−to−Case, R
θ
Junction−to−Ambient, R
JC
θ
JA
45
165
Package Thermal Resistance, SO−14 (Fused) Minimum Pad Data:
Junction−to−Case, R
θ
Junction−to−Ambient, R Junction−to−Pin, R
θ
JP
JC
θ
JA
(Note 3)
15
110
33
Package Thermal Resistance, SO−20L (Fused) Minimum Pad Data:
Junction−to−Case, R
θ
Junction−to−Ambient, R Junction−to−Pin, R
θ
JP
JC
θ
JA
(Note 4)
12 82 26
Lead Temperature Soldering: Reflow: (SMD styles only) (Notes 1, 2) 240 peak °C
1. 60 second maximum above 183°C.
2. −5°C/+0°C allowable conditions.
3. Measured to pin 9.
4. Measured to pin 12. *The maximum package power dissipation must be observed. †During the voltage range which exceeds the maximum tested voltage of V
Thermal dissipation must be observed closely.
, operation is assured, but not specified. Wider limits may apply.
IN
°C/W
°C/W
°C/W
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NCV4279B
ELECTRICAL CHARACTERISTICS (I
= 1.0 mA, −40°C ≤ T
OUT
125°C; 6.0 V < VIN < 26 V; unless otherwise specified.)
J
Characteristic Test Conditions Min Typ Max Unit
Output Stage
Output Voltage
Dropout Voltage (VIN − V
OUT
) I
9.0 V < VIN < 16 V, 100 A I
6.0 V < V
OUT
I
OUT
< 26 V, 100 A I
IN
= 150 mA
= 100 A Load Regulation VIN = 14 V, 5.0 mA I Line Regulation [V Quiescent Current, (IQ)
Active Mode
(typ) + 1.0] < VIN < 26 V, I
OUT
I
= 100 A, VIN = 12 V, Delay = 3.0 V, MON = 3.0 V
OUT
I
= 75 mA, VIN = 14 V, Delay = 3.0 V, MON = 3.0 V
OUT
150 mA, VIN = 14 V, Delay = 3.0 V, MON = 3.0 V
I
OUT
OUT
150 mA
OUT
150 mA
OUT
4.90
4.85
5.0
5.0
400 100
5.10
5.15 600
150
150 mA -30 5.0 30 mV
= 1.0 mA 15 60 mV
OUT
90
4.0 12
125
6.0 19
Current Limit 151 300 mA Short Circuit Output Current V
= 0 V 40 190 mA
OUT
Thermal Shutdown (Guaranteed by Design) 150 180 °C
Reset Function (RESET)
Threshold
RESET
HIGH (V LOW (V
RL
RH
)
)
V V
OUT OUT
Increasing Decreasing
4.55
4.50
4.70
4.60
0.98 × V
0.97 × V
OUT OUT
Output Voltage
Low (V
) 1.0 V V
RLO
OUT
VRL, R
= 10 k 0.1 0.4 V
RESET
Delay Switching Threshold (VDT) 1.4 1.8 2.2 V
V V
mV mV
A mA mA
V V
Reset Delay Low Voltage V Delay Charge Current DELAY = 1.0 V, V Delay Discharge Current DELAY = 1.0 V, V Reset Adjust Switching Voltage
(V
)
R(ADJ)
< RESET Threshold Low(min) 0.1 V
OUT
> V
OUT
RH
= 1.5 V 5.0 mA
OUT
1.5 2.5 3.5 A
1.23 1.31 1.39 V
FLAG/Monitor
Monitor Threshold
Increasing and Decreasing 1.10 1.20 1.31 V Hysteresis 20 50 100 mV Input Current MON = 2.0 V −0.5 0.1 0.5 A Output Saturation Voltage MON = 0 V, I
= 1.0 mA 0.1 0.4 V
FLAG
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PACKAGE PIN DESCRIPTION
Package Pin Number
NCV4279B
SO−8 SO−14 SO−20L
3 1 1 R
Pin Symbol Function
ADJ
Reset Adjust. If not needed connect to ground. 4 2 2 DELAY Timing capacitor for RESET function. 5 3−5, 10−12 4−7, 14−17 GND Ground. All GND leads must be connected to Ground
.
6 3, 8, 9, 13, 18 NC No connection. 6 7 10 RESET Active reset (accurate to V
OUT
1.0 V) 7 8 11 FLAG Open collector output from early warning comparator. 8 9 12 V 1 13 19 V
OUT
IN
±2.0%, 150 mA output. Input Voltage.
2 14 20 MON Monitor. Input for early warning comparator. If not needed connect to V
TYPICAL PERFORMANCE CHARACTERISTICS
(V)
OUT
V
5.01
5.00
4.99
V V I
OUT
OUT IN
= 5.0 V
= 14 V
= 5.0 mA
1.2
1.0
0.8
0.6
(mA)
Q
I
0.4
+125°C
+25°C
OUT.
VIN = 12 V
−40°C
0.2
4.98
−25 −10 1255 203550658095110
−40 Temperature (°C)
0
0
5 10152025
(mA)
I
OUT
Figure 2. Output Voltage vs. Temperature Figure 3. Quiescent Current vs. Output Current
14
VIN = 12 V
12
10
8
(mA)
Q
I
6
+125°C
+25°C
4
2
0
0
15 30 45 60 14075 90 105 120 135
(mA)
I
OUT
Figure 4. Quiescent Current vs. Output Current
−40°C
7
6
I
= 100 mA
5
OUT
4
(mA)
Q
I
3
I
= 50 mA
2
1
0
6
8101214 2616 18 20 22 24
OUT
I
OUT
V
IN
= 10 mA
(V)
Figure 5. Quiescent Current vs. Input Voltage
T = 25°C
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NCV4279B
TYPICAL PERFORMANCE CHARACTERISTICS
120
100
I
OUT
= 100 A
80
60
(µA)
Q
I
49
20
0
8101214 2616 18 20 22 24
6
(V)
V
IN
Figure 6. Quiescent Current vs. Input Voltage
1000
Unstable Region
100
T = 25°C
450 400 350 300 250 200
+125°C
+25°C
−40°C
150
Dropout Voltage (mV)
100
50
0
0
25 50 75 100 150
(mA)
I
OUT
Figure 7. Dropout Voltage vs. Output Current
1000
C
Unstable Region
100
10
Vout
= 10 F
C
Vout
125
= 0.1 F
ESR ()
10
Stable Region
C
= 10 F
1
Vout
0 10 20 30 40 50 60 70 80 90 100110120130140150
OUTPUT CURRENT (mA)
Figure 8. Output Capacitor ESR
ESR ()
1
Stable Region
0.1
0.01 0 102030 5060708090100110
40
OUTPUT CURRENT (mA)
Figure 9. Output Stability with Output
Capacitor Change
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NCV4279B
V
V
IN
Current Source
(Circuit Bias)
I
BIAS
Current Limit
Sense
OUT
R
ADJ
RESET
Delay
MON
+ +
V
BG
I
BIAS
+
− Error Amplifier
V
+
1.8 V
BG
Thermal
Protection
3.0 µA I
BIAS
Bandgap
Reference
V
BG
+
I
BIAS
V
BG
GND
FLAG
Figure 10. Block Diagram
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NCV4279B
CIRCUIT DESCRIPTION
REGULATOR CONTROL FUNCTIONS
The NCV4279B contains the microprocessor compatible
control function RESET (Figure 11).
V
IN
V
OUT
DELAY
RESET
T
d
T
d
RESET
Threshold
DELAY
Threshold
(V
DT
Figure 11. Reset and Delay Circuit Wave Forms
RESET Function
A RESET signal (low voltage) is generated as the IC powers up until V voltage, or when V
is within 6.0% of the regulated output
OUT
drops out of regulation,and is lower
OUT
than 8.0% below the regulated output voltage. Hysteresis is included in the function to minimize oscillations.
The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC thereby guaranteeing that the RESET
signal is valid for V
OUT
as low
as 1.0 V.
Adjustable Reset Function
The reset threshold can be made lower by connecting an external resistor divider to the R
lead from the V
ADJ
OUT
lead, as displayed in Figure 12. This lead is grounded to select the default value of 4.6 V.
DELAY Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
The DELAY lead provides source current (typically
2.5 A) to the external DELAY capacitor during the following proceedings:
1. During Power Up (once the regulation threshold has been verified).
2. After a reset event has occurred and the device is back in regulation. The DELAY capacitor is discharged when the regulation (RESET
)
has been violated. This is a latched incident. The capacitor will fully discharge and wait for the device to regulate before going through the delay time event again.
FLAG/Monitor Function
An on−chip comparator is provided to perform an early warning to the microprocessor of a possible reset signal. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with the microprocessor. The signal received from the FLAG will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the bandgap reference. The actual trip point can be programmed externally using a resistor divider to the input monitor (MON) (Figure 13). The typical threshold is 1.20 V on the MON Pin.
V
BAT
V
IN
MON
V
NCV4279B
FLAG
OUT
C
OUT
threshold)
V
CC
µP
I/O
pin
C
DELAY
V
OUT
RESET
R
ADJ
NCV4279B
Delay
Figure 12. Adjustable RESET
R
ADJ
to µP and System Power
C
R
RST
OUT
to µP and RESET Port
Figure 13. FLAG/Monitor Function
Delay
RESET
GND
RESET
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NCV4279B
APPLICATION NOTES
FLAG MONITOR
Figure 14 shows the FLAG Monitor waveforms as a result of the circuit depicted in Figure 13. As the output voltage falls (V
), the Monitor threshold is crossed. This causes
OUT
the voltage on the FLAG output to go low sending a warning signal to the microprocessor that a RESET signal may occur in a short period of time. T
WARNING
is the time the microprocessor has to complete the function it is currently working on and get ready for the RESET
V
OUT
MON
FLAG Monitor
Ref. Voltage
RESET
FLAG
T
WARNING
Figure 14. FLAG Monitor Circuit Waveform
shutdown signal.
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low Voltage, Delay Switching Threshold, and the Delay Charge Current. The delay follows the equation:
t
DELAY
[
C
DELAY(Vdt
Delay Charge Current
Reset Delay Low Voltage)
]
Example:
Using C
DELAY
= 33 nF. Assume reset Delay Low Voltage = 0. Use the typical value for V
= 1.8 V.
dt
Use the typical value for Delay Charge Current = 2.5 A.
t
DELAY
[
33 nF(1.80)
2.5 A
]
23.8 ms
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up delay , load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information.
The value for t he o utput c apacitor C
shown i n F igure 15
OUT
should work for most applications, however it is not necessarily the optimized solution.
V
IN
CIN*
0.1 F
*CIN required if regulator is located far from the power supply filter.
**C
required for stability. Capacitor must operate at minimum
OUT
NCV4279B
temperature expected.
V
OUT
RESET
C
**
R
RST
OUT
10 F
Figure 15. Test and Application Circuit Showing
Output Compensation
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 16) is:
P
D(max)
[V
V
IN(max)
IN(max)IQ
V
OUT(min)]IOUT(max)
(1)
where:
V V I
OUT(max)
is the maximum input voltage,
IN(max) OUT(min)
is the minimum output voltage,
is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at I
OUT(max)
Once the value of P
permissible value of R
The value of R
.
is known, the maximum
D(max)
can be calculated:
JA
R
JA
150°C 
JA
can then be compared with those in the
T
A
P
D
(2)
package section of the data sheet. Those packages with R
’s less than the calculated value in equation 2 will keep
JA
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heatsink will be required.
I
IN
V
IN
SMART
REGULATOR
Control
}
Features
I
Q
Figure 16. Single Output Regulator with Key
Performance Parameters Labeled
I
OUT
V
OUT
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NCV4279B
HEAT SINKS
A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.
Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R
R
R
JA
JC
JA
R
:
CS
R
SA
(3)
where:
R
= the junction−to−case thermal resistance,
JC
R
= the case−to−heatsink thermal resistance, and
CS
R
= the heatsink−to−ambient thermal resistance.
SA
R
appears in the package section of the data sheet. Like
JC
R
, it too is a function of package type. R
JA
CS
and R
are
SA
functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
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ORDERING INFORMATION
Device Output Voltage Package Shipping
NCV4279BD1 NCV4279BD1R2 NCV4279BD2 NCV4279BD2R2 NCV4279BDW NCV4279BDWR2
NCV4279B
SO−8
5.0 V SO−14
SO−20L
98 Units/Rail
2500 Tape & Reel
55 Units/Rail
1000 Tape & Reel
37 Units/Rail
1000 Tape & Reel
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−Y−
−Z−
NCV4279B
PACKAGE DIMENSIONS
SO−8
D SUFFIX
CASE 751−07
ISSUE AA
NOTES:
−X− A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
G
C
SEATING PLANE
0.10 (0.004)
H
D
0.25 (0.010) Z
M
Y
SXS
N
X 45
M
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDAARD IS 751−07
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010
J
J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244
INCHES
−T−
SEATING PLANE
−A−
14 8
G
D 14 PL
0.25 (0.010) A
SO−14
D SUFFIX
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
−B−
71
M
7 PL
P
M
0.25 (0.010) B
R
C
X 45
K
S
B
T
S
M
M
F
J
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
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NCV4279B
PACKAGE DIMENSIONS
SO−20L
DW SUFFIX
CASE 751D−05
ISSUE F
H10X
M
B
M
0.25
D
20
1
B20X
M
SAS
T
0.25
18X
e
A
11
E
10
h X 45
B
B
A
SEATING PLANE
A1
T
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
DIM MIN MAX
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49 C 0.23 0.32 D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55
L
C
h 0.25 0.75 L 0.50 0.90
0 7

SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local Sales Representative.
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