5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET
,
and Monitor FLAG
The NCV4279B is a 5.0 V precision micropower voltage regulator.
The output current capability is 150 mA.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature
drawing only 90 A with a 100 A load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active RESET
DELAY), and a FLAG monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending RESET
signal. The use of the FLAG monitor allows the microprocessor to
finish any signal processing before the RESET shuts the
microprocessor down.
The active RESET
circuit operates correctly at an output voltage as
low as 1.0 V. The RESET function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The reset threshold voltage can be decreased by the connection of
external resistor divider to R
ADJ
lead.
The regulator is protected against reverse battery, short circuit, and
thermal overload conditions. The device can withstand load dump
transients making it suitable for use in automotive environments. The
device has also been optimized for EMC conditions.
Features
• 5.0 V ± 2.0% Output
• Low 90 A Quiescent Current
• Active RESET
• Adjustable Reset
• 150 mA Output Current Capability
• Fault Protection
− +60 V Peak Transient Voltage
− −15 V Reverse Voltage
− Short Circuit
− Thermal Overload
• Early Warning through FLAG/MON Leads
• Internally Fused Leads in SO−14 and SO−20L Packages
• NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
(with
8
14
20
SO−8
SO−14
SO−20L
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MARKING DIAGRAMS
SO−8
D SUFFIX
1
1
1
CASE 751
SO−14
D SUFFIX
CASE 751A
SO−20L
DW SUFFIX
CASE 751D
A= Assembly Location
WL, L= Wafer Lot
YY, Y= Year
WW, W = Work Week
PIN CONNECTIONS
18
V
IN
R
ADJ
114
ADJ
DELAY
NC
1
ADJ
DELAY
GND
GND
NC
RESET
8
1
14
NCV4279B
AWLYWW
1
20
NCV4279B
AWLYYWW
1
V
OUT
FLAGMON
RESET
GNDDELAY
MONR
V
IN
GNDGND
GNDGND
GNDGND
V
OUT
FLAGRESET
20
MONR
V
IN
NCNC
GNDGND
GND
GND
GNDGND
NCNC
V
OUT
FLAG
4279B
ALYW
Semiconductor Components Industries, LLC, 2003
August, 2003 − Rev. 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
1Publication Order Number:
NCV4279B/D
NCV4279B
V
BAT
10 µF
C
DELAY
V
IN
NCV4279B
Delay
V
OUT
R
ADJ
MON
R
FLG
10 k
R
RST
10 k
10 µF
V
DD
Microprocessor
FLAG
RESET
GND
Figure 1. Application Diagram
MAXIMUM RATINGS*
V
(DC)−15 to 45V
IN
Peak Transient Voltage (46 V Load Dump @ VIN = 14 V)60V
RatingValueUnit
I/O
I/O
Operating Voltage45V
V
(DC)16V
OUT
Voltage Range (RESET, FLAG)−0.3 to 10V
Input Voltage Range (MON)−0.3 to 10V
ESD Susceptibility (Human Body Model)2.0kV
Junction Temperature, T
Storage Temperature, T
J
S
−40 to +150°C
−55 to 150°C
Package Thermal Resistance, SO−8:
Junction−to−Case, R
θ
Junction−to−Ambient, R
JC
θ
JA
45
165
Package Thermal Resistance, SO−14 (Fused) Minimum Pad Data:
Junction−to−Case, R
θ
Junction−to−Ambient, R
Junction−to−Pin, R
θ
JP
JC
θ
JA
(Note 3)
15
110
33
Package Thermal Resistance, SO−20L (Fused) Minimum Pad Data:
Junction−to−Case, R
θ
Junction−to−Ambient, R
Junction−to−Pin, R
θ
JP
JC
θ
JA
(Note 4)
12
82
26
Lead Temperature Soldering:Reflow: (SMD styles only) (Notes 1, 2)240 peak°C
1. 60 second maximum above 183°C.
2. −5°C/+0°C allowable conditions.
3. Measured to pin 9.
4. Measured to pin 12.
*The maximum package power dissipation must be observed.
†During the voltage range which exceeds the maximum tested voltage of V
Thermal dissipation must be observed closely.
, operation is assured, but not specified. Wider limits may apply.
= 100 A
Load RegulationVIN = 14 V, 5.0 mA ≤ I
Line Regulation[V
Quiescent Current, (IQ)
Active Mode
(typ) + 1.0] < VIN < 26 V, I
OUT
I
= 100 A, VIN = 12 V, Delay = 3.0 V, MON = 3.0 V
OUT
I
= 75 mA, VIN = 14 V, Delay = 3.0 V, MON = 3.0 V
OUT
≤ 150 mA, VIN = 14 V, Delay = 3.0 V, MON = 3.0 V
I
OUT
OUT
≤ 150 mA
OUT
≤ 150 mA
OUT
4.90
4.85
−
−
5.0
5.0
400
100
5.10
5.15
600
150
≤ 150 mA-305.030mV
= 1.0 mA−1560mV
OUT
−
−
−
90
4.0
12
125
6.0
19
Current Limit−151300−mA
Short Circuit Output CurrentV
= 0 V40190−mA
OUT
Thermal Shutdown(Guaranteed by Design)150180−°C
Reset Function (RESET)
Threshold
RESET
HIGH (V
LOW (V
RL
RH
)
)
V
V
OUT
OUT
Increasing
Decreasing
4.55
4.50
4.70
4.60
0.98 × V
0.97 × V
OUT
OUT
Output Voltage
Low (V
)1.0 V ≤ V
RLO
OUT
≤ VRL, R
= 10 k−0.10.4V
RESET
Delay Switching Threshold (VDT)−1.41.82.2V
V
V
mV
mV
A
mA
mA
V
V
Reset Delay Low VoltageV
Delay Charge CurrentDELAY = 1.0 V, V
Delay Discharge CurrentDELAY = 1.0 V, V
Reset Adjust Switching Voltage
(V
)
R(ADJ)
< RESET Threshold Low(min)−−0.1V
OUT
> V
OUT
RH
= 1.5 V5.0−−mA
OUT
1.52.53.5A
−1.231.311.39V
FLAG/Monitor
Monitor Threshold
Increasing and Decreasing1.101.201.31V
Hysteresis−2050100mV
Input CurrentMON = 2.0 V−0.50.10.5A
Output Saturation VoltageMON = 0 V, I
= 1.0 mA−0.10.4V
FLAG
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3
PACKAGE PIN DESCRIPTION
Package Pin Number
NCV4279B
SO−8SO−14SO−20L
311R
Pin SymbolFunction
ADJ
Reset Adjust. If not needed connect to ground.
422DELAYTiming capacitor for RESET function.
53−5, 10−124−7, 14−17GNDGround. All GND leads must be connected to Ground
.
−63, 8, 9, 13, 18NCNo connection.
6710RESETActive reset (accurate to V
OUT
≥ 1.0 V)
7811FLAGOpen collector output from early warning comparator.
8912V
11319V
OUT
IN
±2.0%, 150 mA output.
Input Voltage.
21420MONMonitor. Input for early warning comparator. If not needed connect to V
TYPICAL PERFORMANCE CHARACTERISTICS
(V)
OUT
V
5.01
5.00
4.99
V
V
I
OUT
OUT
IN
= 5.0 V
= 14 V
= 5.0 mA
1.2
1.0
0.8
0.6
(mA)
Q
I
0.4
+125°C
+25°C
OUT.
VIN = 12 V
−40°C
0.2
4.98
−25 −101255 203550658095110
−40
Temperature (°C)
0
0
5 10152025
(mA)
I
OUT
Figure 2. Output Voltage vs. TemperatureFigure 3. Quiescent Current vs. Output Current
14
VIN = 12 V
12
10
8
(mA)
Q
I
6
+125°C
+25°C
4
2
0
0
153045601407590 105 120 135
(mA)
I
OUT
Figure 4. Quiescent Current vs. Output Current
−40°C
7
6
I
= 100 mA
5
OUT
4
(mA)
Q
I
3
I
= 50 mA
2
1
0
6
8101214261618202224
OUT
I
OUT
V
IN
= 10 mA
(V)
Figure 5. Quiescent Current vs. Input Voltage
T = 25°C
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4
NCV4279B
TYPICAL PERFORMANCE CHARACTERISTICS
120
100
I
OUT
= 100 A
80
60
(µA)
Q
I
49
20
0
8101214261618202224
6
(V)
V
IN
Figure 6. Quiescent Current vs. Input Voltage
1000
Unstable Region
100
T = 25°C
450
400
350
300
250
200
+125°C
+25°C
−40°C
150
Dropout Voltage (mV)
100
50
0
0
255075100150
(mA)
I
OUT
Figure 7. Dropout Voltage vs. Output Current
1000
C
Unstable Region
100
10
Vout
= 10 F
C
Vout
125
= 0.1 F
ESR ()
10
Stable Region
C
= 10 F
1
Vout
0 10 20 30 40 50 60 70 80 90 100110120130140150
OUTPUT CURRENT (mA)
Figure 8. Output Capacitor ESR
ESR ()
1
Stable Region
0.1
0.01
0 1020305060708090100110
40
OUTPUT CURRENT (mA)
Figure 9. Output Stability with Output
Capacitor Change
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5
NCV4279B
V
V
IN
Current Source
(Circuit Bias)
I
BIAS
Current Limit
Sense
OUT
R
ADJ
RESET
Delay
MON
+
+
−
V
BG
I
BIAS
+
−
Error Amplifier
V
+
−
1.8 V
BG
Thermal
Protection
3.0 µA
I
BIAS
Bandgap
Reference
V
BG
+
I
BIAS
V
BG
GND
FLAG
−
Figure 10. Block Diagram
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6
NCV4279B
CIRCUIT DESCRIPTION
REGULATOR CONTROL FUNCTIONS
The NCV4279B contains the microprocessor compatible
control function RESET (Figure 11).
V
IN
V
OUT
DELAY
RESET
T
d
T
d
RESET
Threshold
DELAY
Threshold
(V
DT
Figure 11. Reset and Delay Circuit Wave Forms
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until V
voltage, or when V
is within 6.0% of the regulated output
OUT
drops out of regulation,and is lower
OUT
than 8.0% below the regulated output voltage. Hysteresis is
included in the function to minimize oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET
signal is valid for V
OUT
as low
as 1.0 V.
Adjustable Reset Function
The reset threshold can be made lower by connecting an
external resistor divider to the R
lead from the V
ADJ
OUT
lead, as displayed in Figure 12. This lead is grounded to
select the default value of 4.6 V.
DELAY Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
The DELAY lead provides source current (typically
2.5 A) to the external DELAY capacitor during the
following proceedings:
1. During Power Up (once the regulation threshold
has been verified).
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET
)
has been violated. This is a latched incident. The
capacitor will fully discharge and wait for the
device to regulate before going through the delay
time event again.
FLAG/Monitor Function
An on−chip comparator is provided to perform an early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the FLAG
will allow the microprocessor time to complete its present
task before shutting down. This function is performed by a
comparator referenced to the bandgap reference. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (MON) (Figure 13). The typical
threshold is 1.20 V on the MON Pin.
V
BAT
V
IN
MON
V
NCV4279B
FLAG
OUT
C
OUT
threshold)
V
CC
µP
I/O
pin
C
DELAY
V
OUT
RESET
R
ADJ
NCV4279B
Delay
Figure 12. Adjustable RESET
R
ADJ
to µP and
System
Power
C
R
RST
OUT
to µP and
RESET
Port
Figure 13. FLAG/Monitor Function
Delay
RESET
GND
RESET
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7
NCV4279B
APPLICATION NOTES
FLAG MONITOR
Figure 14 shows the FLAG Monitor waveforms as a result
of the circuit depicted in Figure 13. As the output voltage
falls (V
), the Monitor threshold is crossed. This causes
OUT
the voltage on the FLAG output to go low sending a warning
signal to the microprocessor that a RESET signal may occur
in a short period of time. T
WARNING
is the time the
microprocessor has to complete the function it is currently
working on and get ready for the RESET
V
OUT
MON
FLAG Monitor
Ref. Voltage
RESET
FLAG
T
WARNING
Figure 14. FLAG Monitor Circuit Waveform
shutdown signal.
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
t
DELAY
[
C
DELAY(Vdt
Delay Charge Current
Reset Delay Low Voltage)
]
Example:
Using C
DELAY
= 33 nF.
Assume reset Delay Low Voltage = 0.
Use the typical value for V
= 1.8 V.
dt
Use the typical value for Delay Charge Current = 2.5 A.
t
DELAY
[
33 nF(1.8 0)
2.5 A
]
23.8 ms
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay , load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for t he o utput c apacitor C
shown i n F igure 15
OUT
should work for most applications, however it is not
necessarily the optimized solution.
V
IN
CIN*
0.1 F
*CIN required if regulator is located far from the power supply filter.
**C
required for stability. Capacitor must operate at minimum
OUT
NCV4279B
temperature expected.
V
OUT
RESET
C
**
R
RST
OUT
10 F
Figure 15. Test and Application Circuit Showing
Output Compensation
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 16) is:
P
D(max)
[V
V
IN(max)
IN(max)IQ
V
OUT(min)]IOUT(max)
(1)
where:
V
V
I
OUT(max)
is the maximum input voltage,
IN(max)
OUT(min)
is the minimum output voltage,
is the maximum output current for the
application, and
IQ is the quiescent current the regulator consumes at
I
OUT(max)
Once the value of P
permissible value of R
The value of R
.
is known, the maximum
D(max)
can be calculated:
JA
R
JA
150°C
JA
can then be compared with those in the
T
A
P
D
(2)
package section of the data sheet. Those packages with
R
’s less than the calculated value in equation 2 will keep
JA
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
I
IN
V
IN
SMART
REGULATOR
Control
}
Features
I
Q
Figure 16. Single Output Regulator with Key
Performance Parameters Labeled
I
OUT
V
OUT
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8
NCV4279B
HEAT SINKS
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R
R
R
JA
JC
JA
R
:
CS
R
SA
(3)
where:
R
= the junction−to−case thermal resistance,
JC
R
= the case−to−heatsink thermal resistance, and
CS
R
= the heatsink−to−ambient thermal resistance.
SA
R
appears in the package section of the data sheet. Like
JC
R
, it too is a function of package type. R
JA
CS
and R
are
SA
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
−B−
71
M
7 PL
P
M
0.25 (0.010)B
R
C
X 45
K
S
B
T
S
M
M
F
J
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
DIM MINMAX
A2.352.65
A10.100.25
B0.350.49
C0.230.32
D 12.65 12.95
E7.407.60
e1.27 BSC
H 10.05 10.55
L
C
h0.250.75
L0.500.90
0 7
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free USA/Canada
http://onsemi.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
NCV4279B/D
12
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