ON Semiconductor NCV4269 Technical data

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NCV4269

5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output

The NCV4269 is a 5.0 V precision micropower voltage regulator

with an output current capability of 150 mA.

The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 240 mA with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.

Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.

The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.

The reset threshold voltage can be decreased by the connection of an
external resistor divider to the R
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.

Features

• 5.0 V ± 2.0% Output

• Low 240 mA Quiescent Current

• Active Reset Output Low Down to V

• Adjustable Reset Threshold

• 150 mA Output Current Capability

• Fault Protection

♦ +60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload

• Early Warning through SI/SO Leads

• Internally Fused Leads in SO−14 and SO−20L Packages

• Integrated Pullup Resistor at Logic Outputs (To Use External

Resistors, Select the NCV4279)

• Very Low Dropout Voltage

• Electrical Parameters Guaranteed Over Entire Temperature Range

• NCV Prefix for Automotive and Other Applications Requiring Site

and Control Changes

• Pb−Free Packages are Available

lead. The regulator is protected

ADJ

= 1.0 V

Q

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MARKING

DIAGRAMS

8

8

1

8

1

14

1

20

1

SO−20L
DW SUFFIX
CASE 751D

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G, G = Pb Free

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.

SO−8
D SUFFIX
CASE 751

SO−8

EXPOSED PAD

D SUFFIX

CASE 751AC

SO−14

D SUFFIX

CASE 751A

20

1

4269

ALYW

G

1

8

V4269
ALYW

G

1

14

NCV4269

AWLYWWG

1

NCV4269

AWLYYWWG

© Semiconductor Components Industries, LLC, 2007

February, 2007 − Rev. 10

1 Publication Order Number:

NCV4269/D

NCV4269

PIN CONNECTIONS

I

D

R

ADJ

SI

18

ADJ

SO−8

QI
SOSI

ROR
GNDD

Reference

and Trim

or

Error

Amplifier

Current and

Saturation

Reference

Figure 1. Block Diagram

114

ADJ

Control

+

−

SIR
ID
GNDGND

GNDGND
GNDGND
QGND
SORO

Q

R

SO

R

RO

RO

SO

GND

1

ADJ

20

SIR
ID
NCNC
GNDGND

GND
GND

GND
GND
GNDGND
NCNC
QNC
SORO

SO−20LSO−14

PACKAGE PIN DESCRIPTION

Package Pin Number

SO−8 SO−14 SO−20L

3 1 1 R

Pin Symbol Function

ADJ

Reset Threshold Adjust; if not used to connect to GND.
4 2 2 D Reset Delay; To Set Time Delay, Connect to GND with Capacitor
5 3, 4, 5, 6,

10, 11, 12

4, 5, 6, 7, 14,

15, 16, 17

GND Ground

− − 3, 8, 9, 13, 18 NC No connection to these pins from the IC.
6 7 10 RO

Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor to

Q. Leave Open if Not Used.
7 8 11 SO Sense Output; This Open−Collector Output is Internally Pulled Up by

20 kW pullup resistor to Q. If not used, keep open.
8 9 12 Q

5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W.
1 13 19 I Input; Connect to GND Directly at the IC with a Ceramic Capacitor.
2 14 20 SI Sense Input; If not used, Connect to Q.

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2

NCV4269

MAXIMUM RATINGS (T

= −40°C to 150°C)

J

Parameter Symbol Min Max Unit

Input to Regulator V

Input Transient to Regulator V
Sense Input V

Reset Threshold Adjust V

I

RADJ

Reset Delay V

Ground I
Reset Output V

Sense Output V

Regulated Output V

Junction Temperature
Storage Temperature

T

Input Voltage Operating Range
Junction Temperature Operating Range

I

I

I

I

SI

I

SI

RADJ

D

I

D
q

RO

I

RO

SO

I

SO

Q

I

Q

T

J

STG

V

I

T

J

−40

Internally Limited45Internally Limited

− 60 V

−40

−1

−0.3

−10

45

1
7

10

−0.3

Internally Limited7Internally Limited

50 − mA

−0.3

Internally Limited7Internally Limited

−0.3

Internally Limited7Internally Limited

−0.5

−10

−

−50

−

−40

7.0

−

150
150

45

150

V

V

mA

V

mA

V

V

V

V

mA

°C
°C

V

°C

Lead Temperature Soldering and MSL

Parameter Symbol Value

MSL, 20−Lead LS Temperature 265°C Peak (Note 3) MSL 3
MSL, 20−Lead, LS Temperature 240°C Peak (Note 4) MSL 1
MSL, 8−Lead, 14−Lead, LS Temperature 265°C Peak (Note 3) MSL 1
MSL, 8−Lead EP, LS Temperature 260°C MSL 2

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114.
Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115.

2. Latchup Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78.

3. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.

4. +5°C/−0°C, 30 Sec Max−at−Peak, 60 − 150 Sec above 183°C.

THERMAL CHARACTERISTICS

Characteristic Test Conditions (Typical Values) Unit

SO−8 Package (Note 5)

Junction−to−Pin 4 ( Y − JL4, YL4)
Junction−to−Ambient Thermal Resistance (R

q

JA

, qJA)

SO−8 EP Package (Note 5)

Junction−to−Pin 8 ( Y − JL8, YL8)
Junction−to−Ambient Thermal Resistance (R

q

JA

, qJA)

Junction−to−Pad ( Y − JPad)

SO−14 Package (Note 5)

Junction−to−Pin 4 ( Y − JL4, YL4)
Junction−to−Ambient Thermal Resistance (R

q

JA

, qJA)

SO−20 Package (Note 5)

Junction−to−Pin 4 ( Y − JL4, YL4)
Junction−to−Ambient Thermal Resistance (R

q

JA

, qJA)

5. 2 oz copper, 50 mm2 copper area, 1.5 mm thick FR4

53.8 °C/W

170.9 °C/W

23.7 °C/W

71.4 °C/W

7.7 °C/W

18.4 °C/W

111.6 °C/W

21.8 °C/W

95.3 °C/W

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3

NCV4269

ELECTRICAL CHARACTERISTICS (T

= −40°C ≤ T

J

Characteristic Symbol Test Conditions Min Typ Max Unit

REGULATOR

Output Voltage
Current Limit I
Current Consumption; Iq = II – I
Current Consumption; Iq = II – I
Current Consumption; Iq = II – I

Q

Q

Q

Dropout Voltage V
Load Regulation
Line Regulation

RESET GENERATOR

Reset Switching Threshold V
Reset Adjust Switching Threshold V
Reset Pullup Resistance R
Reset Output Saturation Voltage V
Upper Delay Switching Threshold V
Lower Delay Switching Threshold V
Saturation Voltage on Delay Capacitor V
Charge Current I
Delay Time L ³ H t
Delay Time H ³ L t

INPUT VOLTAGE SENSE

Sense Threshold High V
Sense Threshold Low V
Sense Output Saturation Voltage V
Sense Resistor Pullup R
Sense Input Current I

V

Q

Q

I

q

I

q

I

q

dr

D

VQ

D

VQ

RT

RAD,JTH

SO,INT

RO,SAT

UD

LD

D,SAT

D

d

t

SI,High

SI,Low

SO,Low

SO,INT

SI

≤ 125°C, VI = 13.5 V unless otherwise specified)

J

1 mA v IQ v 100 mA 6 V v VI v 16 V 4.90 5.00 5.10 V

− 150 200 500 mA

IQ = 1 mA, RO, SO High − 240 250
IQ = 10 mA, RO, SO High − 250 450
IQ = 50 mA, RO, SO High − 2.0 3.0 mA

VI = 5 V, IQ = 100 mA − 0.25 0.5 V

IQ = 5 mA to 100 mA − 10 20 mV

VI = 6 V to 26 V IQ = 1 mA − 10 30 mV

− 4.50 4.65 4.80 V

VQ > 3.5 V 1.26 1.35 1.44 V

− 10 20 40

VQ < VRT, R

RO, INT

− 0.1 0.4 V

− 1.4 1.8 2.2 V

− 0.3 0.45 0.60 V

VQ < V

RT

− − 0.1 V

VD = 1 V 3.0 6.5 9.5
CD = 100 nF 17 28 − ms
CD = 100 nF − 1.0 −

− 1.24 1.31 1.38 V

− 1.16 1.20 1.28 V

VSI < 1.20 V; VQ > 3 V; R

SO

− 0.1 0.4 V

− 10 20 40

− −1.0 0.1 1.0

mA
mA

kW

mA

ms

kW
mA

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4

NCV4269

I

I

C

1000 mF

V

I

V

SI

I

470 nF

I

I

SI

SI

D GND RO SO

I

D

V

C

D

D

RADJ

I

V

q

RO

V

Q

SO

I

Q

RADJ1

I

RADJ

V

RADJ

RADJ2

C

Q

22 mF

V

Q

100 nF

Figure 2. Measuring Circuit

V

I

V

Q

V

RT

V

D

V

UD

V

LD

t

d

V

RO

V

ROSAT

Power−on−Reset Thermal

t

RR

Shutdown

Voltage Dip

Undervoltage Secondary

at Input

Figure 3. Reset Timing Diagram

Spike

< t

RR

Overload
at Output

dV

t

t

I

D

+

dt

C

D

t

t

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5

Sense Input Voltage

V

SI,HIGH

V

SI,LOW

NCV4269

t

Sense Output Voltage

16
14
12
10

HIGH

LOW

VI = 13.5 V
VD = 1.0 V

t

PDSOLH

Figure 4. Sense Timing Diagram

TYPICAL PERFORMANCE CHARACTERISTICS

3.2

2.8

2.4

2.0

VI = 13.5 V

V

UD

t

PDSOHL

t

8

, (mA)

D

I

6
4
2
0

−40 0 40 80 120 160
TJ, (°C)

Figure 5. Charge Current ID vs. Temperature T

1.6

, (V)

D

V

1.2

0.8

0.4
0

−40 0 40 80 120 160

J

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6

V

LD

TJ, (°C)

Figure 6. Switching Voltage VUD and VLD vs.

Temperature T

J

I

, (mA)

1.7

0

V

, (mV)

500

0

J

J

V

, (V)

0

400

300

dr

200

100

TJ = 125°C

TJ = 25°C

NCV4269

TYPICAL PERFORMANCE CHARACTERISTICS

1.6

1.5

1.4

, (V)

TJ = −40°C

1.3

RAD,JTH

1.2

V

1.1

1.0

0

0 30 60 90 120 150 180

IQ, (mA)

Figure 7. Drop Voltage Vdr vs. Output Current I

35

30

25

20

q

15

10

5

0

0

RL = 33 W

RL = 100 W

RL = 200 W

RL = 50 W

10 20 30 40 50

VI, (V)

Figure 9. Current Consumption Iq vs. Input

Voltage V

I

0.9

−40

0 40 80 120 16

TJ, (°C)

Q

Figure 8. Reset Adjust Switching Threshold,

V

RAD,JTH

vs. Temperature T

J

12

10

8

(V)

6

Q

V

RL = 50 W

4

2

0

0

24681

VI, (V)

Figure 10. Output Voltage VQ vs. Input Voltage V

I

1.6
VI = 13.5 V

1.5

1.4

1.3

SI

V

SI, High

V

SI, Low

1.2

1.1

1.0

−40 0 40 80 120 160
TJ, (°C)

Figure 11. Sense Threshold VSI vs. Temperature T

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5.2

5.1
VI = 13.5 V

5.0

4.9

, (V)

Q

V

4.8

4.7

4.6

−40 0 40 80 120 16
TJ, (°C)

Figure 12. Output Voltage VQ vs. Temperature T

7

NCV4269

I

, (

A)

I

, (mA)

I

, (mA)

350

12

0

6

0

TYPICAL PERFORMANCE CHARACTERISTICS

300

250

200

150

Q

100

50

0

0 1020304050

TJ = 25°C

TJ = 125°C

VI, (V)

Figure 13. Output Current Limit IQ vs. Input

Voltage V

1.6
VI = 13.5 V

1.4
TJ = 25°C

1.2

1.0

0.8

q

0.6

0.4

0.2

0.0

01020 4050

IQ, (mA)

I

30

VI = 13.5 V

10

TJ = 25°C

8

6

, (mA)

q

I

4

2

0

02040 80 12

60

IQ, (mA)

100

Figure 14. Current Consumption Iq vs. Output

7

6

5

4

, (mA)

q

3

I

2

1

0

Current I

IQ = 100 mA

IQ = 50 mA

IQ = 10 mA

6

810121416182022242

VI, (V)

Q

TJ = 125°C

Figure 15. Current Consumption Iq vs.

Output Current I

250

TJ = 25°C

200

m

150

q

100

50

6

8101214161820222426

IQ = 100 mA

VI, (V)

Figure 17. Quiescent Current Iq vs. Input Voltage V

Q

100

10

ESR (W)

1

0.1
0

I

Figure 16. Quiescent Current Iq vs.

Input Voltage V

Unstable Region

for all caps

Unstable Region

for 0.1 mF ONLY

25 50 75 100 125 15

OUTPUT CURRENT IN MILLIAMPS

I

Stable Region for

0.1 mF to 10 mF

Stable Region for

1 mF to 10 mF

Figure 18. Output Stability, Capacitance ESR

vs. Output Load Current

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8

0

200

0

180
160
140
120
100

(°C/W)

JA

q

80
60
40
20

NCV4269

TYPICAL THERMAL CHARACTERISTICS

0

600400300200100 5000

COPPER HEAT−SPREADER AREA (mm2)

SO−8 Std Package NCV4269, 1.0 oz
SO−8 Std Package NCV4269, 2.0 oz
SO−14 w/6 Thermal Leads NCV4269, 1.0 oz
SO−14 w/6 Thermal Leads NCV4269, 2.0 oz
SO−20 w/8 Thermal Leads NCV4269, 1.0 oz
SO−20 w/8 Thermal Leads NCV4269, 2.0 oz

70

Figure 19. Junction−to−Ambient Thermal Resistance (qJA) vs. Heat Spreader Area

1000

100

10

R(t) (°C/W)

1

0.1

0.000001 0.00001 0.0001 0.001 0.01 0.1

PULSE TIME (s)

Single Pulse (SO−8 Std Package) PCB = 50 mm2, 2.0 oz
Single Pulse (SO−8 EP Package)
Single Pulse (SO−14 w/6 Thermal Leads) PCB = 50 mm2, 2.0 oz
Single Pulse (SO−20 w/8 Thermal Leads) PCB = 50 mm2, 2.0 oz

YLA (SO−8)
YLA (SO−14)
YLA (SO−20)

Figure 20. R(t) vs. Pulse Time

1 10 100 100

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9

NCV4269

APPLICATION DESCRIPTION

OUTPUT REGULATOR

The output is controlled by a precision trimmed reference.
The PNP output has base drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.

RESET OUTPUT (RO)

A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage V
increases above the reset threshold voltage VRT, the delay
timer D is started. When the voltage on the delay timer V
passes VUD, the reset signal RO goes high. A discharge of
the delay timer VD is started when VQ drops and stays below
the reset threshold voltage VRT. When the voltage of the
delay timer VD drops below the lower threshold voltage V

LD

the reset output voltage VRO is brought low to reset the
processor.

The reset output RO is an open collector NPN transistor
with an internal 20 kW pullup resistor connected to the
output Q, controlled by a low voltage detection circuit. The
circuit is functionally independent of the rest of the IC,
thereby guaranteeing that RO is valid for VQ as low as 1.0 V.

RESET ADJUST (R

ADJ

)

The reset threshold VRT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 21. The resistor divider keeps the voltage
above the V

RADJ,TH

(typical 1.35 V) for the desired input
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:

VRT+ V

RADJ,TH

@ (R

ADJ1

) R

ADJ2

)ń R

ADJ2

(eq. 1)

If the reset adjust option is not needed, the R
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).

RESET DELAY (D)

The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output lead RO. The delay lead D

provides charge current ID (typically 6.5 mA) to the external
delay capacitor CD during the following times:

1. During Powerup (once the regulation threshold has

Q

been exceeded).

2. After a reset event has occurred and the device is

D

back in regulation. The delay capacitor is set to
discharge when the regulation (VRT, reset
threshold voltage) has been violated. When the
delay capacitor discharges to VLD, the reset signal
RO pulls low.

SETTING THE DELAY TIME

The delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delay
capacitor voltage charging from the low level of V
the higher level VUD. The time delay follows the equation:

td+ [CD(VUD* V

DSAT

)]ńI

Example:
Using CD = 100 nF.
Use the typical value for V

DSAT

= 0.1 V.
Use the typical value for VUD = 1.8 V.
Use the typical value for Delay Charge Current ID = 6.5 mA.

td+ [100 nF(1.8* 0.1 V)]ń 6.5 mA + 26.2 ms

pin

ADJ

to

DSAT

D

(eq. 2)

(eq. 3)

V

BAT

CI*

C

D

0.1 mF

I

D

NCV4269

Q

R

ADJ1

R

ADJ

R

ADJ2

SI

R

SI1

R

SI2

CQ**
10 mF

V

DD

Microprocessor

SO

GND

*CI required if regulator is located far from the power supply filter.
** CQ required for Stability. Cap must operate at minimum temperature expected.

RO

Figure 21. Application Diagram

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10

I/O

I/O

NCV4269

V

V

SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE
MONITOR

An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal. The
output is from an open collector driver with an internal
20 kW pull up resistor to output Q. The reset signal typically
turns the microprocessor off instantaneously. This can cause
unpredictable results with the microprocessor. The signal
received from the SO pin will allow the microprocessor time
to complete its present task before shutting down. This
function is performed by a comparator referenced to the
band gap voltage. The actual trip point can be programmed
externally using a resistor divider to the input monitor SI
(Figure 21). The values for R

SI1

and R

are selected for a

SI2

typical threshold of 1.20 V on the SI Pin.

SIGNAL OUTPUT

Figure 22 shows the SO Monitor timing waveforms as a
result of the circuit depicted in Figure 21. As the output
voltage (VQ) falls, the monitor threshold (V

SILOW

), is
crossed. This causes the voltage on the SO output to go low
sending a warning signal to the microprocessor that a reset
signal may occur in a short period of time. T

WARNIN G

is the
time the microprocessor has to complete the function it is
currently working on and get ready for the reset
shutdown signal.

Q

SI

SILOW

V

RO

instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.

The value for the output capacitor CQ shown in Figure 21
should work for most applications; however, it is not
necessarily the optimized solution. Stability is guaranteed at
values CQ = 10 mF and an ESR = 10 W within the operating
temperature range. Actual limits are shown in a graph in the
typical data section.

CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR

The maximum power dissipation for a single output
regulator (Figure 21) is:

P

D(max)

+ [V

I(max)

* V

Q(min)]IQ(max)

) V

I(max)Iq

(eq. 4)

where:
V

is the maximum input voltage,

I(max)

V
I

is the minimum output voltage,

Q(min)

is the maximum output current for the application,

Q(max)

and Iq is the quiescent current the regulator consumes at
I

.

Q(max)

Once the value of P
permissible value of R

R

= (150°C – TA) / P

q

JA

The value of R

can then be compared with those in the

qJA

qJA

is known, the maximum

D(max)

can be calculated:

D

(eq. 5)

package section of the data sheet. Those packages with
R

’s less than the calculated value in equation 2 will keep

qJA

the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required. The current
flow and voltages are shown in the
Measurement Circuit Diagram.

HEATSINKS

SO

A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.

Each material in the heat flow path between the IC and the

T

WARNING

Figure 22. SO Warning Waveform Time Diagram

STABILITY CONSIDERATIONS

The input capacitor CI in Figure 21 is necessary for
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a r es is to r of approximately 1.0 W in series
with C

I.

The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay ,
load transient response and loop stability.

The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause

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outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R

R

+ R

qJA

qJA

qJC

:

) R

qCS

) R

qSA

where:
R

= the junction−to−case thermal resistance,

qJC

R

= the case−to−heat sink thermal resistance, and

qCS

R

= the heat sink−to−ambient thermal resistance.

qSA

R

appears in the package section of the data sheet. Like

qJC

R

, it too is a function of package type. R

qJA

qCS

and R
functions of the package type, heatsink and the interface
between them. These values appear in data sheets of
heatsink manufacturers. Thermal, mounting, and
heatsinking considerations are discussed in the
ON Semiconductor application note AN1040/D, available
on the ON Semiconductor website.

11

(eq. 6)

qSA

are

NCV4269

ORDERING INFORMATION

Device Output Voltage Package Shipping

NCV4269D1
NCV4269D1G SO−8

NCV4269D1R2 SO−8
NCV4269D1R2G SO−8

NCV4269PDG SO−8 EP

NCV4269PDR2G SO−8 EP

NCV4269D2 SO−14
NCV4269D2G SO−14

NCV4269D2R2 SO−14
NCV4269D2R2G SO−14

NCV4269DW SO−20L
NCV4269DWG SO−20L

NCV4269DWR2 SO−20L
NCV4269DWR2G SO−20L

†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

5.0 V

SO−8

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

98 Units/Rail

2500 Tape & Reel

98 Units/Rail

2500 Tape & Reel

55 Units/Rail

2500 Tape & Reel

38 Units/Rail

1000 Tape & Reel

†

http://onsemi.com

12

−Y−

−Z−

NCV4269

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

NOTES:

−X−
A

58

B

1

S

0.25 (0.010)

4

M

M

Y

K

G

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

Y

SXS

N

X 45

_

M

J

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050

M 0 8 0 8

____

N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

INCHES

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

0.6

0.024

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

4.0

0.155

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

http://onsemi.com

13

2 X

LOCATION

8 X

SEATING

PLANE

C0.10

PIN ONE

C

D

A

E1

D

14

e

B

TOP VIEW

C0.10

C0.10

SIDE VIEW

NCV4269

PACKAGE DIMENSIONS

SOIC−8 EP

CASE 751AC−01

ISSUE B

2 X

C0.10 A−B

D

58

EXPOSED

PAD

F

58

E

8 X b

2 X

C0.20

BOTTOM VIEW

14

A−B0.25 DC

DETAIL A

G

AA

END VIEW

c

GAUGE

PLANE

H

b1

A

A2

L

A1

0.25

(L1)

DETAIL A

q

c1

SECTION A−A

NOTES:

1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).

3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE

0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.

MILLIMETERS

h

(b)

DIM MIN MAX

A 1.35 1.75
A1 0.00 0.10
A2 1.35 1.65

b 0.31 0.51

b1 0.28 0.48

c 0.17 0.25

c1 0.17 0.23

D 4.90 BSC

E 6.00 BSC
E1 3.90 BSC

e 1.27 BSC

L 0.40 1.27

L1 1.04 REF

F 2.24 3.20

G 1.55 2.51

h 0.25 0.50

q 0 8

__

SOLDERING FOOTPRINT*

2.72

0.107

1.52

0.060

7.0

0.275

2.03

0.08

4.0

0.155

0.6

0.024

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

1.270

0.050

Exposed
Pad

mm

ǒ

Ǔ

inches

http://onsemi.com

14

−T−

SEATING
PLANE

−A−

14 8

G

D 14 PL

0.25 (0.010) A

NCV4269

PACKAGE DIMENSIONS

SO−14

D SUFFIX

CASE 751A−03

ISSUE G

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

−B−

P 7 PL

M

71

0.25 (0.010) B

C

R X 45

K

M

S

B

T

S

M

_

M

F

J

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

____

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

http://onsemi.com

15

NCV4269

−PACKAGE DIMENSIONS

SO−20L

DW SUFFIX

CASE 751D−05

ISSUE G

H10X

M

B

M

0.25

D

20

1

B20X

M

SAS

T

18X

0.25

e

A

11

_

E

10

h X 45

B

B

A

SEATING
PLANE

A1

T

q

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 12.65 12.95

E 7.40 7.60
e 1.27 BSC

L

C

H 10.05 10.55

h 0.25 0.75
L 0.50 0.90

q 0 7

__

SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLIC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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LITERATURE FULFILLMENT:

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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For additional information, please contact your local
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NCV4269/D

16