ON Semiconductor NCV4269 Technical data

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NCV4269

5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output

The NCV4269 is a 5.0 V precision micropower voltage regulator

with an output current capability of 150 mA.

The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 240 mA with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.

Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.

The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.

The reset threshold voltage can be decreased by the connection of an
external resistor divider to the R
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.

Features

• 5.0 V ± 2.0% Output

• Low 240 mA Quiescent Current

• Active Reset Output Low Down to V

• Adjustable Reset Threshold

• 150 mA Output Current Capability

• Fault Protection

♦ +60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload

• Early Warning through SI/SO Leads

• Internally Fused Leads in SO−14 and SO−20L Packages

• Integrated Pullup Resistor at Logic Outputs (To Use External

Resistors, Select the NCV4279)

• Very Low Dropout Voltage

• Electrical Parameters Guaranteed Over Entire Temperature Range

• NCV Prefix for Automotive and Other Applications Requiring Site

and Control Changes

• Pb−Free Packages are Available

lead. The regulator is protected

ADJ

= 1.0 V

Q

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MARKING

DIAGRAMS

8

8

1

8

1

14

1

20

1

SO−20L
DW SUFFIX
CASE 751D

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G, G = Pb Free

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.

SO−8
D SUFFIX
CASE 751

SO−8

EXPOSED PAD

D SUFFIX

CASE 751AC

SO−14

D SUFFIX

CASE 751A

20

1

4269

ALYW

G

1

8

V4269
ALYW

G

1

14

NCV4269

AWLYWWG

1

NCV4269

AWLYYWWG

© Semiconductor Components Industries, LLC, 2007

February, 2007 − Rev. 10

1 Publication Order Number:

NCV4269/D

NCV4269

PIN CONNECTIONS

I

D

R

ADJ

SI

18

ADJ

SO−8

QI
SOSI

ROR
GNDD

Reference

and Trim

or

Error

Amplifier

Current and

Saturation

Reference

Figure 1. Block Diagram

114

ADJ

Control

+

−

SIR
ID
GNDGND

GNDGND
GNDGND
QGND
SORO

Q

R

SO

R

RO

RO

SO

GND

1

ADJ

20

SIR
ID
NCNC
GNDGND

GND
GND

GND
GND
GNDGND
NCNC
QNC
SORO

SO−20LSO−14

PACKAGE PIN DESCRIPTION

Package Pin Number

SO−8 SO−14 SO−20L

3 1 1 R

Pin Symbol Function

ADJ

Reset Threshold Adjust; if not used to connect to GND.
4 2 2 D Reset Delay; To Set Time Delay, Connect to GND with Capacitor
5 3, 4, 5, 6,

10, 11, 12

4, 5, 6, 7, 14,

15, 16, 17

GND Ground

− − 3, 8, 9, 13, 18 NC No connection to these pins from the IC.
6 7 10 RO

Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor to

Q. Leave Open if Not Used.
7 8 11 SO Sense Output; This Open−Collector Output is Internally Pulled Up by

20 kW pullup resistor to Q. If not used, keep open.
8 9 12 Q

5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W.
1 13 19 I Input; Connect to GND Directly at the IC with a Ceramic Capacitor.
2 14 20 SI Sense Input; If not used, Connect to Q.

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NCV4269

MAXIMUM RATINGS (T

= −40°C to 150°C)

J

Parameter Symbol Min Max Unit

Input to Regulator V

Input Transient to Regulator V
Sense Input V

Reset Threshold Adjust V

I

RADJ

Reset Delay V

Ground I
Reset Output V

Sense Output V

Regulated Output V

Junction Temperature
Storage Temperature

T

Input Voltage Operating Range
Junction Temperature Operating Range

I

I

I

I

SI

I

SI

RADJ

D

I

D
q

RO

I

RO

SO

I

SO

Q

I

Q

T

J

STG

V

I

T

J

−40

Internally Limited45Internally Limited

− 60 V

−40

−1

−0.3

−10

45

1
7

10

−0.3

Internally Limited7Internally Limited

50 − mA

−0.3

Internally Limited7Internally Limited

−0.3

Internally Limited7Internally Limited

−0.5

−10

−

−50

−

−40

7.0

−

150
150

45

150

V

V

mA

V

mA

V

V

V

V

mA

°C
°C

V

°C

Lead Temperature Soldering and MSL

Parameter Symbol Value

MSL, 20−Lead LS Temperature 265°C Peak (Note 3) MSL 3
MSL, 20−Lead, LS Temperature 240°C Peak (Note 4) MSL 1
MSL, 8−Lead, 14−Lead, LS Temperature 265°C Peak (Note 3) MSL 1
MSL, 8−Lead EP, LS Temperature 260°C MSL 2

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114.
Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115.

2. Latchup Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78.

3. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.

4. +5°C/−0°C, 30 Sec Max−at−Peak, 60 − 150 Sec above 183°C.

THERMAL CHARACTERISTICS

Characteristic Test Conditions (Typical Values) Unit

SO−8 Package (Note 5)

Junction−to−Pin 4 ( Y − JL4, YL4)
Junction−to−Ambient Thermal Resistance (R

q

JA

, qJA)

SO−8 EP Package (Note 5)

Junction−to−Pin 8 ( Y − JL8, YL8)
Junction−to−Ambient Thermal Resistance (R

q

JA

, qJA)

Junction−to−Pad ( Y − JPad)

SO−14 Package (Note 5)

Junction−to−Pin 4 ( Y − JL4, YL4)
Junction−to−Ambient Thermal Resistance (R

q

JA

, qJA)

SO−20 Package (Note 5)

Junction−to−Pin 4 ( Y − JL4, YL4)
Junction−to−Ambient Thermal Resistance (R

q

JA

, qJA)

5. 2 oz copper, 50 mm2 copper area, 1.5 mm thick FR4

53.8 °C/W

170.9 °C/W

23.7 °C/W

71.4 °C/W

7.7 °C/W

18.4 °C/W

111.6 °C/W

21.8 °C/W

95.3 °C/W

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NCV4269

ELECTRICAL CHARACTERISTICS (T

= −40°C ≤ T

J

Characteristic Symbol Test Conditions Min Typ Max Unit

REGULATOR

Output Voltage
Current Limit I
Current Consumption; Iq = II – I
Current Consumption; Iq = II – I
Current Consumption; Iq = II – I

Q

Q

Q

Dropout Voltage V
Load Regulation
Line Regulation

RESET GENERATOR

Reset Switching Threshold V
Reset Adjust Switching Threshold V
Reset Pullup Resistance R
Reset Output Saturation Voltage V
Upper Delay Switching Threshold V
Lower Delay Switching Threshold V
Saturation Voltage on Delay Capacitor V
Charge Current I
Delay Time L ³ H t
Delay Time H ³ L t

INPUT VOLTAGE SENSE

Sense Threshold High V
Sense Threshold Low V
Sense Output Saturation Voltage V
Sense Resistor Pullup R
Sense Input Current I

V

Q

Q

I

q

I

q

I

q

dr

D

VQ

D

VQ

RT

RAD,JTH

SO,INT

RO,SAT

UD

LD

D,SAT

D

d

t

SI,High

SI,Low

SO,Low

SO,INT

SI

≤ 125°C, VI = 13.5 V unless otherwise specified)

J

1 mA v IQ v 100 mA 6 V v VI v 16 V 4.90 5.00 5.10 V

− 150 200 500 mA

IQ = 1 mA, RO, SO High − 240 250
IQ = 10 mA, RO, SO High − 250 450
IQ = 50 mA, RO, SO High − 2.0 3.0 mA

VI = 5 V, IQ = 100 mA − 0.25 0.5 V

IQ = 5 mA to 100 mA − 10 20 mV

VI = 6 V to 26 V IQ = 1 mA − 10 30 mV

− 4.50 4.65 4.80 V

VQ > 3.5 V 1.26 1.35 1.44 V

− 10 20 40

VQ < VRT, R

RO, INT

− 0.1 0.4 V

− 1.4 1.8 2.2 V

− 0.3 0.45 0.60 V

VQ < V

RT

− − 0.1 V

VD = 1 V 3.0 6.5 9.5
CD = 100 nF 17 28 − ms
CD = 100 nF − 1.0 −

− 1.24 1.31 1.38 V

− 1.16 1.20 1.28 V

VSI < 1.20 V; VQ > 3 V; R

SO

− 0.1 0.4 V

− 10 20 40

− −1.0 0.1 1.0

mA
mA

kW

mA

ms

kW
mA

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NCV4269

I

I

C

1000 mF

V

I

V

SI

I

470 nF

I

I

SI

SI

D GND RO SO

I

D

V

C

D

D

RADJ

I

V

q

RO

V

Q

SO

I

Q

RADJ1

I

RADJ

V

RADJ

RADJ2

C

Q

22 mF

V

Q

100 nF

Figure 2. Measuring Circuit

V

I

V

Q

V

RT

V

D

V

UD

V

LD

t

d

V

RO

V

ROSAT

Power−on−Reset Thermal

t

RR

Shutdown

Voltage Dip

Undervoltage Secondary

at Input

Figure 3. Reset Timing Diagram

Spike

< t

RR

Overload
at Output

dV

t

t

I

D

+

dt

C

D

t

t

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