ON Semiconductor NCP9003 Technical data

NCP9003

Compact Backlight LED Boost Driver

The NCP9003 is a high efficiency boost converter operating in current loop, based on a PFM mode, to drive White LED. The current mode regulation allows a uniform brightness of the LEDs. The chip has been optimized for small ceramic capacitors, capable to supply up to 1.0 W output power.

Features

• 2.7 to 5.5 V Input Voltage Range

• V

to 24 V Output Compliance Allows up to 5 LEDs Drive in

out

Series

• Built−in Overvoltage Protection

• Full EMI Immunity

• Inductor Based Converter brings up to 90% Efficiency

• Constant Output Current Regulation

• 0.3 mA Standby Quiescent Current

• Includes Dimming Function (PWM)

• Enable Function Driven Directly from Low Battery Voltage Source

• Automatic LEDs Current Matching

• Thermal Shutdown Protection

• All Pins are Fully ESD Protected

• Low EMI Radiation

• Pb−Free Package is Available

http://onsemi.com

TSOP−5

SN SUFFIX

CASE 483

DBN = Specific Device Code A = Assembly Location Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location)

PIN CONNECTIONS

out

2GND

3EN

MARKING DIAGRAM

DBNAYWG

bat

Typical Applications

• LED Display Back Light Control

• Keyboard Back Light

• High Efficiency Step Up Converter

(Top View)

ORDERING INFORMATION

Device Package Shipping†

NCP9003SNT1G TSOP−5

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

3000 Tape & Reel

August, 2006 − Rev. 1

1 Publication Order Number:

NCP9003/D

NCP9003

GND

15 W

bat

22 mH

GNDGND

out

NCP9003

LWT67CD5LWT67CD4LWT67CD3LWT67CD2LWT67C

Figure 1. Typical Application

4.7 mF

MBR0530

GND

1.0 mF

GND

300 k

+200 mV

Thermal Shutdown Current Sense

sense

100 k

CONTROLLER

− +

Band Gap

Figure 2. Block Diagram

GND

bat

out

GND

http://onsemi.com

NCP9003

PIN FUNCTION DESCRIPTION

Pin Pin Name Type Description

1 V

2 GND POWER This pin is the system ground for the NCP9003 and carries both the power and

3 FB ANALOG INPUT This pin provides the output current range adjustment by means of a sense

4 EN DIGITAL INPUT This is an Active−High logic input which enables the boost converter. The built−in

5 V

out

bat

POWER This pin is the power side of the external inductor and must be connected to the

POWER The external voltage supply is connected to this pin. A high quality reservoir

external Schottky diode. It provides the output current to the load. Since the boost converter operates in a current loop mode, the output voltage can range up to +24 V but shall not extend this limit. However, if the voltage on this pin is higher than the Over Voltage Protection threshold (OVP) the device comes back to shutdown mode. To restart the chip, one must either send a Low to High sequence on Pin EN, or switch off the V the output voltage to avoid false triggering of the OVP circuit. This capacitor should be 1.0 mF minimum. Ceramic type, (ESR <100 mW), is mandatory to achieve the high end efficiency. This capacitor limits the noise created by the fast transients present in this circuitry. In order to limit the inrush current and to operate with an acceptable start−up time, it is recommended to use any value between 1.0 mF and 8.2 mF capacitor maximum. Care must be observed to avoid EMI through the PCB copper tracks connected to this pin.

the analog signals. High quality ground must be provided to avoid spikes and/or uncontrolled operation. Care must be observed to avoid high−density current flow in a limited PCB copper track. Ground plane technique is recommended.

resistor connected to the analog control or with a PWM control. The dimming function can be achieved by applying a PWM voltage technique to this pin (see Figure 29). The current output tolerance depends upon the accuracy of this resistor. Using a "5% metal film resistor or better, yields a good enough output current accuracy. Note: A built−in comparator switch OFF the DC/DC converter if the voltage sensed across this pin and ground is higher than 700 mV (typical).

pull down resistor disables the device when the EN pin is left open. The LED brightness can be controlled by applying a pulse width modulated signal to the enable pin (see Figure 31).

capacitor must be connected across Pin 1 and Ground to achieve the specified output voltage parameters. A 4.7 mF/6.3 V, low ESR capacitor must be connected as close as possible across Pin 5 and ground Pin 2. The X5R or X7R ceramic MURATA types are recommended. The return side of the external inductor shall be connected to this pin. Typical application will use a 22 mH, size 1008, to handle the 1.0 to 100 mA max output current range. On the other hand, when the desired output current is above 20 mA, the inductor shall have an ESR < 1.5 W to achieve a good efficiency over the V

bat

range.

supply. A capacitor must be used on

bat

http://onsemi.com

NCP9003

MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply V

Output Power Supply Voltage Compliance V

Digital Input Voltage

bat

out

EN −0.3 < Vin < V

Digital Input Current

ESD Capability (Note 1)

ESD

Human Body Model (HBM) Machine Model (MM)

TSOP−5 Package

Power Dissipation @ T Thermal Resistance, Junction−to−Air

Operating Ambient Temperature Range T

Operating Junction Temperature Range T

Maximum Junction Temperature T

Storage Temperature Range T

= +85°C (Note 2)

Jmax

stg

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22−A114 Machine Model (MM) "200 V per JEDEC standard: JESD22−A115

2. The maximum package power dissipation limit must not be exceeded.

3. Latch−up current maximum rating: "100 mA per JEDEC standard: JESD78.

4. Moisture Sensivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.

6.0 V

28 V

+ 0.3

bat

1.0

2.0

200

160 250

°C/W

−25 to +85 °C

−25 to +125 °C

+150 °C

−65 to +150 °C

POWER SUPPLY SECTION (Typical values are referenced to T

= +25°C, Min & Max values are referenced −25°C to +85°C ambient

temperature, unless otherwise noted.)

Rating Pin Symbol Min Typ Max Unit

Power Supply 4 V

Output Load Voltage Compliance 5 V

Continuous DC Current in the Load @ V

ESR < 1.5 W, V

Stand By Current, @ I

Inductor Discharging Time @ V

= 10 mA

out

= 3.60 V

bat

= 0 mA, EN = L, V

out

= 0 mA, EN = L, V

out

= 3.6 V, L = 22 mH, 3xLED,

bat

= 3xLED, L = 22 mH,

out

= 3.6 V 4 I

bat

= 5.5 V 4 I

bat

5 I

4 Toffmax − 320 − ns

Thermal Shutdown Protection − T

Thermal Shutdown Protection Hysteresis − T

bat

out

stdb

SDH

2.7 − 5.5 V

21 24 − V

50 − − mA

− 0.3 − mA

− 0.8 3.0 mA

− 160 − °C

− 30 − °C

http://onsemi.com

NCP9003

ANALOG SECTION (Typical values are referenced to T

temperature, unless otherwise noted.)

Rating Pin Symbol Min Typ Max Unit

High Level Input Voltage Low Level Input Voltage

EN Pull Down Resistor 4 R

Feedback Voltage Threshold 3 FB 185 200 225 mV

Output Current Stabilization Time Delay following a DC/DC Start−up,

@ V

= 3.60 V, L = 22 mH, I

bat

Internal Switch ON Resistor @ Tamb = +25°C 1 QR

5. The overall tolerance depends upon the accuracy of the external resistor.

= 20 mA

out

= +25°C, Min & Max values are referenced −25°C to +85°C ambient

4 EN 1.3

1 I

outdly

DSON

−

− 100 − kW

− 100 − ms

− 1.7 − W

−

0.4

ESD PROTECTION

The NCP9003 includes silicon devices to protect the pins against the ESD spikes voltages. To cope with the different ESD voltages developed in the applications, the built−in structures have been designed to handle "2.0 kVin Human Body Model (HBM) and "200 V in Machine Model (MM) on each pin.

means of a current loop, the output voltage will varies depending upon the dynamic impedance presented by the load.

Considering high intensity LED, the output voltage can range from a low 6.40 V (two LED in series biased with a low current), up to 21 V, the voltage compliance the chip can sustain continuously.

DC/DC OPERATION

The DC/DC converter is designed to supply a constant current to the external load, the circuit being powered from a standard battery supply. Since the regulation is made by

The basic DC/DC structure is depicted in Figure 3. With a 28 V maximum rating voltage capability, the power device can accommodate high voltage source without any leakage current downgrading.

bat

V V

LOGIC

CONTROL

POR

TIME_OUT

ZERO_CROSSING

RESET

L1 22 mH

sense

GND

sense

V(Ipeak)

−

Vref

GND

Vds

1.0 mF

GND

R2 xR

D5 D4 D3 D2

GND

Figure 3. Basic DC/DC Converter Structure

http://onsemi.com

NCP9003

Basically, the chip operates with two cycles:

Cycle #1: time t1, the energy is stored into the inductor

Cycle #2: time t2, the energy is dumped to the load

The POR signal sets the flip−flop and the first cycle takes

place. When the current hits the peak value, defined by the

First Start−Up Normal Operation

0 mA

Ids

0 mA

Figure 4. Basic DC−DC Operation

error amplifier associated to the loop regulation, the flip−flop resets, the NMOS is deactivated and the current is dumped into the load. Since the timings depend on the environment, the internal timer limits the toff cycle to 320 ns (typical), making sure the system operates in a continuous mode to maximize the energy transfer.

Ipeak

t1 t2

Based on the data sheet, the current flowing into the

inductor is bounded by two limits:

• Ipeak Value: Internally fixed to 350 mA typical

• Iv Value: Limited by the fixed Toff time built in the

chip (320 ns typical)

The system operates in a continuous mode as depicted in Figure 4 and t1 and t2 times can be derived from basic equations. (Note: The equations are for theoretical analysis only, they do not include the losses.)

dI dt

(Ip * Iv) * L

bat

(Ip * Iv) * L

Vo * V

bat

Let V

= E, then:

bat

L + E*

t1 +

t2 +

Since t2 = 320 ns typical and Vo = 21 V maximum, then (assuming a typical V

DImax +

= 3.0 V):

bat

t2 * (Vo * V

DI +

320 ns * (21−3.0)

22 mH

bat)

+ 261 mA

Of course, from a practical stand point, the inductor must be sized to cope with the peak current present in the circuit

(eq. 1)

(eq. 2)

(eq. 3)

(eq. 4)

to avoid saturation of the core. On top of that, the ferrite material shall be capable to operate at high frequency (1.0 MHz) to minimize the Foucault’s losses developed during the cycles.

The operating frequency can be derived from the

electrical parameters. Let V = Vo − V

, rearranging

bat

Equation 1:

ton +

dI * L

(eq. 5)

Since toff is nearly constant (according to the 320 ns typical time), the dI is constant for a given load and inductance value. Rearranging Equation 5 yields:

V*dt

Let E = V

ton +

, and Vopk = output peak voltage, then:

bat

ton +

(Vopk * V

bat

)*dt

(eq. 6)

(eq. 7)

Finally, the operating frequency is:

f +

ton ) toff

(eq. 8)

The output power supplied by the NCP9003 is limited to one watt: Figure 5 shows the maximum power that can be delivered by the chip as a function of the output voltage.

http://onsemi.com

1200

1000

out

2 LED

= f(V

NCP9003

) @ Rs = 2.0 W I

bat

400

3 LED

350

peak

= f(V

bat

) @ L

= 22 mH

out

800

600

(mW)

out

5 LED

4 LED

400

200

= f(V

bat

(V)

bat

) @ R

out

sense

= 2.0 W

Figure 5. Maximum Output Power as a Function of

the Battery Supply Voltage

120

100

(mA)

out

300

250

Ipeak (mA)

200

150

Test conditions: L = 22 mH, R

Figure 6. Typical Inductor Peak Current as a

2 LED

3 LED

4 LED

5 LED

bat

Function of V

432

(V)

= 10 W, Tamb = +20°C

sense

Voltage

bat

3.0 4.0 5.02.5 3.5 4.5 5.5 V

(V)

bat

Test conditions: L = 22 mH, R

= 2.0 W, Tamb = +25°C

sense

Figure 7. Maximum Output Current as a Function of V

bat

http://onsemi.com

+ 15 hidden pages