ON Semiconductor NCP5008, NCP5009 Technical data

NCP5008, NCP5009

l

s

l

l

Backlight LED Boost Driver

The NCP5008/NCP5009 is a high efficiency boost converter
operating in current loop control mode to drive Light Emitting
Diode. The current mode regulation allows a uniform brightness of
the LEDs.

Features

• 2.7 to 6.0 V Input Voltage Range

• Output Voltage from V

to 15 V

bat

• 3.0 mA Quiescent Supply Current

• Automatically LEDs Current Matching

• No External Sense Resistor

• Includes Dimming Function

• Programmable or Automatic Current Output Mode

• LOCAL or REMOTE Control Facility

• Photo Transistor Sense Feedback Input

• Inductor Based Converter brings High Efficiency

• Low Noise DC/DC Converter

• All Pins are Fully ESD Protected

• Pb−Free Package is Available

T ypical Applications

• LED Display Back Light Control

• High Efficiency Step Up Converter

R1

30 k

GND

Q1

NPN−PHOTO

GND

GND

LED

GND

Vcc

MICROCONTROLLER

Figure 1. Typical Battery Powered LED Boost Driver

© Semiconductor Components Industries, LLC, 2006

April, 2006 − Rev. 7

U1

1

I

ref

2

PHOTO

V

bat

4

4 8

VBIAS

3

CS

5 6

CLK
NCP5009

D1

D2

LED

C2

2.2 mF/16 V

GND

LOCAL

D3

LED

10

V

bat

9

L1

L2

7

D4

LED

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Micro 10

DM SUFFIX

1

(Note: Microdot may be in either location)

CASE 846B

5Tx = Device Number

x = 8 or 9
A = Assembly Location
Y = Year
W = Work Week
G = Pb−Free Package

PIN CONNECTIONS

I

110

ref

NC

2

V

bat

C1

10 mF/6.3 V

GND

L1

22 mH

D5 MBR0520

GND

CS

VBIAS

CLOCK

I

Photo

CS

VBIAS

CLOCK

3
4
5 LOCAL

NCP5008

110

ref

2
3
4
5

NCP5009

ORDERING INFORMATION

Device Package Shipping

NCP5008DMR2 Micro 10
NCP5008DMR2G

NCP5009DMR2 Micro 10
†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

1 Publication Order Number:

Micro 10

(Pb−Free)

4000 / Tape & Ree
4000 / Tape & Ree

4000 / Tape & Ree

MARKING
DIAGRAM

AYW G

1

V

bat

L1

9
8

L2 Iout

7

GND

6

V

bat

L1

9
8

L2 Iout

7

GND

6

LOCAL

NCP5008/D

5Tx

G

†

NCP5008, NCP5009

BACK LIGHT WHITE LED CURRENT DRIVE CONTROLLER

V

bat

VBIAS

CLK

CS

LOCAL

I

ref

PHOTO

(See Note)

4

5

3

6

1
2

BandGap

50 k

V

bat

V

bat

50 k

Q2

10

V

bat

L1

9

Latches

Serial To Parallel

POR

1:8

Selection
V

V

bat

POR

R1

1R8

+

A=10

Isense

−

Iout Reference

V

bat

ref

GND

POR

ref

V

V

bat

Iout

L2

8

Q1

CONTROLLER

GND

7

GND

V

bat

V

bat

+

V

_OK

bat

−

BANDGAP

REFERENCE

GND

NOTE: This functionality is NOT implemented on the NCP5008 type.

Figure 2. Block Diagram

BandGap

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2

NCP5008, NCP5009

PIN FUNCTION DESCRIPTION

Pin Symbol Type Description

1 I

ref

2 PHOTO SIGNAL This pin provides an access to the output current control loop for the NCP5009 version. The cur-

3 CS INPUT Negative going Chip Select logic input. This pin is used to select the NCP5008/ NCP5009 and

4 VBIAS POWER This pin should be connected to V
5 CLOCK INPUT The clock signal connected to this pin is used to serially shift right the internal preset high logic

6 LOCAL INPUT This pin is used to select the mode of operation.

7 GND POWER This pin is the system ground for the NCP5008/NCP5009 and carries both the Power and the

8 L2 POWER This pin is the power side of the external inductor and must be connected either to the external

9 L1 POWER The return side of the external inductor shall be connected to this pin. Typical application will use a

10 V

bat

INPUT This pin provides the output current range adjustment by means of a resistor connected to

ground. The current output tolerance depends upon the accuracy of this resistor. Using a "1%
metal film resistor, or better, yields the best output current accuracy.

rent sunk to ground from this pin is subtracted from the output current mirror. Primary use is the
ambient light automatic adjustment by means of an external photo transistor connected across
this pin and ground. The output current decreases as the ambient light increases. The internal
circuit provides a 1/1 current ratio with the I
ground. This current shall be limited to 65 mA.

defined by the resistor connected from pin 1 to

ref

This functionality is NOT implemented on the NCP5008 type.

validate the clock/data when CS = Low. The internal shift register is automatically clear to zero
upon the falling edge, thanks to a 20 ns built−in one shoot. The built−in pull−up resistor disables
the device when the CS pin is left open.

.

bat

level. The clock is valid between the falling edge and until the rising edge of the CS. There is nei­ther a feedback nor an overflow control. If the clock count exceeds 8 bits, the internal register is
clear, the output current is forced to zero and the device comes back to the shutdown mode.

• When LOCAL = High or Open, the chip is controlled by two digital lines:CS and CLOCK. The
output current is programmed by the logic control of these pins, allowing a current adjustment

within the range defined by the I

resistor.

ref

• When LOCAL = Low, the chip is turned ON /OFF by means of the CS line, the CLOCK pins
being deactivated. The output current is constant, as defined by the I

resistor value.

ref

In order to minimize the standby current a dynamic pull−up resistor is activated when POR is
High, this pull−up resistor being disconnected when LOCAL = Low.

Digital signals. High quality ground must be provided to avoid spikes and/or uncontrolled opera­tion. Care must be observed to avoid high−density current flow in a limited PCB copper track.

Schottky diode (see Figure 22) or directly to one external LED (see Figure 23). It provides the
output current to the load. Since the boost converter operates in a current loop mode, the output
voltage can range up to +15 V but shall not extend this limit. The user must make sure this voltage
will not be exceeded during the normal operation of this part.

An external low cost ceramic capacitor (2.2 mF/16 V , ESR < 100 mW) is recommended to smooth
the current flowing into the diode(s), thus limiting the noise created by the fast transients present
in this circuitry.

Care must be observed to avoid EMI though the PCB copper tracks connected to this pin.

22 mH, size 1210, to handle the 2.8 to 364 mA max range. On the other hand, when the desired
output current is above 20 mA, the inductor shall have an ESR < 1.0 W. The output current toler­ance can be improved by using a larger inductor value.

POWER The external voltage supply is connected to this pin. A high quality reservoir capacitor must be

connected across pin 10 and Ground to achieve the specified output voltage parameters. A
10 mF/6.3 V , low ESR capacitor must be connected as close as possible across pin 10 and
ground pin 7. The X5R ceramic types are recommended.

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3

NCP5008, NCP5009

T able 1. Shift Register Bits Assignment and Functions

SetReg shift register (Note: The register content is latched upon CS positive going).

B7 B6 B5 B4 B3 B2 B1

Bn Value After POR 0 0 0 0 0 0 0
Iout Peak (mA) I

LOCAL CLOCK CS B1−B7 Output Current

L X H X 0

L X L X I
H or Open X H No Change I
H or Open ↓ L No Change I
H or Open ↑ L Q

The register is clear to 0 during the first 20 ns following the CS falling edge.

Note:

Coefficient Value (internal ratio): k = 746
Maximum output peak current @ B7 = 1 and Iphoto = 0 mA :Iout peak = I

V

ref

R1

+

1.24 V
R1

I

+

ref

*k*7.5 I

ref

*k*6.5 I

ref

*k*5.5 I

ref

data

*k*4.5 I

ref

*k*3.5 I

ref

→ Bn I

* (7 + 0.5) * 746 = I

ref

*k*2.5 I

ref

* k

ref

* k * (Bn + 0.5)

ref

* k * (Bn + 0.5)

ref

* k * (Bn + 0.5)

ref

ref

* 5595

ref

*k*1.5

MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply V
Output Power Supply Voltage Compliance V
Digital Input Voltage

Digital Input Current
Human Body Model: R = 1500 W, C = 100 pF ESD "2.0 kV
Machine Model ESD "200 V
Micro 10 Package

Power Dissipation @ T
Thermal Resistance, Junction−to−Air

= +85°C

A

Operating Ambient Temperature Range T
Operating Junction Temperature Range T
Maximum Junction Temperature T
Storage Temperature Range T

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

bat

, V

BIAS

L2

7.0 V
16 V

CLK, CS −0.3 tV tV

1.0

R

Jmax

P

Thja

stg

D

A

J

200
200

−25 to +85 °C

−25 to +125 °C
+150 °C

−65 to +150 °C

+ 3.0 V

bat

V

mA

mW

°C/W

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4

NCP5008, NCP5009

POWER SUPPLY SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)

Rating Pin Symbol Min Typ Max Unit

Power Supply 10 V
Power Supply Threshold Startup Voltage 10 V
Output Load Voltage Compliance 8 V
Pulsed Current Regulation Range 8 I
Continuous DC Current in the Load 8 I
Output Pulsed Current Tolerance @ V

R

ref

"1%, I

= 20 mA (Note 1)

LED

Output Leakage @ LOCAL = 0, CS = H, Vout = 15 V, V
Standby Current @ Iout = 0 mA, CS = H, CLK = H, V
Standby Current @ Iout = 0 mA, CS = H, CLK = H, V
Operating Current @ V

LOCAL = Open

bat

= V

BIAS

Boost Internal Oscillator Clock @ L1 = 22 mH, V
Iout = 20 mA (Vout = 14 V)

= 3.6 V , L1 = 22 mH/0.71 W,

bat

bat
bat

= 3.6 V , I

= 30 mA, CLK = H, CS = L,

ref

= V

bat

8 I

= 6.0 V 8 I

bat

= V

= 3.6 V 10 I

BIAS

= V

= 6.0 V 10 I

BIAS

10 I

BIAS

= 3.6 V ,

− F

1. The tolerance refers to the 20 mA to 70 mA current range.

DIGITAL SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)

Rating Pin Symbol Min Typ Max Unit

High Level Input Voltage (Note 2)
Low Level Input Voltage (Note 2)
Input Capacitance

High Level Input Voltage (Note 2)
Low Level Input Voltage (Note 2)
Input Capacitance

LOCAL Pullup Resistor 6 R
LOCAL Leakage Current 9 I
CS Pullup Resistor 3 R
Minimum CS Low Time 3 Tcs
Clock Frequency 5 F
CLOCK tr and tf 5 tr
Internal Register Clear − t
Internal Power on Reset Width − t

2. Digital inputs undershoot < − 0.30 V, Digital inputs overshoot < 0.30 V.

3, 5 V

6 V

batThr

out
out
out

out
stdb
stdb

ope

osc

V
C

V
C

Loc

CLK

CLK

clear
POR

bat

out

IH
IL

in

IH
IL

in

loc

cs

setup

, tf

CLK

2.7 − 6.0 V

− 2.3 2.7 V

− − 15.0 V
0 − 400 mA

− − 75 mA

− "5.0 − %

− − 500 nA

− 3.0 − mA

− − 10 mA

− 600 −

− 300 − kHz

0.7*V

bat

−

−

−

−

−

10

0.6*V

0.4*V
10

−

−

bat
bat

V

0.3*V

bat

−

−

−

−

bat

20 − 80 kW

− − 100 nA

20 − 80 kW

250 − − ns

− − 5.0 MHz
10 − − ns
10 30 − ns

− 100 − ms

mA

V
V

pF

V
V

pF

ANALOG SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)

Rating Pin Symbol Min Typ Max Unit

Output Voltage Range Reference @ 2.5 mA < I
Maximum Output Current Range Ratio 8 I
Minimum Output Current Range Ratio 8 I
Output Current Sense Resistor 10, 9 R
Output Voltage Range Reference @ 2.5 mA < Ipho < 65 mA 2 V
Output Current Stabilization tdelay following a DC/DC startup 8 I
Internal NMOS Resistor @ V

= 3.6 V 8 QR

bat

Internal Comparator Delay Time − Td

< 65 mA (Note 3) 1 V

ref

ref
out
out

s

pho

outdly

DSON

comp

1.20 1.24 1.28 V

− 5595 − −

− 1119 − −

− 1.8 5.0 W

1.20 1.24 1.28 V

− 100 − ms

− 2.2 3.0 W

− 60 − ns

3. The overall tolerance depends upon the accuracy of the external resistor. Using a 1%/low PPM metal film resistor is recommended to achieve
"5% output current tolerance.

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5

NCP5008, NCP5009

EFFICIENCY (%)

load

ref

0

5

EFFICIENCY (%)

.5

EFFICIENCY (%)

TYPICAL OPERATING CHARACTERISTICS

Condition: T ypical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW

80

75

V

= 4.2 V

bat

70

V

= 3.6 V

65

bat

60

55

V

bat

= 3.0 V

50

0 5 10 15 20 25 30 35

I

(mA)

LED

Figure 3. Efficiency vs. Load Current @ 4 LEDS

= 4*Vf ⇒ 14.2 V)

(V

load

85

80

75

70

V

bat

= 4.2 V

V

bat

V

= 3.6 V

= 3.0 V

bat

80

75

70

65

60

EFFICIENCY (%)

55

V

= 3.0 V

bat

50

0 5 10 15 20 25 30 3

I

(mA)

LED

Figure 4. Efficiency vs. Load Current @ 3 LEDS

(V

= 3*Vf ⇒ 10.5 V)

load

100

90

80

70

V

bat

V

bat

V

out

I

= 40 mA

led

V

out

I

= 20 mA

led

= 4.2 V

= 3.6 V

=7.5 V

= 15 V

EFFICIENCY (%)

65

60

60

0 5 10 15 20 25 30 35

I

(mA)

LED

Figure 5. Efficiency vs. Load Current @ 2 LEDS

(V

= 2*Vf ⇒ 7.1 V)

load

100

V

= 6.0 V

bat

95

5.0 V

90

85

80

4.2 V

3.6 V

50

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V

(V)

bat

Figure 6. Efficiency vs. V

(mA)

peak

I

400
350
300
250
200
150
100

50

V

out

V

out

= 15 V/I

= 7.5 V/I

= 20mA and

led

= 40 mA

led

bat

6

@

Bn

7
6

5
4

3
2

1

3.0 V

75

0 1020304050 6070

I

(mA)

LED

Figure 7. Efficiency vs. Load Current @ 4 LEDS

= 2 strings of 2 LEDs in series = 7.1V)

(V

0

0 2040608

I

(mA)

ref

Figure 8. Inductor peak Current vs.

I

@ Bn = {1, 2, 3, 4, 5, 6, 7}

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6

0

I

(mA)

I

(mA)

.0

TYPICAL OPERATING CHARACTERISTICS

35

NCP5008, NCP5009

Condition: T ypical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW

50
45
40
35
30
25

LED

20
15
10

5
0

0 10203040506070

I

ref

Figure 9. Load Current (I

@ V

= 3.6 V, V

bat

load

200
180
160

Theoretical

140

Measured

120
100

peak

80
60
40
20

0

0 10203040

I

photo

Figure 11. Inductor Peak Current vs. I

V

= 10 V

load

V

= 15 V

load

(mA)

) vs. I

led

= 15 V and 10 V

(mA)

photo

@ I

ref

ref

= 34 mA

20
18
16
14
12
10

ERROR (%)

8

peak

I

6
4
2
0

0 50 100 150 200 250 300 350 40

THEORETICAL I

peak

(mA)

Figure 10. Inductor Peak Current Error vs.

Theoretical Inductor Peak Current

7.0

6.5

6.0

5.5

(mA)

5.0

stby

I

4.5

4.0

3.5

3.0

2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6
V

(V)

bat

Figure 12. Stand by Current vs. V

@ T = 20°C

bat

6

80

75

70

65

60

EFFICIENCY (%)

55

V

= 3.0 V

bat

50

0 5 10 15 20 25 30 35

I

(mA)

LED

Figure 13. Efficiency vs. Load Current @ 4 LEDS

= 4*Vf ⇒ 14.2 V)

(V

load

V

= 4.2 V

bat

V

= 3.6 V

bat

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85

80

V

= 4.2 V

bat

75

V

= 3.6 V

bat

70

65

EFFICIENCY (%)

60

55

V

= 3.0 V

50

bat

0 5 10 15 20 25 30

I

(mA)

LED

Figure 14. Efficiency vs. Load Current @ 3 LEDS

= 3*Vf ⇒ 10.5 V)

(V

load

7

NCP5008, NCP5009

70

EFFICIENCY (%)

TYPICAL OPERATING CHARACTERISTICS

Condition: T ypical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW

90

85

80

75

70

65

60

0 5 10 15 20 25 30 35

I

(mA)

LED

Figure 15. Efficiency vs Load Current @ 2 LEDS

= 2*Vf ⇒ 7.1 V)

(V

load

Operating Description

t

CLKmin

V

V

= 4.2 V

bat

V

bat

= 3.0 V

bat

= 3.6 V

100

95

90

4.2 V

85

80

EFFICIENCY (%)

75

70

0102030405060

I

LED

3.0 V

(mA)

Figure 16. Efficiency vs Load Current @ 4 LEDS

(V

= 2 strings of 2 LEDs in series = 7.1 V)

load

Output

V

bat

ON

V

bat

3.6 V

= 6.0 V

5.0 V

90%
50%

10%

Figure 17. Digital Timing Definitions

Input Schmitt Triggers

All the Logic Input pins have built−in Schmitt trigger

circuits to prevent the NCP5008/NCP5009 against

tf tr

OFF

Figure 18. Typical Schmitt Trigger Characteristic

the current drawn pin 1. The clock signal is irrelevant and
the output current is derived by equation I
internal constant k being equal to 746.

0.30* V

bat

0.70* V

batVbat

out

= I

Input

* k, the

ref

uncontrolled ope ration. The typical dynamic characteristics
of the re la te d pins are depi ct e d in Figure 18.

The output signal is guaranteed to go High when the
input voltage is above 0.70*V
input voltage is below 0.30*V

, and will go Low when the

bat

.

bat

Local Mode

When the system operate in a Local Mode (Pin 6,

ESD Protection

The NCP5008/NCP5009 includes silicon devices to
protect the pins against the ESD spikes voltages. To cope
with the different ESD voltages developed in the
applications, the built−in structures have been designed to
handle $2.0 kV in Human Body Model (HBM) and
$200 V in Machine Model (MM) and on each pin.

/LOCAL=Low), the output current depends solely upon

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8

Remote Control Programming Sequence

tCSsetup

CS

CLEAR

CLK

Qdata

B1

B2

B3

B4

NCP5008, NCP5009

tclear

I

out ref

Iout

B5

B6

B7

Output Current Programmed Register

Internal Latch Data and Reset

Last Latched Bit

Figure 19. Programming Sequence

Upon CS transition from High to Low, the internal

sequence will take place:

− Qdata is internally set to high level.

− Upon positive going transition of the next CLK signal,
the Qdata is shifted to the next Bn stage.

− Clear the Qdata flip−flop upon the positive going of
the SetReg[B1] transient.

The sequence keeps going until CS = High.

When the CS line returns to a High state, the
programming output current flip−flop is set according to
the previous state of the shift register and SetReg B[1−7] is
cleared afterward.

Depending upon the CS width, for a given CLK period,
the last SetReg bit will be latched and the output current

Ioutdly

will be adjusted accordingly. If the number of CLK pulses
is higher than 7, the Qdata is lost and the SetReg register
bits B[1−7] are in the Low state, yielding a zero output
current.

The internal shift register can be clear by sending more
than 7 pulses to the CLK pin when the pin CS is low . If the
internal shift register is clear upon the CS transition from
Low to High, the device will be placed or maintained in the
shut down mode.

When the register content is higher than zero, the DC/DC
is activated and a 100 ms delay (typical) is necessary to
stabilize the output current to the programmed value.

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9

Set Up Output Current Range

1 1

V

bat

+

−

V

bat

BandGap

NCP5008, NCP5009

I

ref

V

bat

R

ref

30 k

GND

Q1
NPN−PHOTO

GND

I

ref

Photo

GND

V

bat

1

V

bat

+

BandGap

−

GND

Iphoto

1

1

GND GND

1

1

GND GND

1

I = (I

ref

1:Bn

1:746

= (I

−Iphoto)*(Bn+0.5)

2:1

GND

Iout Reference

−Iphoto)*746*(Bn+0.5)

ref

Figure 20. Functional Diagram

The current sunk to ground on PHOTO pin is subtracted

from the current sunk to ground on I

pin. The result is

ref

multiplied by the programmed value (Bn) and then
multiplied by the constant factor ratio (k = 746) in the
current mirror.

The constant factor k is a ratio between the current on

Iout sense and the Iout reference internally fixed.
The output current reference is:

Ipeak = Ivalley + (I

− Iphoto) * Bn * k.

ref

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Where k = 746, Bn represents the bit of the internal shift
register, range from 1 to 7, and Ivalley = (I

− Iphoto)

ref

* 0.5 * k.
We can write also Ipeak = (I

− Iphoto) * (Bn + 0.5) * k.

ref

Please find below the formula to quickly calculate R1
resistor (resistor on I

10

ref

pin):

I

ref

+

1.24
R1

NCP5008, NCP5009

DC/DC Converter Operation

The DC/DC converter operates with a boost structure
depicted in Figure 21, the load being supplied by the pulsed
current coming from the external inductor L1. The current

V

bat

+

U4

−

V

bat

GND

+

U2

−

GND

U5

U3

U6

I

peak_ref

I

valley_ref

POR

is monitored by the internal sense resistor Rsense to Set and
Reset the flip−flop U3 and U6 according to the comparators
U2 and U4 output state.

V

bat

V

bat

U1

GND

+

−

U7

Rsense
1R8

Q1

GND

V

bat

L1

L2

C2

2.2 mF/16 V

L1
22 mH

D5
MBR0520

D4
LED

D3
LED

D2
LED

GND

Figure 21. Basic DC/DC Boost Structure

D1
LED

GND

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11

NCP5008, NCP5009

Output Load Drive

In order to make profit of the built−in Boost capabilities,
one shall operate the NCP5008/NCP5009 in the continuous
output current mode. Such a mode is achieved by using and
external reservoir capacitor (preferably a low ESR ceramic
type) across the LED as depicted in Figures 22, 23, 24, 25,
and 26.

Using an extra photo sensor is not mandatory and the
related pin 2 can be either left open or connected to V

bat

but must not be grounded on the NCP5009 version only.

At this point, the designer must carefully analyze two
parameters:

1. The output voltage must be limited to 15 V
maximum. It’s the designer responsibility to
make sure that spike voltages beyond the

TYPICAL APPLICATION CIRCUIT

R1

30 k

GND

1
2

U1
I

ref

PHOTO

maximum rating will not exist across pin 8 and
ground. Depending upon a specific application
(V

voltage, PCB layout…), using an external

bat

voltage clamp could be necessary.

2. The peak current flowing into the LED diodes
shall be within the maximum ratings specified for
these devices.

The Schottky diode D5, associated with capacitor C2,

,

provides a rectification and filtering function.

When a pulse−operating mode is acceptable:

• The LEDs brightness can be controlled in LOCAL

mode with a PWM on CS pin as depicted in Figure 24.

• Or the Schottky can be removed and replaced by at

least one LED diode as depicted in Figure 23.

V

bat

C1

10

V

bat

9

L1

10 mF/6.3 V

GND

Vcc

MICROCONTROLLER

Q1

NPN−PHOTO

GND

Figure 22. Basic DC Current Mode Operation in REMOTE Control

GND

V

bat

4

4 8

VBIAS

3

CS

5 6

CLK
NCP5009

D1

LED

GND

D2

LED

L2

GND

LOCAL

D3

LED

C2

2.2 mF/16 V

L1
22 mH

D5 MBR0520

7

GND

D4

LED

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12

GND

R1

30 k

NCP5008, NCP5009

U1

1
2

I

ref

PHOTO

V

bat

L1

10

V

bat

C1

10 mF/6.3 V

GND

9

Vcc

Q1

NPN−PHOTO

MICROCONTROLLER

GND

Figure 23. Typical Semi−Pulsed Mode of Operation in REMOTE Mode

GND

R1

30 k

GND

V

bat

4

4 8

VBIAS

3

CS

5 6

CLK
NCP5009

U1

1

I

ref

2

PHOTO

L2

GND

LOCAL

GND

V

bat

L1

7

GND

LED

1.0 mF/16 V

10

9

D3

C2

V

L1
22 mH

bat

10 mF/6.3 V

D4

LED

C1

GND

Q1

NPN−PHOTO

V

bat

L1
22 mH

GND

4

PWM

4 8

VBIAS

3

CS

5 6

CLK

L2

GND

LOCAL

7

NCP5009

GND

D1

LED

D2

LED

D3

LED

D4

LED

C2

2.2 mF/16 V

GND

Figure 24. PWM Current Control Mode Operation in LOCAL Mode

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13

D5 MBR0520

DAC

R1

30 k

1
2

NCP5008, NCP5009

U1
I

ref

PHOTO

V

bat

L1

10

V

bat

C1

10 mF/6.3 V

GND

9

Q1

NPN−PHOTO

Figure 25. DAC Current Control Mode Operation in LOCAL Mode

GND

GND

OFF ON

R1

30 k

V

bat

4

4 8

VBIAS

3

CS

5 6

CLK
NCP5009

D1

LED

D2

LED

GND

U1

1

I

ref

2

PHOTO

L2

GND

LOCAL

D3

LED

C2

2.2 mF/16 V

V

7

bat

L1

10

9

GND

D4

LED

L1
22 mH

V

bat

D5 MBR0520

C1

10 mF/6.3 V

GND

Q1

NPN−PHOTO

V

bat

GND

OFF ON

4 8

VBIAS

3

CS

5 6

CLK

L2

GND

LOCAL

7

4

NCP5009

GND

D1

LED

D2

LED

D3

LED

C2

GND

2.2 mF/16 V

Figure 26. Basic DC Current Mode Operation in LOCAL Mode

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14

L1
22 mH

D5 MBR0520

D4

LED

TYPICAL LEDS LOAD MAPPING

bat

Load+

75 mA

6.7 V

D1

LED

D2

LED

NCP5008, NCP5009

D3

LED

D4

LED

D5

LED

D6

LED

D7

LED

D8

LED

D9

LED

D10
LED

Load+

GND

60 mA

D1

LED

6.7 V
D2

LED

GND GND

D3

LED

D4

LED

Example 2

D5

LED

D6

LED

Example 1

Load+

50 mA

10.4 V

D1

LED

D2

LED

D3

LED

Example 3

Figure 27. Three different examples of load can be driven by the NCP5009 or NCP5008

Condition: V

= 3.6 V, L = 22 mH

D4

LED

D5

LED

D6

LED

D7

LED

D8

LED

D9

LED

MANUFACTURER REFERENCE

Design Ref Value/Reference or Size Manufacturer Reference Number

D5 MBR0520/SOD−123 ON Semiconductor MBR0520

L1 22 mH/1210 MURATA LQH3C220K34
C1 10 mF/ 6.3 V/0805 MURATA GRM40 X5R 106K 6.3
C2 2.2 mF/16 V/1206 MURATA GRM42−6 X7R 225K 16
Q1 SFH320/PLCC2 Osram SFH320

D1 to D4 White LED Osram LW5413−VBW−1

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15

LAYOUT EXAMPLE

NCP5008, NCP5009

Figure 28. Typical Printed Circuit Layout

(the Top Silk Screen and the Top Layer)

The Figure 28 represents the typical printed circuit
layout based on the basic application Figure 1. This
application has been routed on a single copper layer to save
cost. A dual side PCB has better noise protection and can
be the right choice for an industrial system. In order to
avoid voltage spikes, care must be observed to group the
capacitors, the inductor, the Schottky diode and the

integrated circuit in the same area. On the other hand, using
large copper tracks to reduce the resistor connectivity is
strongly recommended.

Obviously, the connectors GND, CLK, CS, V

bat

and
Load are for engineering purpose only and not for final
application.

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16

0.038 (0.0015)

−T−

SEATING
PLANE

PIN 1 ID

NCP5008, NCP5009

PACKAGE DIMENSIONS

Micro10

CASE 846B−03

ISSUE D

−A−

K

G

−B−

D

8 PL

0.08 (0.003) A

M

S

B

T

S

C

H

J

L

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.

4. DIMENSION “B” DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. 846B−01 OBSOLETE. NEW STANDARD
846B−02

DIM MIN MAX MIN MAX

A 2.90 3.10 0.114 0.122
B 2.90 3.10 0.114 0.122
C 0.95 1.10 0.037 0.043
D 0.20 0.30 0.008 0.012
G 0.50 BSC 0.020 BSC
H 0.05 0.15 0.002 0.006

J 0.10 0.21 0.004 0.008

K 4.75 5.05 0.187 0.199

L 0.40 0.70 0.016 0.028

INCHESMILLIMETERS

SOLDERING FOOTPRINT*

1.04

10X 10X

0.041

3.20

0.126

0.50

8X

0.0196

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

0.32

0.0126

4.24

0.167

SCALE 8:1

5.28

0.208

mm

ǒ

inches

Ǔ

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [e-mail]

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Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

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17

ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your
local Sales Representative.

NCP5008/D