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NCP2820
Technical data
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ON Semiconductor NCP2820 Technical data

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NCP2820
2.65 W Filterless Class−D Audio Power Amplifier
The NCP2820 is a cost−effective mono Class−D audio power
The NCP2820 processes analog inputs with a pulse width modulation technique that lowers output noise and THD when compared to a conventional sigma−delta modulator. The device allows independent gain while summing signals from various audio sources. Thus, in cellular handsets, the earpiece, the loudspeaker and even the melody ringer can be driven with a single NCP2820. Due to its low 42V noise floor, A−weighted, a clean listening is guaranteed no matter the load sensitivity.
Features
• Optimized PWM Output Stage: Filterless Capability
• Efficiency up to 90%
Low 2.5 mA Typical Quiescent Current
• Large Output Power Capability: 1.4 W with 8.0  Load (CSP) and
THD + N < 1%
• Wide Supply Voltage Range: 2.5−5.5 V Operating Voltage
• High Performance, THD+N of 0.03% @ V
R
= 8.0 , P
L
= 100 mW
out
• Excellent PSRR (−65 dB): No Need for Voltage Regulation
• Surface Mounted Package 9−Pin Flip−Chip CSPand UDFN8
• Fully Differential Design. Eliminates Two Input Coupling Capacitors
• Very Fast Turn On/Off Times with Advanced Rising and Falling
Gain Technique
• External Gain Configuration Capability
• Internally Generated 250 kHz Switching Frequency
• Short Circuit Protection Circuitry
• “Pop and Click” Noise Protection Circuitry
• Pb−Free Packages are Available
Applications
• Cellular Phone
• Portable Electronic Devices
• PDAs and Smart Phones
• Portable Computer
= 5.0 V,
p
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MARKING
DIAGRAMS
AYWW
C1
ZB MG
A3
MAQG
Cs
1
9−PIN FLIP−CHIP CSP
1
FC SUFFIX
CASE 499AL
8
1
8 PIN UDFN 2x2.2
MU SUFFIX
CASE 506AV
A = Assembly Location Y = Year WW = Work Week M = Date Code G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of this data sheet.
Audio
Input
from
DAC
Microcontroller
1.6 mm
R
R
Input from
R
R
i
INP
i
INM
SD
GND
i
i
3.7 mm
A1
1
VP
OUTM
OUTP
Cs
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 5
1 Publication Order Number:
NCP2820/D
9−Pin Flip−Chip CSP
NCP2820
PIN CONNECTIONS
UDFN8
Negative
Differential
Input
8
7
6
5
OUTM
GND
VP
OUTP
INM
A1
B1
VP
C1
A2
A3
GNDINP OUTM
B2
VP
C2
SD
B3
GND
C3
OUTP
SD
VP
INP
INM
1
2
3
4
(Top View)
(Top View)
BATTERY
Cs
V
p
R
i
INM
R
f
OUTP
RAMP
GENERATOR
Data
Processor
CMOS Output
Stage
8
= L
R
OUTM
Positive
Differential
Input
R
i
INP
R
f
300 k
Shutdown
Control
GND
SD
V
ih
V
il
Figure 1. Typical Application
PIN DESCRIPTION
Pin No.
CSP UDFN8
A1 3 INP I Positive Differential Input.
A2 7 GND I Analog Ground.
A3 8 OUTM O Negative BTL Output.
B1 2 V
B2 6 V
B3 7 GND I Analog Ground.
C1 4 INM I Negative Differential Input.
C2 1 SD I The device enters in Shutdown Mode when a low level is applied on this pin. An internal
C3 5 OUTP O Positive BTL Output.
Symbol Type Description
p
p
I Analog Positive Supply. Range: 2.5 V – 5.5 V.
I Power Analog Positive Supply. Range: 2.5 V – 5.5 V.
300 k resistor will force the device in shutdown mode if no signal is applied to this pin. It also helps to save space and cost.
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2
NCP2820
MAXIMUM RATINGS
Symbol Rating Max Unit
V
p
V
in
I
out
P
d
T
A
T
J
T
stg
R
JA
−
−
− Latchup Current @ TA = 85°C (Note 6) 9−Pin Flip−Chip
MSL Moisture Sensitivity (Note 7) Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
1. The device is protected by a current breaker structure. See “Current Breaker Circuit” in the Description Information section for more
information.
2. The thermal shutdown is set to 160°C (typical) avoiding irreversible damage to the device due to power dissipation.
3. For the 9−Pin Flip−Chip CSP package, the R
2
total area and also 135°C/W with 500 mm2. When using ground and power planes, the value is around 90°C/W, as specified in table.
50 mm
4. Human Body Model: 100 pF discharged through a 1.5 k resistor following specification JESD22/A114. On 9−Pin Flip−Chip, B2 Pin (V
is qualified at 1500 V.
5. Machine Model: 200 pF discharged through all pins following specification JESD22/A115.
6. Latchup Testing per JEDEC Standard JESD78.
7. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
Supply Voltage Active Mode
Shutdown Mode
6.0
7.0
Input Voltage −0.3 to VCC +0.3 V
Max Output Current (Note 1) 1.5 A
Power Dissipation (Note 2) Internally Limited −
Operating Ambient Temperature −40 to +85 °C
Max Junction Temperature 150 °C
Storage Temperature Range −65 to +150 °C
Thermal Resistance Junction−to−Air 9−Pin Flip−Chip
UDFN8
90 (Note 3)
50
°C/W
ESD Protection
Human Body Model (HBM) (Note 4)
Machine Model (MM) (Note 5)
is highly dependent of the PCB Heatsink area. For example, R
JA
UDFN8
> 2000
> 200
$70
$100
can equal 195°C/W with
JA
mA
V
V
)
P
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3
NCP2820
ELECTRICAL CHARACTERISTICS (Limits apply for T
Characteristic
Operating Supply Voltage V
Supply Quiescent Current I
Shutdown Current I
Shutdown Voltage High V
Shutdown Voltage Low V
Switching Frequency F
Gain G
Output Impedance in Shutdown Mode Z
Resistance from SD to GND Rs − − 300 −
Symbol Conditions Min Typ Max Unit
p
dd
sd
sdih
sdil
sw
SD
= +25°C unless otherwise noted) (NCP2820FCT1G and NCP2820FCT2G)
A
TA = −40°C to +85°C 2.5 − 5.5 V
Vp = 3.6 V, RL = 8.0
V
= 5.5 V, No Load
p
V
from 2.5 V to 5.5 V, No Load
p
= −40°C to +85°C
T
A
−
−
−
2.15
2.61
−
−
−
4.6
Vp = 4.2 V
T
= +25°C
A
T
= +85°C
A
−
−
0.42
0.45
0.8
−
Vp = 5.5 V
T
= +25°C
A
T
= +85°C
A
Vp from 2.5 V to 5.5 V
T
= −40°C to +85°C
A
RL = 8.0 285 k
−
−
0.8
0.9
1.5
−
1.2 − − V
− − 0.4 V
190 250 310 kHz
300 k
R
i
315 k
R
i
R
i
− 300 −
mA
A
A
k
Output Offset Voltage Vos Vp = 5.5 V − 6.0 − mV
Turn On Time To n Vp from 2.5 V to 5.5 V − 9.0 − ms
Turn Off Time To ff Vp from 2.5 V to 5.5 V − 5.0 − ms
Thermal Shutdown Temperature Ts d − − 160 − °C
Output Noise Voltage Vn V
RMS Output Power Po
= 3.6 V, f = 20 Hz to 20 kHz
p
no weighting filter
with A weighting filter
RL = 8.0 , f = 1.0 kHz, THD+N < 1%
V
= 2.5 V
p
= 3.0 V
V
p
V
= 3.6 V
p
V
= 4.2 V
p
V
= 5.0 V
p
Vrms
−
−
−
−
−
−
−
65 42
0.32
0.48
0.7
0.97
1.38
−
−
−
−
−
−
−
RL = 8.0 , f = 1.0 kHz, THD+N < 10%
V
p
V
p
V
p
V
p
V
p
= 2.5 V = 3.0 V = 3.6 V = 4.2 V = 5.0 V
−
−
−
−
−
0.4
0.59
0.87
1.19
1.7
−
−
−
−
−
RL = 4.0 , f = 1.0 kHz, THD+N < 1%
V
p
V
p
V
p
V
p
V
p
= 2.5 V = 3.0 V = 3.6 V = 4.2 V = 5.0 V
−
−
−
−
−
0.49
0.72
1.06
1.62
2.12
−
−
−
−
−
RL = 4.0 , f = 1.0 kHz, THD+N < 10%
V
p
V
p
V
p
V
p
V
p
= 2.5 V = 3.0 V = 3.6 V = 4.2 V = 5.0 V
−
−
−
−
−
0.6
0.9
1.33
2.0
2.63
−
−
−
−
−
V V
W
W
W
W
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4
NCP2820
ELECTRICAL CHARACTERISTICS (Limits apply for T
= +25°C unless otherwise noted) (NCP2820FCT1G and NCP2820FCT2G)
A
Characteristic UnitMaxTypMinConditionsSymbol
Efficiency −
RL = 8.0 , f = 1.0 kHz
V
= 5.0 V, P
p
= 3.6 V, P
V
p
out out
= 1.2 W = 0.6 W
−
−
91 90
−
−
RL = 4.0 , f = 1.0 kHz
Total Harmonic Distortion + Noise THD+N
V
= 5.0 V, P
p
V
= 3.6 V, P
p
V
= 5.0 V, RL = 8.0 ,
p
f = 1.0 kHz, P
V
= 3.6 V, RL = 8.0 ,
p
f = 1.0 kHz, P
= 2.0 W
out
= 1.0 W
out
= 0.25 W
out
= 0.25 W
out
Common Mode Rejection Ratio CMRR Vp from 2.5 V to 5.5 V
V
= 0.5 V to V
ic
V
= 3.6 V, Vic = 1.0 V
p
− 0.8 V
p
f = 217 Hz
f = 1.0 kHz
Power Supply Rejection Ratio PSRR
V
p_ripple_pk−pk
= 200 mV, RL = 8.0 ,
−
−
−
−
−
pp
−
−
82 81
0.05
0.09
−62
−56
−57
−
−
−
−
dB
−
−
−
dB
Inputs AC Grounded
V
= 3.6 V
p
f = 217 kHz f = 1.0 kHz
ELECTRICAL CHARACTERISTICS (Limits apply for T
Characteristic
Operating Supply Voltage V
Supply Quiescent Current I
Shutdown Current I
Symbol Conditions Min Typ Max Unit
p
dd
sd
= +25°C unless otherwise noted) (NCP2820MUTBG)
A
TA = −40°C to +85°C 2.5 − 5.5 V
Vp = 3.6 V, RL = 8.0
V
= 5.5 V, No Load
p
V
from 2.5 V to 5.5 V, No Load
p
T
= −40°C to +85°C
A
Vp = 4.2 V
T
= +25°C
A
T
= +85°C
A
Vp = 5.5 V
T
= +25°C
A
T
= +85°C
A
Shutdown Voltage High V
Shutdown Voltage Low V
Switching Frequency F
Gain G
Output Impedance in Shutdown Mode Z
sdih
sdil
sw
SD
Vp from 2.5 V to 5.5 V
T
= −40°C to +85°C
A
RL = 8.0 285 k
Resistance from SD to GND Rs − − 300 −
−
−
−
−
−
−62
−65
2.15
2.61
−
3.8
−
−
−
mA
−
A
−
−
0.42
0.45
0.8
2.0
A
−
−
0.8
0.9
1.5
−
1.2 − − V
− − 0.4 V
180 240 300 kHz
300 k
R
i
− 20 −
315 k
R
i
R
i
k
k
Output Offset Voltage Vos Vp = 5.5 V − 6.0 − mV
Turn On Time To n Vp from 2.5 V to 5.5 V − 1.0 −
Turn Off Time To ff Vp from 2.5 V to 5.5 V − 1.0 −
s
s
Thermal Shutdown Temperature Ts d − − 160 − °C
Output Noise Voltage Vn V
= 3.6 V, f = 20 Hz to 20 kHz
p
no weighting filter
with A weighting filter
Vrms
−
−
65 42
−
−
%
%
V V
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5
NCP2820
ELECTRICAL CHARACTERISTICS (Limits apply for T
= +25°C unless otherwise noted) (NCP2820MUTBG)
A
Characteristic UnitMaxTypMinConditionsSymbol
RMS Output Power Po
RL = 8.0 , f = 1.0 kHz, THD+N < 1%
V
= 2.5 V
p
= 3.0 V
V
p
V
= 3.6 V
p
V
= 4.2 V
p
V
= 5.0 V
p
RL = 8.0 , f = 1.0 kHz, THD+N < 10%
V
= 2.5 V
p
V
= 3.0 V
p
V
= 3.6 V
p
= 4.2 V
V
p
V
= 5.0 V
p
RL = 4.0 , f = 1.0 kHz, THD+N < 1%
V
= 2.5 V
p
V
= 3.0 V
p
V
= 3.6 V
p
V
= 4.2 V
p
V
= 5.0 V
p
RL = 4.0 , f = 1.0 kHz, THD+N < 10%
V
= 2.5 V
p
V
= 3.0 V
p
V
= 3.6 V
p
V
= 4.2 V
p
V
= 5.0 V
p
Efficiency −
RL = 8.0 , f = 1.0 kHz
V
= 5.0 V, P
p
V
= 3.6 V, P
p
out out
= 1.2 W = 0.6 W
RL = 4.0 , f = 1.0 kHz
Total Harmonic Distortion + Noise THD+N
V
= 5.0 V, P
p
V
= 3.6 V, P
p
V
= 5.0 V, RL = 8.0 ,
p
f = 1.0 kHz, P
V
= 3.6 V, RL = 8.0 ,
p
f = 1.0 kHz, P
= 2.0 W
out
= 1.0 W
out
= 0.25 W
out
= 0.25 W
out
Common Mode Rejection Ratio CMRR Vp from 2.5 V to 5.5 V
V
= 0.5 V to V
ic
V
= 3.6 V, Vic = 1.0 V
p
− 0.8 V
p
f = 217 Hz
f = 1.0 kHz
Power Supply Rejection Ratio PSRR
V
p_ripple_pk−pk
= 200 mV, RL = 8.0 ,
Inputs AC Grounded
V
= 3.6 V
p
f = 217 kHz f = 1.0 kHz
−
−
−
−
−
0.22
0.33
0.45
0.67
0.92
−
−
−
−
−
W
W
−
−
−
−
−
0.36
0.53
0.76
1.07
1.49
−
−
−
−
−
W
−
−
−
−
−
0.24
0.38
0.57
0.83
1.2
−
−
−
−
−
W
−
−
−
−
−
0.52
0.8
1.125
1.58
2.19
−
−
−
−
−
%
−
−
−
−
87 87
79 78
−
−
−
−
%
−
−
0.05
0.06
−
−
dB
−
pp
−
−
−62
−56
−57
−
−
−
dB
−
−
−62
−65
−
−
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6
NCP2820
NCP2820
INP
INM
VP
4.7 F
OUTM
OUTP
GND
Load
30 kHz
Low Pass
Filter
Audio Input
Signal
C
+
C
−
Power Supply
R
i
i
i
R
i
+
−
Figure 2. Test Setup for Graphs
NOTES:
1. Unless otherwise noted, C
= 100 nF and Ri= 150 k. Thus, the gain setting is 2 V/V and the cutoff frequency of the
i
input high pass filter is set to 10 Hz. Input capacitors are shorted for CMRR measurements.
2. To closely reproduce a real application case, all measurements are performed using the following loads: RL = 8 means Load = 15 H + 8 + 15 H
= 4 means Load = 15 H + 4 + 15 H
R
L
Very low DCR 15 H inductors (50 m) have been used for the following graphs. Thus, the electrical load measurements are performed on the resistor (8 or 4 ) in differential mode.
3. For Efficiency measurements, the optional 30 kHz filter is used. An RC low−pass filter is selected with
(100 , 47 nF) on each PWM output.
+
Measurement
Input
−
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7
NCP2820
TYPICAL CHARACTERISTICS
100
NCP2820 CSP
90
80
70
NCP2820 DFN
60
50
40
30
EFFICIENCY (%)
20
10
Class AB
Vp = 5 V R
0
0 0.2 0.4 0.6 0.8 1
P
(W)
out
Figure 3. Efficiency vs. P
out
Vp = 5 V, RL = 8, f = 1 kHz
100
NCP2820 CSP
90
80
NCP2820 DFN
70
60
50
EFFICIENCY (%)
40
30
20
10
Class AB
Vp = 3.6 V R
= 8
L
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
P
(W)
out
Figure 5. Efficiency vs. P
out
Vp = 3.6 V, RL = 8, f = 1 kHz
= 8
L
100
90
80
70
60
50
40
DIE TEMPERATURE (°C)
30
20
0 0.2 0.4
60
55
50
45
40
35
30
DIE TEMPERATURE (°C)
25
20
0 0.1 0.2
Vp = 3.6 V, RL = 8, f = 1 kHz @ T
Class AB
0.6 0.8 1.0 1.2 1.4
P
(W)
out
Figure 4. Die Temperature vs. P
Vp = 5 V, RL = 8, f = 1 kHz @ T
Class AB
0.3 0.4
P
(W)
out
0.5 0.6 0.7
Figure 8. Die Temperature vs. P
Vp = 5 V R
= 8
L
NCP2820
out
= +25°C
A
Vp = 3.6 V R
= 8
L
NCP2820
out
= +25°C
A
90
80
70
NCP2820 CSP
NCP2820 DFN
60
50
EFFICIENCY %
40
30
20
10
Class AB
Vp = 5 V R
L
0
0 0.5 1 1.5 2
P
(W)
out
Figure 6. Efficiency vs. P
out
Vp = 5 V, RL = 4, f = 1 kHz
= 4
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160
140
Class AB
120
100
80
Vp = 5 V R
= 4
L
60
DIE TEMPERATURE (°C)
40
20
0 0.5 1.0
P
Figure 7. Die Temperature vs. P
Vp = 5 V, RL = 4, f = 1 kHz @ T
out
(W)
NCP2820
1.5 2.0
A
out
= +25°C
8
NCP2820
TYPICAL CHARACTERISTICS
90
80
70
NCP2820 CSP
NCP2820 DFN
60
50
40
30
EFFICIENCY %
20
10
Class AB
Vp = 3.6 V R
L
0
0 0.2 0.4 0.6 0.8 1 1.2
P
(W)
out
Figure 9. Efficiency vs. P
out
Vp = 3.6 V, RL = 4, f = 1 kHz
10
Vp = 5.0 V R
= 8
L
1.0
f = 1 kHz
= 4
100
90
80
70
60
50
40
DIE TEMPERATURE (°C)
30
20
0 0.2 0.4
Figure 10. Die Temperature vs. P
Vp = 3.6 V, RL = 4, f = 1 kHz @ T
10
Vp = 4.2 V R
= 8
L
1.0
f = 1 kHz
Class AB
P
(W)
out
NCP2820
0.6 0.8
Vp = 3.6 V R
= 4
L
out
= +25°C
A
1.0
NCP2820 DFN
THD+N (%)
0.1
NCP2820 CSP
0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
P
(W)
out
Figure 11. THD+N vs. P
Vp = 5 V, RL = 8, f = 1 kHz
10
Vp = 3.6 V R
= 8
L
1.0
THD+N (%)
0.1
f = 1 kHz
NCP2820 DFN
NCP2820 CSP
out
NCP2820 DFN
THD+N (%)
0.1
NCP2820 CSP
0.01 0 0.2 0.4 0.6 0.8 1.0 1.2
P
(W)
out
Figure 12. THD+N vs. P
out
Vp = 4.2 V, RL = 8, f = 1 kHz
10
Vp = 3 V R
= 8
L
1.0
THD+N (%)
0.1
f = 1 kHz
NCP2820 DFN
NCP2820 CSP
0.01 0 0.2 0.4 0.6 0.8
P
(W)
out
Figure 13. THD+N vs. P
Vp = 3.6 V, RL = 8, f = 1 kHz
out
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0.01 0 0.1 0.2 0.3 0.4 0.5 0.6
P
(W)
out
Figure 14. THD+N vs. P
out
Vp = 3 V, RL = 8, f = 1 kHz
9
NCP2820
p
TYPICAL CHARACTERISTICS
10
Vp = 2.5 V R
= 8
L
f = 1 kHz
1.0
NCP2820 DFN
THD+N (%)
0.1
0.01 0 0.1 0.2 0.3 0.4
P
out
NCP2820 CSP
(W)
Figure 15. THD+N vs. Pout
V
= 2.5 V, RL = 8, f = 1 kHz
p
10
Vp = 4.2 V R
= 4
L
1.0
f = 1 kHz
10
Vp = 5 V R
= 4
L
f = 1 kHz
1.0
THD+N (%)
0.1
0.01 0 0.5 1.0
10
Vp = 3.6 V R
= 4
L
1.0
f = 1 kHz
1.5 2.0
P
(W)
out
Figure 16. THD+N vs. Pout
V
= 5 V, RL = 4, f = 1 kHz
p
2.5
THD+N (%)
0.1
0.01 0 0.5 1.0 1.5 2.0
P
(W)
out
Figure 17. THD+N vs. Pout
V
= 4.2 V, RL = 4, f = 1 kHz
p
10
Vp = 3 V R
= 4
L
f = 1 kHz
1.0
THD+N (%)
0.1 0
0.2 0.4 0.6 0.8
P
(W)
out
1.0
THD+N (%)
0.1
0.01
0.2 0.6 1.0
0 0.4 0.8 1.2 1.4
P
(W)
out
Figure 18. THD+N vs. Pout
V
= 3.6 V, RL = 4, f = 1 kHz
p
10
Vp = 2.5 V R
= 4
L
f = 1 kHz
1.0
THD+N (%)
0.1 0
0.1 0.2 0.3 0.4
P
(W)
out
0.5 0.6
Figure 19. THD+N vs. Power Out
V
= 3 V, RL = 4, f = 1 kHz
Figure 20. THD+N vs. Power Out
V
= 2.5 V, RL = 4, f = 1 kHz
p
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10
NCP2820
0
TYPICAL CHARACTERISTICS
2.0
RL = 8 f = 1 kHz
1.5
NCP2820 CSP
(W)
out
P
THD+N = 10%
1.0
0.5
0
2.5 3.0 3.5 4.0
NCP2820 DFN
THD+N = 10%
NCP2820 CSP
THD+N = 1%
POWER SUPPLY (V)
Figure 21. Output Power vs. Power Supply
R
= 8 @ f = 1 kHz
L
10
1.0
Vp = 2.5 V
THD+N (%)
0.1
Vp = 3.6 V
Vp = 5 V
NCP2820 DFN
THD+N = 3%
4.5 5.0
3.0
RL = 4 f = 1 kHz
THD+N = 10%
2.5 3.0 3.5 4.0
POWER SUPPLY (V)
(W)
out
P
2.5
2.0
1.5
1.0
0.5
0
Figure 22. Output Power vs. Power Supply
RL = 4@ f = 1 kHz
10
1.0
Vp = 2.5 V
THD+N (%)
0.1
Vp = 5 V
Vp = 3.6 V
THD+N = 1%
4.5
5.0
0.01 10
100 1000 10000 100000
FREQUENCY (Hz)
Figure 23. THD+N vs. Frequency
R
−20
−30
−40
−50
PSSR (dB)
−60
−70
−80
10
L
Vp = 3.6 V
= 8, P
Vp = 5 V
100 1000 10000 100000
= 250 mW @ f = 1 kHz
out
FREQUENCY (Hz)
Inputs to GND
Figure 25. PSRR vs. Frequency
Inputs Grounded, RL = 8, Vripple = 200 mvpkpk
R
= 8
L
0.01 10
100 1000 10000 100000
FREQUENCY (Hz)
Figure 24. THD+N vs. Frequency
R
−20
−30
−40
−50
PSSR (dB)
−60
−70
−80
10
= 4, P
L
Vp = 3.6 V
Vp = 5 V
100 1000 10000 10000
= 250 mW @ f = 1 kHz
out
FREQUENCY (Hz)
Inputs to GND
Figure 26. PSRR vs. Frequency
Inputs grounded, RL = 4, Vripple = 200 mVpkpk
R
= 4
L
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NCP2820
0
p
TYPICAL CHARACTERISTICS
−20
−30
−40
−50
CMMR (dB)
−60
−70
−80
10
100 1000 10000 100000
FREQUENCY (Hz)
Figure 27. PSRR vs. Frequency
V
= 3.6 V, RL = 8, Vic = 200 mvpkpk
p
900
800
700
600
500
400
300
200
SHUTDOWN CURRENT (nA)
100
0
2.5
RL = 8
3.5 4.5 5.5
POWER SUPPLY (V)
Vp = 3.6 V R
= 8
L
3.5
3.0
2.5
2.0
1.5
1.0
QUIESCENT CURRENT (mA)
0.5
0 120
130 140 150 160
TEMPERATURE (°C)
Thermal Shutdown
V
= 3.6 V
p
R
= 8
L
Figure 28. Thermal Shutdown vs. Temperature
Vp = 5 V, RL = 8 ,
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
SHUTDOWN CURRENT (nA)
1.2
1.0
2.5
RL = 8
3.5 4.5 5.5
POWER SUPPLY (V)
Figure 29. Shutdown Current vs. Power Supply
R
= 8
L
1000
Vp = 3.6 V R
= 8
L
NOISE (Vrms)
100
10
10
No Weighting
With A Weighting
100 1000 10000
FREQUENCY (Hz)
Figure 31. Noise Floor, Inputs AC Grounded
with 1F V
= 3.6 V
1000
100
NOISE (Vrms)
10
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Figure 30. Quiescent Current vs. Power Supply
R
= 8
L
Vp = 5 V R
= 8
L
No Weighting
With A Weighting
10
100 1000 1000
FREQUENCY (Hz)
Figure 32. Noise Floor, Inputs AC Grounded
with 1F Vp = 5 V
NCP2820
11
TA = +85°C
10
9
8
TURN ON TIME (mS)
7
6
2.5 3.5 4.5 5.5
TA = +25°C
TA = −40°C
POWER SUPPLY (V)
Figure 33. Turn on Time
DESCRIPTION INFORMATION
Detailed Description
The basic structure of the NCP2820 is composed of one analog pre−amplifier, a pulse width modulator and an H−bridge CMOS power stage. The first stage is externally configurable with gain−setting resistor R fixed feedback resistor R
(the closed−loop gain is fixed by
f
and the internal
i
the ratios of these resistors) and the other stage is fixed. The load is driven differentially through two output stages.
The differential PWM output signal is a digital image of the analog audio input signal. The human ear is a band pass filter regarding acoustic waveforms, the typical values of which are 20 Hz and 20 kHz. Thus, the user will hear only the amplified audio input signal within the frequency range. The switching frequency and its harmonics are fully filtered. The inductive parasitic element of the loudspeaker helps to guarantee a superior distortion value.
Power Amplifier
The output PMOS and NMOS transistors of the amplifier have been designed to deliver the output power of the specifications without clipping. The channel resistance (Ron) of the NMOS and PMOS transistors is typically 0.4.
Turn On and Turn Off Transitions in Case of 9 Pin Flip−Chip Package
In order to eliminate “pop and click” noises during transition, the output power in the load must not be established or cutoff suddenly. When a logic high is applied to the shutdown pin, the internal biasing voltage rises quickly and, 4 ms later, once the output DC level is around the common mode voltage, the gain is established slowly (5.0 ms). This method to turn on the device is optimized in terms of rejection of “pop and click” noises. Thus, the total turn on time to get full power to the load is 9 ms (typical).
8
7
TA = +25°C
6
TA = +85°C
5
TURN OFF TIME (mS)
4
2.5 3.5 4.5 5.5
Figure 34. Turn off Time
TA = −40°C
POWER SUPPLY (V)
The device has the same behavior when it is turned−off by a logic low on the shutdown pin. No power is delivered to the load 5 ms after a falling edge on the shutdown pin. Due to the fast turn on and off times, the shutdown signal can be used as a mute signal as well.
Turn On and Turn Off Transitions in Case of UDFN8
In case of UDFN8 package, the audio signal is established instantaneously after the rising edge on the shutdown pin. The audio is also suddenly cut once a low level is sent to the amplifier. This way to turn on and off the device in a very fast way also prevents from “pop & click” noise.
Shutdown Function
The device enters shutdown mode when the shutdown signal is low. During the shutdown mode, the DC quiescent current of the circuit does not exceed 1.5 A.
Current Breaker Circuit
The maximum output power of the circuit corresponds to an average current in the load of 820 mA.
In order to limit the excessive power dissipation in the load if a short−circuit occurs, a current breaker cell shuts down the output stage. The current in the four output MOS transistors are real−time controlled, and if one current exceeds the threshold set to 1.5 A, the MOS transistor is opened and the current is reduced to zero. As soon as the short−circuit is removed, the circuit is able to deliver the expected output power.
This patented structure protects the NCP2820. Since it completely turns off the load, it minimizes the risk of the chip overheating which could occur if a soft current limiting circuit was used.
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NCP2820
APPLICATION INFORMATION
NCP2820 PWM Modulation Scheme
The NCP2820 uses a PWM modulation scheme with each
output switching from 0 to the supply voltage. If V
= 0 V
in
outputs OUTM and OUTP are in phase and no current is flowing through the differential load. When a positive signal
OUTP
OUTM
+Vp
0 V
−Vp
Load Current
0 A
Figure 35. Output Voltage and Current Waveforms into an Inductive Loudspeaker
DC Output Positive Voltage Configuration
is applied, OUTP duty cycle is greater than 50% and OUTM is less than 50%. With this configuration, the current through the load is 0 A most of the switching period and thus power losses in the load are lowered.
Voltage Gain
The first stage is an analog amplifier. The second stage is a comparator: the output of the first stage is compared with a periodic ramp signal. The output comparator gives a pulse width modulation signal (PWM). The third and last stage is the direct conversion of the PWM signal with MOS transistors H−bridge into a powerful output signal with low impedance capability.
With an 8 load, the total gain of the device is typically set to:
300 k
R
i
Input Capacitor Selection (Cin)
The input coupling capacitor blocks the DC voltage at the amplifier input terminal. This capacitor creates a high−pass filter with R
Fc +
2 Ri C
, the cut−off frequency is given by
in
1
.
i
When using an input resistor set to 150 k, the gain configuration is 2 V/V. In such a case, the input capacitor selection can be from 10 nF to 1F with cutoff frequency values between 1 Hz and 100 Hz. The NCP2820 also includes a built in low pass filtering function. It’s cut off frequency is set to 20 kHz.
Optional Output Filter
This filter is optional due to the capability of the speaker to filter by itself the high frequency signal. Nevertheless, the high frequency is not audible and filtered by the human ear.
An optional filter can be used for filtering high frequency
signal before the speaker. In this case, the circuit consists of two inductors (15 H) and two capacitors (2.2 F) (Figure 36). The size of the inductors is linked to the output power requested by the application. A simplified version of this filter requires a 1 F capacitor in parallel with the load, instead of two 2.2 F connected to ground (Figure 37).
Cellular phones and portable electronic devices are great applications for Filterless Class−D as the track length between the amplifier and the speaker is short, thus, there is usually no need for an EMI filter. However, to lower radiated emissions as much as possible when used in filterless mode, a ferrite filter can often be used. Select a ferrite bead with the high impedance around 100 MHz and a very low DCR value in the audio frequency range is the best choice. The MPZ1608S221A1 from TDK is a good choice. The package size is 0603.
Optimum Equivalent Capacitance at Output Stage
If the optional filter described in the above section isn’t selected. Cellular phones and wireless portable devices design normally put several Radio Frequency filtering capacitors and ESD protection devices between Filter less Class D outputs and loudspeaker. Those devices are usually connected between amplifier output and ground. In order to achieve the best sound quality, the optimum value of total equivalent capacitance between each output terminal to the ground should be less than or equal to 150 pF. This total equivalent capacitance consists of the radio frequency filtering capacitors and ESD protection device equivalent parasitic capacitance.
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NCP2820
OUTM
15 H
OUTM
15 H
2.2 F
8
= L
R
OUTP
2.2 F
8
= L
R
1.0 F
OUTP
15 H
15 H
Figure 36. Advanced Optional Audio Output Filter Figure 37. Optional Audio Output Filter
OUTM
FERRITE
CHIP BEADS
8
= L
R
OUTP
Figure 38. Optional EMI Ferrite Bead Filter
Cs
Differential
Audio Input
from DAC
Input from
R
i
R
i
INP
INM
SD
VP
OUTM
OUTP
Microcontroller
GND
Figure 39. NCP2820 Application Schematic with Fully Differential Input Configuration
Cs
Differential
Audio Input
from DAC
Microcontroller
Input from
R
i
R
i
INP
INM
SD
VP
OUTM
FERRITE
CHIP BEADS
OUTP
GND
Figure 40. NCP2820 Application Schematic with Fully Differential Input Configuration and
Ferrite Chip Beads as an Output EMI Filter
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NCP2820
Cs
Differential
Audio Input
from DAC
C
i
C
i
Input from
R
i
R
i
INP
INM
SD
VP
OUTM
FERRITE
CHIP BEADS
OUTP
Microcontroller
GND
Figure 41. NCP2820 Application Schematic with Differential Input Configuration and
High Pass Filtering Function
Cs
Single−Ended Audio Input
from DAC
C
i
C
i
Input from
Microcontroller
R
i
R
i
INP
INM
SD
VP
OUTM
OUTP
GND
Figure 42. NCP2820 Application Schematic with Single Ended Input Configuration
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16
J7
U1
J1
NCP2820
V
p
V
C3*
C4*
4.7 F
B1, B2
p
J2
C1
100 nF
C2
100 nF
R1
150 k
R2
150 k
INP
A1
INM
C1
R
f
R
f
J8
*J6 not Mounted *C3 not Mounted in case of 9 Pin Flip−Chip Evaluation Board *C4 not Defined in case of UDFN8 Evaluation Board.
J6*
RAMP
GENERATOR
300 k
SD
Shutdown
Control
C2
J5
J5
Processor
V
p
CL = NCP2820 ON
C
= NCP2820 OFF
L
Data
CMOS Output
Stage
GND
OUTM
OUTP
A2, B3
A3
C3
J4
J3
= 8
L
R
Figure 43. Schematic of the Demonstration Board of the 9−pin Flip Chip CSP Device
Figure 44. Silkscreen Layer of the 9 Pin Flip−Chip Evaluation Board
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NCP2820
Figure 45. Silkscreen Layer of the UDFN8 Evaluation Board
PCB Layout Information
NCP2820 is suitable for low cost solution. In a very small package it gives all the advantages of a Class−D audio amplifier. The required application board is focused on low cost solution too. Due to its fully differential capability, the audio signal can only be provided by an input resistor. If a low pass filtering function is required, then an input coupling capacitor is needed. The values of these components determine the voltage gain and the bandwidth frequency. The battery positive supply voltage requires a good decoupling capacitor versus the expected distortion.
When the board is using Ground and Power planes with at least 4 layers, a single 4.7F filtering ceramic capacitor on the bottom face will give optimized performance.
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A 1.0 F low ESR ceramic capacitor can also be used with
slightly degraded performances on the THD+N from 0.06% up to 0.2%.
In a two layers application, if both V
pins are connected
p
on the top layer, a single 4.7 F decoupling capacitor will optimize the THD+N level.
The NCP2820 power audio amplifier can operate from
2.5 V until 5.5 V power supply. With less than 2% THD+N, it delivers 500 mW rms output power to a 8.0 load at Vp =3.0 V and 1.0 W rms output power at V
18
= 4.0 V.
p
NCP2820
Note
Figure 46. Top Layer of Two Layers Board Dedicated to the 9−Pin Flip−Chip Package
Note: This track between Vp pins is only needed when a 2 layers board is used. In case of a typical 4 or more layers, the use of laser vias in pad will optimize the THD+N floor. The demonstration board delivered by ON Semiconductor is a 4 Layers with Top, Ground, Power Supply and Bottom.
Bill of Materials
PCB
Item Part Description Ref
1 NCP2820 Audio Amplifier U1 NCP2820
2
3 Ceramic Capacitor 100 nF, 50 V, X7R C1, C2 0603 TDK C1608X7R1H104KT
4
5 PCB Footprint J7, J8
6 I/O connector. It can be plugged by
7 I/O connector. It can be plugged by
8 Jumper Connector, 400 mils J4 Harwin D3082−B01
9 Jumper Header Vertical Mount
SMD Resistor 150 k
Ceramic Capacitor 4.7 F, 6.3 V, X5R
MC−1,5/3−ST−3,81
BLZ5.08/2 (Weidmuller Reference)
3*1, 2.54 mm.
R1, R2 0603 Vishay−Draloric CRCW0603
C3, C4 0603 TDK C1608X5R0J475MT
J2 Phoenix Contact MC−1,5/3−G
J1, J3 Weidmuller SL5.08/2/90B
J5 Tyco Electronics / AMP 5−826629−0
Footprint
Manufacturer Part Number
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NCP2820
ORDERING INFORMATION
Device Marking Package Shipping†
NCP2820FCT1 MAQ 9−Pin Flip−Chip CSP 3000 / Tape & Reel
NCP2820FCT1G
NCP2820FCT2G
NCP2820MUTBG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
T1 Orientation T2 Orientation
Pin 1 (Upper Right) Pin 1 (Upper Left)
MAQG
MAQG
ZBMG
9−Pin Flip−Chip CSP
(Pb−Free)
9−Pin Flip−Chip CSP
(Pb−Free)
8 PIN UDFN 2x2.2
(Pb−Free)
3000 / Tape & Reel
T1 Orientation
3000 / Tape & Reel
T2 Orientation
3000 / Tape & Reel
Die orientation in tape with bumps downDie orientation in tape with bumps down
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20
0.10 C
0.10 C
0.05
4 X
C
D
TOP VIEW
NCP2820
PACKAGE DIMENSIONS
9 PIN FLIP−CHIP
CASE 499AL−01
ISSUE O
−A−
−B−
E
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS.
MILLIMETERS
DIM MIN MAX
A 0.540 0.660
A1 0.210 0.270
0.330 0.390
A2
D 1.450 BSC
1.450 BSC
E b 0.290 0.340
e 0.500 BSC D1 1.000 BSC E1 1.000 BSC
−C−
SEATING PLANE
9 X b
0.05 C
0.03 C
SIDE VIEW
D1
C
B
A
12 3
A B
BOTTOM VIEW
A2
A1
e
E1
e
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21
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
8X
0.08 C
L8X
0.10 C
D
TOP VIEW
SIDE VIEW
D2
1
NCP2820
PACKAGE DIMENSIONS
8 PIN UDFN, 2x2.2, 0.5P
CASE 506AV−01
ISSUE B
A B
E
A
(A3)
SEATING PLANE
A1
e
4
C
E2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN NOM MAX
A 0.45 0.50 0.55 A1 0.00 0.03 0.05 A3 0.127 REF
b 0.20 0.25 0.30
D 2.00 BSC D2 1.40 1.50 1.60
E 2.20 BSC E2 0.70 0.80 0.90
e 0.50 BSC
K 0.20 −−− −−−
L 0.35 0.40 0.45
SOLDERING FOOTPRINT*
2.15
1
8X
0.48
8X
0.25
K8X
BOTTOM VIEW
58
8X
b
1.60
0.10 B
NOTE 3
0.05ACC
0.80
DIMENSIONS: MILLIMETERS
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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For additional information, please contact your local Sales Representative
NCP2820/D
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