Datasheet NCP1308 Datasheet (ON Semiconductor)

s

查询NCP1052供应商

NCP1308

PWM Current−Mode
Controller for Free−Running
Quasi−Resonant Operation

The NCP1308 combines a true current mode modulator and a
demagnetization detector to ensure full borderline/Critical
Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi−Resonant operation). Due to its inherent
skip cycle capability, the controller enters burst mode as soon as the
power demand falls below a predetermined level. As this happens at
low peak current, no audible noise can be heard. An internal 10 ms
timer prevents the free−run frequency to exceed a high frequency
(therefore below the 150 kHz CISPR−22 EMI starting limit), while
the skip adjustment capability lets the user select the frequency at
which the burst foldback takes place.

The Dynamic Self−Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1308. This feature is particularly useful in
applications where the output voltage varies during operation (e.g.
battery chargers). Thanks to its high−voltage technology, the IC is
directly connected to the high−voltage DC rail. As a result, the
short−circuit trip point is not dependent upon any VCC auxiliary
level.

The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin. If an OVP is detected on
the VCC pin, the IC permanently latches off.

Finally, the continuous feedback signal monitoring implemented
with an Overcurrent fault Protection circuitry (OCP) makes the final
design rugged and reliable.

Features

• Free−Running Borderline/Critical Mode Quasi−Resonant Operation

• Current−Mode with Adjustable Skip Cycle Capability

• Dynamic Self−Supply Type of V

• Auto−Recovery Overcurrent Protection

• Improved UVLO for V

CC

• Latching Overvoltage Protection on V

• 500 mA Peak Current Source/Sink Capability

• Internal 1.0 ms Soft−Start

• Internal 10 ms Minimum T

• Adjustable Skip Level

• Internal Temperature Shutdown

• Internal Leading Edge Blanking

• Direct Optocoupler Connection

• SPICE Models Available for TRANsient Analysis

• This is a Pb−Free Device

T ypical Applications

• AC−DC Adapters for Notebooks, etc.

• Offline Battery Chargers

• Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)

• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)

CC

below 10 V

CC

OFF

http://onsemi.com

MARKING

8

1

SOIC−8

DR SUFFIX

CASE 751

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

PIN CONNECTIONS

Dmg

1

FB

2

CS

3

GND

4

(Top View)

ORDERING INFORMATION

Device Package Shipping

NCP1308DR2G SOIC−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

DIAGRAM

8

1308

ALYW

G

1

HV

8

7

V

6

CC

Drv

5

2500/Tape & Reel

†

© Semiconductor Components Industries, LLC, 2005

December, 2005 − Rev . 2

1 Publication Order Number:

NCP1308/D

NCP1308

Universal
Network

+

NCP1308

1 8
2
3
4

*Please refer to the application information section.

7
6

5

R*

12 V @ 1 A

+

GND

+

Y1 Type

Figure 1. Typical Application Schematic

PIN FUNCTION DESCRIPTION

Pin Symbol Function Description

1 Dmg Core reset detection The auxiliary FLYBACK signal ensures discontinuous operation.

2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is adjusted

3 CS Current sense input and skip

4 GND The IC ground −

5 Drv Driving pulses The driver’s output to an external MOSFET.

6 V

7

8 HV High−voltage pin Connected to the high−voltage rail, this pin injects a constant current into the V

CC

NC

cycle level selection

Supplies the IC This pin is connected to an external bulk capacitor of typically 10 mF. If an auxiliary

− This unconnected pin ensures adequate creepage distance.

accordingly to the output power demand. By bringing this pin below the internal
skip level, the device shuts off.

This pin senses the primary current and routes it to the internal comparator via an
LEB By inserting a resistor in series with the pin, you control the level at which the
skip operation takes place.

winding brings this pin above 16 V typical, the circuit permanently latches off.

bulk capacitor.

CC

http://onsemi.com

2

HV

V

CC

GND

7 mA

To Internal

Supply

PON

+

+

12 V
10 V

5.3 V (Fault)

Fault

Mngt.

50 us

Filter

16 V

OVP

NCP1308

+

−

+

VUVLO

Dmg

10 us

Blanking

+

+

S

Q

S

Q

R

R

+

+

50 mV

Resd

10 V

Driver src = 20 sink = 10

To internal supply

Soft−Start = 1 ms

+

−

/3

1 V

200 mA

when DRV

Overload?

5 us

Timeout

Time

Reset

Dmg

is OFF

380 ns

LEB

Dmg

Drv

20k

FB

CS

Figure 2. Internal Circuit Architecture

MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Voltage VCC, Drv 20 V
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (Drv) and

Pin 1 (Dmg)

Maximum Current into all pins except VCC (6), HV (8) and Dmg (1) when 10 V ESD diodes

are activated
Maximum Current in Pin 1 Idem +3.0/−2.0 mA
Thermal Resistance, Junction−to−Case R
Thermal Resistance, Junction−to−Air R
Maximum Junction Temperature TJ
Temperature Shutdown − 155 °C
Hysteresis in Shutdown − 30 °C
Storage Temperature Range − −60 to +150 °C
ESD Capability, Human Body Model (All pins except HV) − 2.0 kV
ESD Capability, Machine Model − 200 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 mF V
Minimum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 mF V

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.

− −0.3 to 10 V

− 5.0 mA

q

JC

q

JA

MAX

HVMAX

HVMIN

57 °C/W
178 °C/W
150 °C

500 V

40 V

http://onsemi.com

3

NCP1308

ELECTRICAL CHARACTERISTICS (For typical values T

= 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,

J

VCC = 11 V unless otherwise noted.)

Characteristic Pin Symbol Min Typ Max Unit

DYNAMIC SELF SUPPL Y

VCC Increasing Level at which the Current Source Turns−Off 6 VCC
VCC Decreasing Level at which the Current Source Turns−On 6 VCC
VCC Decreasing Level at which the Latchoff Phase Ends 6 VCC

OFF

ON

latch

VCC Level at which pulses are disabled 6 VUVLO − VCCON −

10.8 12 12.9 V

9.1 10 10.6 V

− 5.3 − V

− V

200 mV

Internal IC Consumption, No Output Load on Pin 5, F

= 60 kHz 6 ICC1 − 1.0 1.3

SW

(Note 1)

Internal IC Consumption, 1.0 nF Output Load on Pin 5, F

= 60 kHz 6 ICC2 − 1.6 2.0

SW

(Note 1)

Internal IC Consumption, Latchoff Phase, VCC = 6.0 V 6 ICC3 − 330 − mA

INTERNAL STARTUP CURRENT SOURCE ( TJ = 0°C)

High−Voltage Current Source, VCC = 10 V 8 IC1 4.3 7.0 9.6 mA
High−Voltage Current Source, VCC = 0 8 IC2 − 8.0 − mA

DRIVE OUTPUT

Output Voltage Rise−T ime @ CL = 1.0 nF, 10−90% of Output Signal 5 T
Output Voltage Fall−T ime @ CL = 1.0 nF, 10−90% of Output Signal 5 T
Source Resistance 5 R
Sink Resistance 5 R

r

f
OH
OL

− 40 − ns

− 20 − ns

12 20 36 W

5.0 10 20 W

CURRENT COMPARATOR

Input Bias Current @ 1.0 V Input Level on Pin 3 3 I
Maximum Internal Current Setpoint 3 I
Propagation Delay from Current Detection to Gate OFF State 3 T
Leading Edge Blanking Duration 3 T

IB

Limit

DEL
LEB

− 0.02 − mA

0.92 1.0 1.12 V

− 100 160 ns

− 380 − ns

Internal Current Offset Injected on the CS Pin During OFF Time 3 Iskip − 200 − mA

OVERVOLTAGE SECTION

Voltage on the VCC above which the controller latches off 6 VOVP 14.3 16 17.8 V
Integration Time Constraint on the OVP comparator 6 Tint − 50 − ms

FEEDBACK SECTION (VCC = 11 V, Pin 5 loaded by 1.0 kW)

Internal Pullup Resistor 2 Rup − 20 − kW
Pin 3 to Current Setpoint Division Ratio − Iratio − 3.3 − −
Internal Soft−Start − Tss − 1.0 − ms

DEMAGNETIZATION DETECTION BLOCK

Input Threshold Voltage (Vpin 1 Decreasing) 1 V
Hysteresis (Vpin 1 Decreasing) 1 V

th
H

35 50 90 mV

− 20 − mV

Input Clamp Voltage

High State (Ipin 1 = 3.0 mA)

Low State (Ipin 1 = −2.0 mA)
Dmg Propagation Delay 1 T
Internal Input Capacitance at Vpin 1 = 1.0 V 1 C
Minimum T

(Internal Blanking Delay After TON) 1 T

OFF

1
1

VC

VC

dem

blank

par

H
L

8.0

−0.9

10

−0.7

12

−0.5

− 210 − ns

− 10 − pF

− 10 − ms

Timeout After Last Dmg Transition 1 Tout − 5.0 − ms

1. Max value at TJ = 0°C, please see characterization curves.

mA

mA

V

http://onsemi.com

4

NCP1308

120

V

, (mV)

5

1.20

V

, (V)

5

TYPICAL CHARACTERISTICS

100

80

60

TH

40

20

0

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 3. Demagnetization Threshold

vs. Temperature

18

18

17

17

CC

16

1.15

1.10

, (V)

1.05

limit

I

1.00

0.95

0.90

−25 0 25 50 75 100 12
TEMPERATURE (°C)

Figure 4. Maximum Peak Current Setpoint

vs. Temperature

1.60

1.40

1.20

1.00

, (mA)

CC1

I

0.80

16

15

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 5. OVP Level Threshold vs. Temperature

2.00

1.95

1.90

1.85

1.80

1.75

, (mA)

CC2

1.70

I

1.65

1.60

1.55

1.50

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 7. Internal IC Consumption (1.0 nF Load)

0.60

0.40

−25 0 25 50 75 100 12
TEMPERATURE (°C)

Figure 6. Internal IC Consumption

(No Output Load) vs. Temperature

vs. Temperature

http://onsemi.com

5

NCP1308

TYPICAL CHARACTERISTICS

12.90

12.40

11.90

, (V)

OFF

11.40

VCC

10.90

10.40

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 8. VCC Increasing Level at which the

Current Source Turns−off vs. Temperature

12

11

10

9
8
7

, (mA)

C1

I

6
5
4
3
2

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 10. Internal Startup Current Source,

= 10 V vs. Temperature

V

CC

11.0

10.8

10.6

10.4

10.2

, (V)

10.0

ON

9.8

VCC

9.6

9.4

9.2

9.0

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 9. VCC Decreasing Level at which the

Current Source Turns−on vs. Temperature

40
35
30

(W)

25

OL

20

and R

15

OH

R

10

5
0

−25 0 25 50 75 100 125

TEMPERATURE (°C)

R

OH

R

OL

Figure 11. Source and Sink Resistance vs.

Temperature

http://onsemi.com

6

NCP1308

V

CURRENT SOURCE

CC

APPLICATION INFORMATION

INTRODUCTION

The NCP1308 implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint, whereas the core reset detection
triggers the turn−on event. This component represents the
ideal candidate where low part−count is the key parameter,
particularly in low−cost AC/DC adapters, consumer
electronics, auxiliary supplies, etc. Due to its
high−performance High−Voltage technology, the
NCP1308 incorporates all the necessary
components/features needed to build a rugged and reliable
Switch−Mode Power Supply (SMPS):

• Transformer Core Reset Detection: Borderline/critical

operation is ensured whatever the operating conditions
are. As a result, there are virtually no primary switch
turn−on losses and no secondary diode recovery
losses. The converter also stays a first−order system
and accordingly eases the feedback loop design.

• Quasi−Resonant Operation: By delaying the turn−on

event, it is possible to restart the MOSFET in the
minimum of the drain−source wave, ensuring reduced
EMI/video noise perturbations. In nominal power
conditions, the NCP1308 operates in Borderline
Conduction Mode (BCM) also called Critical
Conduction Mode (CCM).

• Dynamic Self−Supply (DSS): Due to its Very High

Voltage Integrated Circuit (VHVIC) technology, ON
Semiconductor’s NCP1308 allows for a direct pin
connection to the high−voltage DC rail. A dynamic
current source charges up a capacitor and thus

a noise−free operation with cheap transformer. This
option also offers the ability to fix the maximum
switching frequency when ent ering light load conditions.

• Overcurrent Protection (OCP): By continuously

monitoring the FB line activity, NCP1308 enters burst
mode as soon as the power supply undergoes an
overload. The device enters a safe low power
operation that prevents from any lethal thermal
runaway. As soon as the default disappears, the power
supply resumes operation. Unlike other controllers,
overload detection is performed independently of any
auxiliary winding level. In presence of a bad coupling
between both power and auxiliary windings, the short
circuit detection can be severely affected. The DSS
naturally shields you against these troubles.

Dynamic Self−Supply

The DSS principle is based on the charge/discharge of the
VCC bulk capacitor from a low level up to a higher level.
We can easily describe the current source operation with
some simple logical equations:

POWER−ON: IF VCC < VCC

is ON, no output pulses
IF VCC decreasing > VCCON THEN

Current Source is OFF, output is pulsing
IF VCC increasing < VCC

Current Source is ON, output is pulsing

Typical values are: VCC

OFF

To better understand the operational principle, the
diagram in Figure 12 offers the necessary light:

THEN Current Source

OFF

THEN

OFF

= 12 V, VCCON = 10 V

provides a fully independent VCC level to the
NCP1308. As a result, there is no need for an auxiliary
winding to supply the IC, whose management is
always a problem in variable output voltage designs
(e.g. battery chargers).

• Overvoltage Protection (OVP): By monitoring the

Vripple = 2V

CC

VCC

OFF

= 12V

VCCON = 10V

VCC pin via a 50 ms time constant filter, the NCP1308
goes into latched fault condition whenever an
overvoltage condition is detected. This occurs if V

CC

ON

goes above 16 V typically. The controller stays fully
latched in this position until the VCC is cycled down to

OFF

4 V, e.g. when the user unplugs the power supply from
the mains outlet and re−plugs it.

• Adjustable Skip Cycle Level: By offering the ability

to tailor the level at which the skip cycle takes place,
the designer can make sure that the skip operation
only occurs at low peak current. This point guarantees

Figure 12. The Charge/Discharge Cycle over a 10 mF

V

Output pulses

Capacitor

http://onsemi.com

7

NCP1308

CURRENT SENSE SIGNAL (mV)

The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg equals 22 nC
(max). With a maximum switching frequency selected at
75 kHz, the average power necessary to drive the MOSFET
(excluding the driver efficiency and neglecting various
voltage drops) is: F

SW

@ Qg@ V

CC

with:
FSW = maximum switching frequency
Qg = MOSFET’s gate charge
VCC = VGS level applied to the gate

To obtain the output current, simply divide this result by

VCC: I

+ FSW@ Qg + 1.6 mA. The total standby

driver

power consumption at no−load will therefore heavily rely
on the internal IC consumption plus the above driving
current (altered by the driver ’s efficiency). Suppose that
the IC is supplied from a 350 VDC line. The current
flowing through Pin 8 is a direct image of the NCP1308
consumption (neglecting the switching losses of the HV
current source). If I

equals 2.3 mA @ TJ = 60°C, then

CC2

the power dissipated (lost) by the IC is simply:
350 V x 2.3 mA = 805 mW. For design and reliability
reasons, it would be interesting to reduce this source of
wasted power that increases the die temperature. This can
be achieved by using different methods:

1. Use a MOSFET with lower gate charge Qg

2. Connect a diode to the half−wave portion to
directly supply the HV pin:

HV

Cbulk

12

MAINS

1N4007

5

1 8
2
3
4

7
6
5

Skipping Cycle Mode

The NCP1308 automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, Pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 14)
and follows the following formula:

1

@ Lp@ Ip2@ FSW@ D

2

burst

with:

Lp = primary inductance
FSW = switching frequency within the burst
Ip = peak current at which skip cycle occurs
D

= burst width/burst recurrence

burst

300

200

100

0

6

Figure 14. The Skip Cycle Takes Place at Low Peak

Currents which Guarantees Noise−Free Operation

MAX PEAK
CURRENT

WIDTH

RECURRENCE

DRIVER

NORMAL CURRENT

MODE OPERATION

SKIP CYCLE

CURRENT LIMIT

Figure 13. The Connection to the Half−Wave Signal

Reduces the Dissipated Power on the Controller

3. Permanently force the VCC level above VCC
with an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully self−supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. Make sure the auxiliary
voltage never exceeds the 16 V limit. When the
power supply is switched off, an internal
comparator makes sure that all output pulses are
disable when VCC crosses VCCON.

RESET

ON

Level Selection via a Series Resistor Inserted in

http://onsemi.com

8

DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 mA

R

3

−
+

2

+

Figure 15. A Patented Method Allows for Skip

Series with the Current

skip

R

sense

NCP1308

The skip level selection is done through a simple resistor
inserted between the current sense input and the sense
element. Every time the NCP1308 output driver goes low,
a 200 mA source forces a current to flow through the sense
pin (Figure 15): when the driver is high, the current source
is off and the current sense information is normally
processed. As soon as the driver goes low, the current
source delivers 200 mA and develops a ground−referenced
voltage across R

. If this voltage is below the feedback

skip

voltage, the current sense comparator stays in the high state
and the internal latch can be triggered by the next clock
cycle. Now, if because of a low load mode the feedback
voltage is below R

level, then the current sense

skip

comparator permanently resets the latch and the next clock
cycle (given by the demagnetization detection) is ignored:
we are skipping cycles as shown in Figure 15. As soon as
the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1308. T o the opposite, in low output power conditions,
no more ringing waves are present on the drain and the
toggling of the current sense comparator together with the

internal 5 ms timeout initiates a new cycle start. In normal
operating conditions, e.g. when the drain oscillations are
generous, the demagnetization comparator can detect the
50 mV crossing and gives the “green light”, alone, to
re−active the power switch. However, when skip cycle
takes place (e.g. at low output power demands), the restart
event slides along the drain ringing waveforms (actually
the valley locations) which decays more or less quickly,
depending on the L

primary−Cparasitic

network damping
factor. The situation can thus quickly occur where the
ringing becomes too weak to be detected by the
demagnetization comparator: it then permanently stays
locked in a given position and can no longer deliver the
“green light” to the controller. To help in this situation, the
NCP1308 implements a 5 ms timeout generator: each time
the 50 mV crossing occurs, the timeout is reset. So, as long
as the ringing becomes too low, the timeout generator starts
to count and after 5 ms, it delivers its “green light”. If the
skip signal is already present then the controller restarts;
otherwise the logic waits for it to set the drive output high.
Figure 16 depicts these two different situations:

Drain

Signal

Timeout

Signal

Dmg Restart

Current Sense and Timeout Restart

Drain

Signal

Timeout

Signal

Figure 16. When the primary natural ringing becomes too low, the internal Timeout

together with the sense comparator initiates a new cycle when FB passes the skip level.

5 ms5 ms

http://onsemi.com

9

NCP1308

TO INTERNAL

C

x

DRAIN VOLTAGE (V)

Demagnetization Detection

The core reset detection is done by monitoring the
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 17.

7.0

5.0

3.0

1.0

DMG SIGNAL (V)

−1.0

POSSIBLE

RESTARTS

50 mV

0 V

Figure 17. Core Reset Detection is Done through

a Dedicated Auxiliary Winding Monitoring

An internal timer prevents any restart within 10 μs
further to the driver going−low transition. This prevents the
switching frequency to exceed (1/(TON + 10 ms)) but also
avoid false leakage inductance tripping at turn−off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.

The NCP1308 demagnetization detection pad features a
specific component arrangement as detailed by Figure 18.
In this picture, the Zener diodes network protect the IC
against any potential ESD discharge that could appear on
the pins. The first ESD diode connected to the pad, exhibits
a parasitic capacitance. When this parasitic capacitance
(10 pF typically) is combined with R

, a restart delay is

dem

created and the possibility to switch right in the
drain−source wave exists. This guarantees QR operation
with all the associated benefits (low EMI, no turn−on losses
etc.). R

should be calculated to limit the maximum

dem

current flowing through Pin 1 to less than +3 mA / −2 mA:
if during turn−on, the auxiliary winding delivers −30 V (at
the highest line level), then the minimum R

dem

value is
defined by: (−30 + 0.7. This value will be further increased
to introduce a restart delay and also a slight filtering in case
of high leakage energy.

OMPARATOR

R

esd

R

1

dem

Figure 19 portrays a typical Vds shot at nominal output

power.

400

300

200

100

0

Figure 19. The NCP1308 Operates in

Borderline/Critical Operation

Overvoltage Protection

The overvoltage works by monitoring the VCC pin via a
comparator and a reference voltage. Figure 20 portrays the
internal arrangement:

50 us

FILTER

V

CC

+

16 V

−

+

OVP
COMPARATOR

TO LATCH

Figure 20. OVP Section Circuitry

A 50 ms time−constant filter prevents any parasitic spikes
superimposed on the VCC to adversely trigger the OVP
comparator. When the OVP comparator output goes high,
the NCP1308 fully latches off and stays latched, being
self−supplied by the DSS. The user must unplug the power
supply and wait that the VCC comes down below a reset
voltage of typically 4 V.

ESD ESD

4

Figure 18. Internal Pad Implementation

Au

http://onsemi.com

10

NCP1308

Shutting off the NCP1308

Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 21. When
OFF, Q1 is transparent to the operation. When forward
biased, the transistor pulls the FB pin to ground (V

CEsat

≈
200 mV) and permanently disables the IC. A small time
constant on the transistor base will avoid false triggering

NCP1308

1 8

10 k

ON/OFF

10 nF

Figure 21. A Simple Bipolar Transistor Totally

Disables the IC

Power Dissipation

Q1

2
3
4

7
6

5

The SOIC package offers a 178°C/W thermal resistor.
Again, adding some copper area around the PCB footprint
will help decreasing this number: 12 mm x 12 mm to drop
R

down to 1 0 0 °C/W with 35 mm copper thickness (1 oz)

JA

θ

or 6.5 mm x 6.5 mm with 70 mm copper thickness (2 oz).
As one can see, the designer must be cautious when using
the SO−8 package to check if its thermal performance is
compatible with the total power dissipation. The power
dissipation is simply Vbulk (high line) x I
I

DSS,A VG

parameter can be measured by inserting an

DSS,A VG

. The

amp−meter in series with the HV pin and compute its
average value.

We therefore recommend the insertion of a resistor from
the bulk connection to the HV pin. This will help to:

1. Avoid negative spikes at turn−off on the HV pin
(see below)

2. Split the power budget between this resistor and
the package. The resistor is calculated by leaving
at least 50 V on pin 8 at minimum input voltage
(suppose 100 Vdc in our case):

R

drop

v

V

bulkmin

* 50 V

7.0 mA

t 7.1 kW .

The power dissipated by the resistor is thus:

P

drop

V

dropRMS

+

R

(I

DSS

+

(7.0 mA @ 7.1 kW @ 0.286)

+

drop

@ R

2

drop

7.1 kW

Ǹ

@ DSS

R

drop

Ǹ

duty−cycle

2

2

)

where I

is the peak DSS capability, DSS

DSS

duty−cycle

is the
duty−cycle of the DSS, that is to say, the time it is on and
the time it stays off (DSS

duty−cycle

= on/(on + off) ).

Please refer to the application note AND8069/D

available at www.onsemi.com/pub/ncp1200.

If the power consumption budget is really too high for the
DSS alone, connect a diode between the auxiliary winding
and the VCC pin which will disable the DSS operation
(V

> 10 V).

CC

Overload Operation

In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it
is interesting to implement a true short−circuit protection.
A short−circuit actually forces the output voltage to be at
a low level, preventing a bias current to circulate in the
optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please
note that this can also happen in case of feedback loss, e.g.
a broken optocoupler. To account for this situation,
NCP1308 hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in
a burst manner with a low duty−cycle. The system recovers
when the fault condition disappears.

During the startup phase, the peak current is pushed to
the maximum until the output voltage reaches its target and
the feedback loop takes over. This period of time depends
on normal output load conditions and the maximum peak
current allowed by the system. The timeout used by this IC
works with the VCC decoupling capacitor: as soon as the
VCC decreases from the VCC

level (typically 12 V) the

OFF

device internally watches for an overload current situation.
If this condition is still present when the VCCON level is
reached, the controller stops the driving pulses, prevents
the self−supply current source to restart and puts all the
circuitry in standby, consuming as little as 330 mA typical
(ICC3 parameter). As a result, the VCC level slowly
discharges toward 0. When this level crosses 5.3 V typical,
the controller enters a new startup phase by turning the
current source on: VCC rises toward 12 V and again delivers
output pulses at the VCC

crossing point. If the fault

OFF

condition has been removed before VCCON approaches,
then the IC continues its normal operation. Otherwise, a
new fault cycle takes place. Figure 22 on the following
page shows the evolution of the signals in presence of a
fault.

+ 99.5 mW

http://onsemi.com

11

12 V

10 V

5.3 V

NCP1308

V

CC

REGULATION

OCCURS HERE

LATCHOFF

PHASE

DRV

DRIVER
PULSES

INTERNAL

FAULT FLAG

FAULT IS
RELAXED

FAULT OCCURS HERESTARTUP PHASE

Figure 22.

Soft−Start

The NCP1308 features an internal 1ms soft−start to
soften the constraints occurring in the power supply during
startup. It is activated during the power on sequence. As
soon as VCC reaches VCC

, the peak current is gradually

OFF

increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). The soft−start is also activated during the
over current burst (OCP) sequence. Every restart attempt
is followed by a soft−start activation. Generally speaking,
the soft−start will be activated when VCC ramps up either
from zero (fresh power−on sequence) or 5.3 V, the latchoff
voltage occurring during OCP.

Calculating the VCC Capacitor

As the above section describes, the fall down sequence
depends upon the VCC level: how long does it take for the
VCC line to go from 12 V to 10 V? The required time
depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging

TIME

TIME

TIME

If the fault is relaxed during the V
natural fall down sequence, the IC
automatically resumes.
If the fault still persists when V
reached VCCON, then the controller
cuts everything off until recovery .

CC

CC

must be less than the time needed to discharge from 12 V
to 10 V, otherwise the supply will not properly start. The
test consists in either simulating or measuring in the lab
how much time the system takes to reach the regulation at
full load. Let’s suppose that this time corresponds to 6ms.
Therefore a VCC fall time of 10 ms could be well
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
the MOSFET drive, establishes at 1.6 mA (e.g. with a
10 nC Qg), we can calculate the required capacitor using

the following formula: Dt +

DV@ C

, with ΔV = 2 V. Then

i

for a wanted Δt of 10 ms, C equals 9 mF or 22 mF for a
standard value. When an overload condition occurs, the IC
blocks its internal circuitry and its consumption drops to
330 mA typical. This happens at VCC = 10 V and it remains
stuck until VCC reaches 5.3 V: we are in latchoff phase.
Again, using the calculated 22 mF and 330 mA current
consumption, this latchoff phase lasts: 313 ms.

http://onsemi.com

12

NCP1308

Protecting Pin 8 Against Negative Spikes

As any CMOS controller, NCP1308 is sensitive to
negative voltages that could appear on its pins (Figure 23).
To avoid any adverse latchup of the IC, we strongly
recommend to insert a resistor in series with pin 8. This

Vbulk

Vcc

Figure 23. A negative spike can occur at mains switch−off if the

quality coefficient of Cbulk−Lp is high enough.

resistor prevents from adversely latching the controller in
case of negative spikes appearing on the bulk capacitor
during the power−off sequence. Please refer to the power
dissipation section of this data sheet to see how to calculate
this element.

Latch!

Vbulk
< 0

Another option consists in adding a diode (or two in
series for safety) from the VCC to the bulk capacitor.
Figure 12 details this other option:

1 8

+

Cbulk

Figure 24. A diode will force the VCCto decrease at
the same pace the bulk capacitor does, avoiding a

2
3
4

negative ringing on the HV pin.

7
6
5

1N4007

+

CVCC

1N4007

or

1N4007

http://onsemi.com

13

NCP1308

Operation Shots

Below are some oscilloscope shots captured at Vin = 120 VDC with a transformer featuring a 800 mH primary inductance:

Figure 25. This plot gathers waveforms captured at three different operating points:

1st Upper Plot: Free run, valley switching operation, Pout = 26 W.

nd

Middle Plot: Min Toff clamps the switching frequency and selects

2
the second valley.

rd

Lowest Plot: The skip slices the second valley pattern and will

3
further expand the burst as Pout goes low.

Vgate (5 V/div)

200 mA x Rskip

Current Sense Pin (200 mV/pin)

Vrsense (200 mV/div)

Figure 26. This picture explains how the 200 mA internal offset

current creates the skip cycle level.

http://onsemi.com

14

NCP1308

VCC (5 V/div)

Vgate (5 V/div)

Figure 27. The short−circuit protection forces the IC to enter burst

in presence of a secondary overload.

http://onsemi.com

15

−Y−

−Z−

NCP1308

PACKAGE DIMENSIONS

SOIC−8

DR SUFFIX

CASE 751−07

ISSUE AG

−X−

B

H

A

58

1

4

G

D

0.25 (0.010) Z

M

S

Y

0.25 (0.010)

C

SEATING
PLANE

SXS

M

0.10 (0.004)

M

Y

K

N

X 45

_

M

J

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050

M 0 8 0 8

____

N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

INCHES

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

0.6

0.024

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting T echniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

4.0

0.155

1.270

0.050

SCALE 6:1

mm

ǒ

inches

Ǔ

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [e-mail]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

http://onsemi.com

16

ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your
local Sales Representative.

NCP1308/D