ON Semiconductor NCP1308 Technical data

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NCP1308

PWM Current−Mode
Controller for Free−Running
Quasi−Resonant Operation

The NCP1308 combines a true current mode modulator and a
demagnetization detector to ensure full borderline/Critical
Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi−Resonant operation). Due to its inherent
skip cycle capability, the controller enters burst mode as soon as the
power demand falls below a predetermined level. As this happens at
low peak current, no audible noise can be heard. An internal 10 ms
timer prevents the free−run frequency to exceed a high frequency
(therefore below the 150 kHz CISPR−22 EMI starting limit), while
the skip adjustment capability lets the user select the frequency at
which the burst foldback takes place.

The Dynamic Self−Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1308. This feature is particularly useful in
applications where the output voltage varies during operation (e.g.
battery chargers). Thanks to its high−voltage technology, the IC is
directly connected to the high−voltage DC rail. As a result, the
short−circuit trip point is not dependent upon any VCC auxiliary
level.

The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin. If an OVP is detected on
the VCC pin, the IC permanently latches off.

Finally, the continuous feedback signal monitoring implemented
with an Overcurrent fault Protection circuitry (OCP) makes the final
design rugged and reliable.

Features

• Free−Running Borderline/Critical Mode Quasi−Resonant Operation

• Current−Mode with Adjustable Skip Cycle Capability

• Dynamic Self−Supply Type of V

• Auto−Recovery Overcurrent Protection

• Improved UVLO for V

CC

• Latching Overvoltage Protection on V

• 500 mA Peak Current Source/Sink Capability

• Internal 1.0 ms Soft−Start

• Internal 10 ms Minimum T

• Adjustable Skip Level

• Internal Temperature Shutdown

• Internal Leading Edge Blanking

• Direct Optocoupler Connection

• SPICE Models Available for TRANsient Analysis

• This is a Pb−Free Device

T ypical Applications

• AC−DC Adapters for Notebooks, etc.

• Offline Battery Chargers

• Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)

• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)

CC

below 10 V

CC

OFF

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MARKING

8

1

SOIC−8

DR SUFFIX

CASE 751

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

PIN CONNECTIONS

Dmg

1

FB

2

CS

3

GND

4

(Top View)

ORDERING INFORMATION

Device Package Shipping

NCP1308DR2G SOIC−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

DIAGRAM

8

1308

ALYW

G

1

HV

8

7

V

6

CC

Drv

5

2500/Tape & Reel

†

© Semiconductor Components Industries, LLC, 2005

December, 2005 − Rev . 2

1 Publication Order Number:

NCP1308/D

NCP1308

Universal
Network

+

NCP1308

1 8
2
3
4

*Please refer to the application information section.

7
6

5

R*

12 V @ 1 A

+

GND

+

Y1 Type

Figure 1. Typical Application Schematic

PIN FUNCTION DESCRIPTION

Pin Symbol Function Description

1 Dmg Core reset detection The auxiliary FLYBACK signal ensures discontinuous operation.

2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is adjusted

3 CS Current sense input and skip

4 GND The IC ground −

5 Drv Driving pulses The driver’s output to an external MOSFET.

6 V

7

8 HV High−voltage pin Connected to the high−voltage rail, this pin injects a constant current into the V

CC

NC

cycle level selection

Supplies the IC This pin is connected to an external bulk capacitor of typically 10 mF. If an auxiliary

− This unconnected pin ensures adequate creepage distance.

accordingly to the output power demand. By bringing this pin below the internal
skip level, the device shuts off.

This pin senses the primary current and routes it to the internal comparator via an
LEB By inserting a resistor in series with the pin, you control the level at which the
skip operation takes place.

winding brings this pin above 16 V typical, the circuit permanently latches off.

bulk capacitor.

CC

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2

HV

V

CC

GND

7 mA

To Internal

Supply

PON

+

+

12 V
10 V

5.3 V (Fault)

Fault

Mngt.

50 us

Filter

16 V

OVP

NCP1308

+

−

+

VUVLO

Dmg

10 us

Blanking

+

+

S

Q

S

Q

R

R

+

+

50 mV

Resd

10 V

Driver src = 20 sink = 10

To internal supply

Soft−Start = 1 ms

+

−

/3

1 V

200 mA

when DRV

Overload?

5 us

Timeout

Time

Reset

Dmg

is OFF

380 ns

LEB

Dmg

Drv

20k

FB

CS

Figure 2. Internal Circuit Architecture

MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Voltage VCC, Drv 20 V
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (Drv) and

Pin 1 (Dmg)

Maximum Current into all pins except VCC (6), HV (8) and Dmg (1) when 10 V ESD diodes

are activated
Maximum Current in Pin 1 Idem +3.0/−2.0 mA
Thermal Resistance, Junction−to−Case R
Thermal Resistance, Junction−to−Air R
Maximum Junction Temperature TJ
Temperature Shutdown − 155 °C
Hysteresis in Shutdown − 30 °C
Storage Temperature Range − −60 to +150 °C
ESD Capability, Human Body Model (All pins except HV) − 2.0 kV
ESD Capability, Machine Model − 200 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 mF V
Minimum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 mF V

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.

− −0.3 to 10 V

− 5.0 mA

q

JC

q

JA

MAX

HVMAX

HVMIN

57 °C/W
178 °C/W
150 °C

500 V

40 V

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NCP1308

ELECTRICAL CHARACTERISTICS (For typical values T

= 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,

J

VCC = 11 V unless otherwise noted.)

Characteristic Pin Symbol Min Typ Max Unit

DYNAMIC SELF SUPPL Y

VCC Increasing Level at which the Current Source Turns−Off 6 VCC
VCC Decreasing Level at which the Current Source Turns−On 6 VCC
VCC Decreasing Level at which the Latchoff Phase Ends 6 VCC

OFF

ON

latch

VCC Level at which pulses are disabled 6 VUVLO − VCCON −

10.8 12 12.9 V

9.1 10 10.6 V

− 5.3 − V

− V

200 mV

Internal IC Consumption, No Output Load on Pin 5, F

= 60 kHz 6 ICC1 − 1.0 1.3

SW

(Note 1)

Internal IC Consumption, 1.0 nF Output Load on Pin 5, F

= 60 kHz 6 ICC2 − 1.6 2.0

SW

(Note 1)

Internal IC Consumption, Latchoff Phase, VCC = 6.0 V 6 ICC3 − 330 − mA

INTERNAL STARTUP CURRENT SOURCE ( TJ = 0°C)

High−Voltage Current Source, VCC = 10 V 8 IC1 4.3 7.0 9.6 mA
High−Voltage Current Source, VCC = 0 8 IC2 − 8.0 − mA

DRIVE OUTPUT

Output Voltage Rise−T ime @ CL = 1.0 nF, 10−90% of Output Signal 5 T
Output Voltage Fall−T ime @ CL = 1.0 nF, 10−90% of Output Signal 5 T
Source Resistance 5 R
Sink Resistance 5 R

r

f
OH
OL

− 40 − ns

− 20 − ns

12 20 36 W

5.0 10 20 W

CURRENT COMPARATOR

Input Bias Current @ 1.0 V Input Level on Pin 3 3 I
Maximum Internal Current Setpoint 3 I
Propagation Delay from Current Detection to Gate OFF State 3 T
Leading Edge Blanking Duration 3 T

IB

Limit

DEL
LEB

− 0.02 − mA

0.92 1.0 1.12 V

− 100 160 ns

− 380 − ns

Internal Current Offset Injected on the CS Pin During OFF Time 3 Iskip − 200 − mA

OVERVOLTAGE SECTION

Voltage on the VCC above which the controller latches off 6 VOVP 14.3 16 17.8 V
Integration Time Constraint on the OVP comparator 6 Tint − 50 − ms

FEEDBACK SECTION (VCC = 11 V, Pin 5 loaded by 1.0 kW)

Internal Pullup Resistor 2 Rup − 20 − kW
Pin 3 to Current Setpoint Division Ratio − Iratio − 3.3 − −
Internal Soft−Start − Tss − 1.0 − ms

DEMAGNETIZATION DETECTION BLOCK

Input Threshold Voltage (Vpin 1 Decreasing) 1 V
Hysteresis (Vpin 1 Decreasing) 1 V

th
H

35 50 90 mV

− 20 − mV

Input Clamp Voltage

High State (Ipin 1 = 3.0 mA)

Low State (Ipin 1 = −2.0 mA)
Dmg Propagation Delay 1 T
Internal Input Capacitance at Vpin 1 = 1.0 V 1 C
Minimum T

(Internal Blanking Delay After TON) 1 T

OFF

1
1

VC

VC

dem

blank

par

H
L

8.0

−0.9

10

−0.7

12

−0.5

− 210 − ns

− 10 − pF

− 10 − ms

Timeout After Last Dmg Transition 1 Tout − 5.0 − ms

1. Max value at TJ = 0°C, please see characterization curves.

mA

mA

V

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NCP1308

120

V

, (mV)

5

1.20

V

, (V)

5

TYPICAL CHARACTERISTICS

100

80

60

TH

40

20

0

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 3. Demagnetization Threshold

vs. Temperature

18

18

17

17

CC

16

1.15

1.10

, (V)

1.05

limit

I

1.00

0.95

0.90

−25 0 25 50 75 100 12
TEMPERATURE (°C)

Figure 4. Maximum Peak Current Setpoint

vs. Temperature

1.60

1.40

1.20

1.00

, (mA)

CC1

I

0.80

16

15

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 5. OVP Level Threshold vs. Temperature

2.00

1.95

1.90

1.85

1.80

1.75

, (mA)

CC2

1.70

I

1.65

1.60

1.55

1.50

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 7. Internal IC Consumption (1.0 nF Load)

0.60

0.40

−25 0 25 50 75 100 12
TEMPERATURE (°C)

Figure 6. Internal IC Consumption

(No Output Load) vs. Temperature

vs. Temperature

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