ON Semiconductor NCD5703A, NCD5703B, NCD5703C User Manual

NCD5703A, NCD5703B, NCD5703C

High Current IGBT Gate Drivers

The NCD5703A, NCD5703B and NCD5703C are high−current, high−performance stand−alone IGBT drivers for high power applications that include solar inverters, motor control and uninterruptible power supplies. The devices offer a cost−effective solution by eliminating external output buffer. Devices protection features include accurate Under−voltage−lockout (UVLO), desaturation protection (DESAT) and Active open−drain FAULT output. The drivers also feature an accurate 5.0 V output. The drivers are designed to accommodate a wide voltage range of bias supplies including unipolar and NCD5703B even bipolar voltages.

Depending on the pin configuration the devices also include Active Miller Clamp (NCD5703A) and separate high and low (V driver outputs for system design convenience (NCD5703C).

All three available pin configuration variants have 8−pin SOIC package.

Features

• High Current Output (+4/−6 A) at IGBT Miller Plateau voltages

• Low Output Impedance for Enhanced IGBT Driving

• Short Propagation Delay with Accurate Matching

• Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer

for Isolated Drive, Logic Compatibility for Non−isolated Drive

• DESAT Protection with Programmable Delay

• Tight UVLO Thresholds for Bias Flexibility

• Wide Bias Voltage Range

• This Device is Pb−Free, Halogen−Free and RoHS Compliant

NCD5703A Features

• Active Miller Clamp to Prevent Spurious Gate Turn−on

NCD5703B Features

• Negative Output Voltage for Enhanced IGBT Driving

NCD5703C Features

• Separate Outputs for V

and V

Typical Applications

• Solar Inverters

• Motor Control

• Uninterruptible Power Supplies (UPS)

• Rapid Shutdown for Photovoltaic Systems

and VOL)

www.onsemi.com

MARKING

SOIC−8 D SUFFIX CASE 751

NCD5703 = Specific Device Code X = A, B or C A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

DIAGRAM

NCD5703X

ALYW

PIN CONNECTIONS

VIN

VREF

FLT

DESAT

VIN

VREF

FLT

DESAT

VIN

VREF

FLT

DESAT

NCD5703A

NCD5703B

NCD5703C

CLAMP

GND

VCC

VEE

GND

VCC

GND

VOL

VOH

VCC

ORDERING INFORMATION

See detailed ordering and shipping information on page 9 of this data sheet.

August, 2019 − Rev. 1

1 Publication Order Number:

NCD5703/D

NCD5703A, NCD5703B, NCD5703C

NCD5703A

DESAT

VREF

VCC

VIN

FLT

VCC

CLAMP

GND

NCD5703B

VREF

VIN

FLT

DESAT

VCC

GND

VEE

NCD5703C

VREF

VIN

DESAT

VCC

VOH

VOL

GND

VCC

VEE

VCC

FLT

Figure 1. Simplified Application Schematics

www.onsemi.com

NCD5703A, NCD5703B, NCD5703C

FLT

DESAT

REF

SET

Q S

CLR

Q R

TSD

NCD5703A

DESAT-CHG

DESAT-THR

REF

IN-

Bandgap

UVLO

SET

S Q

CLR

R Q

DELAY

MC-THR

SET

S Q

CLR

R Q

CLAMP

GND

Figure 2(a). Detailed Block Diagram NCD5703A

NCD5703A

CLAMP

VIN

VCC

VREF

FLT

LDO

TSD

VCC

Logic Unit

UVLO

DESAT

Figure 2(b). Simplified Block Diagram NCD5703A

DESAT

CLAMP

GND

VCC

www.onsemi.com

FLT

NCD5703A, NCD5703B, NCD5703C

DESAT

REF

SET

Q S

CLR

Q R

DESAT-CHG

DESAT-THR

IN-L

REF

Bandgap

UVLO

SET

S Q

CLR

R Q

DELAY

TSD

NCD5703B

GND

Figure 3(a). Detailed Block Diagram NCD5703B

NCD5703B

VIN

VCC

VREF

FLT

LDO

TSD

VCC

Logic Unit

UVLO

DESAT

Figure 3(b). Simplified Block Diagram NCD5703B

DESAT

VEE

GND

VCC

www.onsemi.com

FLT

NCD5703A, NCD5703B, NCD5703C

DESAT

REF

SET

Q S

CLR

Q R

DESAT-CHG

DESAT-THR

REF

IN-L

SET

S Q

CLR

R Q

DELAY

TSD

NCD5703C

DELAY

Bandgap

UVLO

GND

Figure 4(a). Detailed Block Diagram NCD5703C

NCD5703C

VIN

VCC

VREF

FLT

LDO

TSD

VCC

UVLO

DESAT

Figure 4(b). Simplified Block Diagram NCD5703C

DESAT

Logic Unit

GND

VOL

VOH

VCC

www.onsemi.com

NCD5703A, NCD5703B, NCD5703C

Table 1. PIN FUNCTION DESCRIPTION

Pin Name No. I/O/x Description

VIN 1 I Input signal to control the output. In applications which require galvanic isolation, VIN is generat-

VREF 2 O 5 V Reference generated within the driver is brought out to this pin for external bypassing and

FLT 3 O Fault open drain output (active low) that allows communication to the main controller that the

DESAT 4 I Input for detecting the desaturation of IGBT due to a fault condition. A capacitor connected to

VCC 5 x Positive bias supply for the driver. The operating range for this pin is from UVLO to the maxi-

(NCD5703A,

NCD5703B)

VOH

(NCD5703C)

VOL

(NCD5703C)

GND

(NCD5703A,

NCD5703B)

GND

(NCD5703C)

VEE

(NCD5703B)

CLAMP

(NCD5703A)

6 O Driver output that provides the appropriate drive voltage, source and sink current to the IGBT

6 O Driver high output that provides the appropriate drive voltage and source current to the IGBT

7 O Driver low output that provides the appropriate drive voltage and sink current to the IGBT gate.

7 x This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors

8 x This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors

8 x A negative voltage with respect to GND can be applied to this pin and that will allow VO to go to

8 I/O Provides clamping for the IGBT gate during the off period to protect it from parasitic turn−on. To

ed at the opto output, the pulse transformer secondary or the digital isolator output. VO (VOH/ VOL) signal is in phase with VIN. VIN is internally clamped to GND and has a pull−down resistor of 1 MW to ensure that an output is low in the absence of an input signal. A minimum pulse− width is required at VIN before VO (VOH/VOL) is activated.

for powering low bias circuits (such as digital isolators).

driver has encountered a fault condition and has deactivated the output. Open drain allows easy setting of (inactive) high level and parallel connection of multiple fault signals. Connect to 10k pull−up resistor recommended. Truth Table is provided in the datasheet to indicate conditions under which this signal is asserted. Capable of driving optos or digital isolators when isolation is required.

this pin allows a programmable blanking delay every ON cycle before DESAT fault is processed, thus preventing false triggering.

mum. A good quality bypassing capacitor is required from this pin to GND and should be placed close to the pins for best results.

gate. VO is actively pulled low during start−up and under Fault conditions.

gate.

VOL is actively pulled low during start−up and under Fault conditions.

should be referenced to this pin and kept at a short distance from the pin.

a negative voltage during OFF state. A good quality bypassing capacitor is needed from VEE to GND. If a negative voltage is not applied or available, this pin must be connected to GND.

be tied directly to IGBT gate with minimum trace length for best results.

www.onsemi.com

NCD5703A, NCD5703B, NCD5703C

Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1)

Parameter Symbol Minimum Maximum Unit

Differential Power Supply VCC−VEE (V

Positive Power Supply VCC−GND −0.3 22 V

Negative Power Supply VEE−GND −18 0.3 V

Gate Output High (VO, VOH)−GND VCC + 0.3 V

Gate Output Low (VO, VOL)−GND VEE − 0.3 V

Input Voltage VIN−GND −0.3 5.5 V

DESAT Voltage V

DESAT

FLT current Sink

Power Dissipation

FLT−SINK

PD 700 mW

SO−8 package

Maximum Junction Temperature T

J(max)

Storage Temperature Range TSTG −65 to 150 °C

ESD Capability, Human Body Model (Note 2) ESDHBM 4 kV

ESD Capability, Machine Model (Note 2) ESDMM 200 V

Moisture Sensitivity Level MSL 1 −

Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 3)

SLD

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78, 25°C

3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

) 0 36 V

max

−GND −0.3 VCC + 0.3 V

150 °C

260 °C

Table 3. THERMAL CHARACTERISTICS

Parameter Symbol Value Unit

Thermal Characteristics, SOIC−8 (Note 4) Thermal Resistance, Junction−to−Air (Note 5)

4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

5. Values based on copper area of 100 mm

(or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.

176

°C/W

Table 4. OPERATING RANGES (Note 6)

Parameter

Differential Power Supply VCC−VEE (V

Positive Power Supply V

Negative Power Supply V

Input Voltage V

Input pulse width t

Ambient Temperature T

6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

Symbol Min Max Unit

) 30 V

max

UVLO 20 V

−15 0 V

0 5 V

40 ns

−40 125 °C

www.onsemi.com

+ 15 hidden pages