TinyLogic UHS D-Type
Flip-Flop with 3-STATE
Output
NC7SZ374
Description
The NC7SZ374 is a single positive edge−triggered D−type CMOS
Flip−Flop with 3−STATE output from ON Semiconductor’s Ultra
High Speed Series of TinyLogic in the space saving SC−88 6−lead
package. The device is fabricated with advanced CMOS technology to
achieve ultra high speed with high output drive while maintaining low
static power dissipation over a very broad V
device is specified to operate over the 1.65 V to 5.5 V V
inputs and output are high impedance when V
voltages up to 5.5 V independent of V
operating range. The
CC
range. The
CC
is 0 V. Inputs tolerate
CC
operating voltage. This
CC
single flip−flop will store the state of the D input that meets the setup
and hold time requirements on the LOW−to−HIGH Clock (CP)
transition. The output tolerates voltages above V
in the 3−STATE
CC
condition.
Features
• Space Saving SC−88 6−Lead Package
• Ultra Small MicroPak™ Leadless Package
• Ultra High Speed: t
• High Output Drive: ±24 mA at 3 V V
• Broad V
Operating Range: 1.65 V to 5.5 V
CC
• Matches the Performance of LCX when Operated at 3.3 V V
= 2.6 ns Typ into 50 pF at 5 V V
PD
CC
CC
CC
• Power Down High Impedance Inputs / Output
• Overvoltage Tolerant Inputs Facilitate 5 V − 3 V Translation
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
IEEC / IEC
OE
CP
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MARKING
DIAGRAMS
SIP6 1.45x1.0
CASE 127EB
Pin 1
SC−88
CASE 419B−02
C9, Z74= Specific Device Code
KK= 2−Digit Lot Run Traceability Code
XY= 2−Digit Date Code Format
Z= Assembly Plant Code
M= Date Code*
G= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
AAA represents Product Code Top Mark − see ordering code.
NOTE: Orientation of Top Mark determines Pin One location.
Read the top product code mark left to right, Pin One
is the lower left pin (see diagram).
Figure 3. Pin 1 Orientation
CP 16 OE
GND 25 V
D 34 Q
CC
Figure 4. MicroPak (Top Through View)
PIN DESCRIPTIONS
Pin NameDescription
D Data Input
CP Clock Pulse Input
OEOutput Enable Input
QFlip−Flop Output
FUNCTION TABLE
InputsOutput
CPDOEQ
LLL
HLH
XLQ
XXHZ
H = HIGH Logic LevelZ = High Impedance
L = LOW Logic LevelQn = No Change in Data
X = Immaterial
n
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Page 3
NC7SZ374
ABSOLUTE MAXIMUM RATINGS
SymbolParameterMinMaxUnit
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
ICC / I
T
STG
T
J
T
L
P
D
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
SymbolParameterConditionsMinMaxUnit
V
CC
V
IN
V
OUT
tr, t
f
T
A
q
JA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Unused inputs must be held HIGH or LOW. They may not float.
Supply Voltage−0.5+6.5V
DC Input Voltage−0.5+6.5V
DC Output Voltage−0.5+6.5V
DC Input Diode CurrentVIN < 0 V−−50mA
DC Output Diode CurrentV
< 0 V−−50mA
OUT
DC Output Source / Sink Current−±50mA
DC VCC / GND Current−±50mA
GND
Storage Temperature Range−65+150°C
Junction Temperature under Bias−150°C
Junction Lead Temperature (Soldering, 10 Seconds)−260°C
Power Dissipation in Still Air
SC−88−332
MicroPak−812
Supply Voltage Operating1.655.5
Supply Voltage Data Retention1.55.5
Input Voltage05.5V
Output Voltage
Active State0V
CC
3−STATE05.5V
Input Rise and Fall Time
VCC = 1.8 V, 2.5 V ±0.2 V020
VCC = 3.3 V ±0.3 V010
V
= 5.5 V ±0.5 V05
CC
Operating Temperature−40+85°C
Thermal Resistance
SC−88−377
MicroPak−154
mW
V
V
ns/V
°C/W
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Page 4
DC ELECTICAL CHARACTERISTICS
SymbolParameterV
V
V
V
V
I
I
OFF
I
HIGH Level Control
IH
Input Voltage
LOW Level Control
IL
Input Voltage
HIGH Level Control
OH
Output Voltage
LOW Level Control
OL
Output Voltage
I
Input Leakage
IN
Current
3−STATE Output
OZ
Leakage
Power Off Leakage
Current
Quiescent Supply
CC
Current
CC
1.65 to 1.950.65 V
2.3 to 5.50.7 V
1.65 to 1.95−−0.35 V
2.3 to 5.5−−0.3 V
1.65
1.81.71.8−1.7−
2.32.22.3−2.2−
3.02.93.0−2.9−
4.54.44.5−4.4−
1.65I
2.3I
3.0I
3.0I
4.5I
1.65
1.8−0.00.1−0.1
2.3−0.00.1−0.1
3.0−0.00.1−0.1
4.5−0.00.1−0.1
1.65I
2.3I
3.0I
3.0I
4.5I
1.65 to 5.50 ≤ VIN ≤ 5.5 V−−±0.1−±1.0
1.65 to 5.5VIN = VIL or V
0.0VIN or V
1.65 to 5.5V
NC7SZ374
(V)Conditions
V
= V
IN
or V
IL
V
= V
IN
or V
IL
0 ≤ V
OUT
= 5.5 V, GND−−1.0−10.0
IN
I
= −100 mA1.551.65−1.55−
IH
OH
= −4 mA1.241.52−1.29−
OH
= −8 mA1.92.15−1.9−
OH
= −16 mA2.42.8−2.4−
OH
= −24 mA2.32.68−2.3−
OH
= −32 mA3.84.2−3.8−
OH
I
= 100 mA−0.00.1−0.1
IH
OL
= 4 mA−0.080.24−0.24
OL
= 8 mA−0.100.3−0.3
OL
= 16 mA−0.150.4−0.4
OL
= 24 mA−0.220.55−0.55
OL
= 32 mA−0.220.55−0.55
OL
IH
≤ 5.5 V
= 5.5 V−−1.0−10
OUT
TA = +25°CTA = −40 to +85°C
MinTypMaxMinMax
−−0.65 V
CC
−−0.7 V
CC
CC
CC
CC
CC
−0.35 V
−0.3 V
−
−
−−±0.5−±5.0
CC
CC
Unit
V
V
V
V
mA
mA
mA
mA
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Page 5
AC ELECTRICAL CHARACTERISTICS
SymbolParameterV
t
t
t
f
PLH
PZL,
PLZ,
MAX
t
t
t
Maximum Clock Frequency
(Figures 5, 7)
, t
Propagation Delay, CP to Q
PHL
(Figures 5, 7)
t
Output Enable Time
PZH
(Figures 5, 8)
t
Output Disable Time
PHZ
(Figures 5, 8)
Setup Time, CP to D
S
(Figures 5, 9)
Hold Time, CP to D
H
(Figures 5, 9)
Pulse Width, CP
W
(Figures 5, 9)
NC7SZ374
TA = +25°CTA = −40 to +85°C
(V)Conditions
CC
C
1.65
1.8−−−100−
L
R
D
S
= Open
1
= 50 pF,
= 500 W,
2.5 ±0.2−−−125−
3.3 ±0.3−−−150−
5.0 ±0.5−−−175−
C
1.65
1.8−6.510.0−11.0
L
R
D
= Open
S
1
= 15 pF,
= 1 MW,
2.5 ±0.2−3.86.5−7.0
3.3 ±0.3−2.84.5−5.0
5.0 ±0.5−2.23.5−3.8
C
3.3 ±0.3
5.0 ±0.5−2.64.0−4.7
1.65
1.8−6.09.0−9.5
2.5 ±0.2−3.76.0−6.6
= 50 pF,
L
= 500 W,
R
D
= Open
S
1
CL = 50 pF,
V
= 2 x VCC,
I
, RD = 500 W,
R
U
S1 = GND for t
S1 = VI for t
PZL
PZH
3.3 ±0.3−2.85.0−5.3
5.0 ±0.5−2.23.7−3.9
1.65
1.8−5.18.0−8.5
2.5 ±0.2−3.56.0−6.3
CL = 50 pF,
V
= 2 x VCC,
I
, RD = 500 W,
R
U
S1 = GND for t
S1 = VI for t
PLZ
PHZ
3.3 ±0.3−2.84.5−4.7
5.0 ±0.5−2.233.7−3.9
C
2.5 ±0.2
3.3 ±0.3−−−2.0−
L
R
D
= Open
S
1
= 50 pF,
= 500 W,
5.0 ±0.5−−1.5−
C
2.5 ±0.2
3.3 ±0.3−−−1.5−
= 50 pF,
L
= 500 W,
R
D
S1 = Open
5.0 ±0.5−−−1.5−
C
2.5 ±0.2
3.3 ±0.3−−−2.8−
L
R
D
S
= Open
1
= 50 pF,
= 500 W,
5.0 ±0.5−−−2.5−
MinTypMaxMinMaxUnit
−−−100−
−9.71.50−16.5
−3.45.5−6.2
−9.013.5−14.3
−7.712.0−13.0
−−−2.5−
−−−1.5−
−−−3.0−
MHz
ns
ns
ns
ns
ns
ns
CAPACITANCE (T
Symbol
C
C
C
Input CapacitanceVCC = Open, VIN = 0 V or V
IN
Output CapacitanceVCC = 3.3 V, VIN = 0 V or V
OUT
Power Dissipation Capacitance (Note 2)VCC = 3.3 V
PD
= +25°C, f = 1 MHz)
A
ParameterConditionTypMaxUnits
CC
CC
3−pF
4−pF
10
V
= 5.0 V
CC
12
−
−
2. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
no output loading and operating at 50% duty cycle. (See Figure 6)
is related to I
C
PD
dynamic operating current by the expression: I
CCD
= (CPD) (VCC) (fIN) + (ICCstatic).
CCD
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5
CCD
pF
) at
Page 6
AC Loading and Waveforms
NC7SZ374
V
CC
V
CC
RU
CP
D
OE
Q
C
RD
L
CL includes load and stray capacitance
Input PRR = 1.0 MHz, t
NC7SZ374L6XC96−Lead MicroPak, 1.00 mm Wide5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
MicroPak is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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Page 7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP6 1.45X1.0
CASE 127EB
ISSUE O
DATE 31 AUG 2016
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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Page 8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
1
SCALE 2:1
D
A
654
E
123
2X
bbb H
D
e
B
TOP VIEW
6X
ccc
C
SIDE VIEWEND VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.30
0.65
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
2X
aaa H D
D
E1
L2
aaa C
2X 3 TIPS
b
6X
M
A2
A
A1
C
6X
0.66
SEATING
PLANE
2.50
DIMENSIONS: MILLIMETERS
Cddd
A-B D
DETAIL A
CASE 419B−02
ISSUE Y
H
L
DETAIL A
GAGE
PLANE
DATE 11 DEC 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
XXX = Specific Device Code
M= Date Code*
G= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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Page 9
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 2:
CANCELLED
STYLE 8:
CANCELLED
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 3:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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Page 10
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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