ON Semiconductor NBC12439, NBC12439A Technical data

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NBC12439, NBC12439A

3.3V/5V Programmable PLL Synthesized Clock Generator

50 MHz to 800 MHz

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Description

The NBC12439 and NBC12439A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the N--output divider, where it can be configured to provide division ratios of 1, 2, 4 or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 16 MHz, 8 MHz, 4 MHz, or 2 MHz can be achieved using a 16 MHz crystal, depending on the output divider settings. The PLL loop filter is fully integrated and does not require any external components.

Features

• Best--in--Class Output Jitter Performance, ±20 ps Peak--to--Peak

• 50 MHz to 800 MHz Programmable Differential PECL Outputs

• Fully Integrated Phase--Lock--Loop with Internal Loop Filter

• Parallel Interface for Programming Counter and Output Dividers

During Powerup

• Minimal Frequency Overshoot

• Serial 3--Wire Programming Interface

• Crystal Oscillator Inputs 10 MHz to 20 MHz

• Operating Range: V

= 3.135 V to 5.25 V

CC

• CMOS and TTL Compatible Control Inputs

• Pin and Function Compatible with Motorola MC12439 and

MPC9239

• Powerdown of PECL Outputs (÷16)

• 0°Cto70°C Ambient Operating Temperature (NBC12439)

• -- 4 0 °Cto85°C Ambient Operating Temperature (NBC12439A)

• Pb--Free Packages are Available

MARKING

DIAGRAMS

128

NBC12439xG

PLCC--28

FN SUFFIX

CASE 776

LQFP--32

FA SUFFIX

CASE 873A

32

1

QFN32

MN SUFFIX

CASE 488AM

x = Blank or A A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week GorG = P b--Free Package

(Note: Microdot may be in either location)

AWLYYWW

NBC12

439x

AWLYYWWG

1

NBC12

439x

AWLYYWWG

G

February, 2007 -- Rev. 10

ORDERING INFORMATION

See detailed ordering and shippinginformation in the package dimensions section on page 16 of this data sheet.

1 Publication Order Number:

NBC12439/D

NBC12439, NBC12439A

XTAL_SEL

FREF_EXT

10--20MHz

S_LOAD

P_LOAD

S_DATA

S_CLOCK

OE

15

28

27

26

PWR_DOWN

2

F

÷ 2

3

4

5

6

7

XTAL1

OSC

XTAL2

REF

7--BIT ÷ M COUNTER

PHASE

DETECTOR

7--BIT SR

VCO

÷ 2

400--800

LATCH

01

POWER

DOWN

÷ N

(1,2,4,8)

MHz

LATCH

01

2--BIT SR 3--BIT SR

+3.3 or 5.0 V

1

PLL_V

CC

LATCH

+3.3 or 5.0 V

21, 25

V

CC

24 23

20

FOUT

TEST

Table 1. Output Division

N [1:0] Output Division

00 01 10 11

8 ¤ 14

7

M[6:0]

17, 18 22, 19

2

N[1:0]

Figure 1. Block Diagram (28 --Lead PLCC)

Tab l e 2. XTAL _ S E L And O E

Input 0 1

2 4 8 1

PWR_DOWN

XTAL_SEL

OE

F

OUT

FREF_EXT

Outputs Disabled

F

÷ 16

OUT

XTAL

Outputs Enabled

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2

NBC12439, NBC12439A

S_CLOCK

S_DATA

S_LOAD

PLL_V

CC

PWR_DOWN

FREF_EXT

XTAL1

VCCFOUT

25 24 23 22 21 20 19

26

27

28

1

2

3

4

56 7891011

FOUT

OE

XTAL2

P_LOAD

GND

M[0]

CC

V

M[1]

Figure 2. 28--Lead PLCC (Top View)

TEST

M[2]

GND

18

N[1]

17

N[0]

16

NC

15

XTAL_SEL

14

M[6]

13

M[5]

12

M[4]

M[3]

S_CLOCK

S_DATA

S_LOAD

PLL_V

PWR_DOWN

FREF_EXT

XTAL1

CC

FOUT

V

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

910111213141516

GND

VCCV

CC

TEST

GND

24

23

22

21

20

19

18

17

N/C

N[1]

N[0]

NC

XTAL_SEL

M[6]

M[5]

M[4]

S_CLOCK

S_DATA

S_LOAD

PLL_V

CC

PLL_V

CC

PWR_DOWN

FREF_EXT

XTAL1

CC

FOUT

V

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

910111213141516

OE

XTAL2

GND

M[0]

P_LOAD

VCCV

M[1]

CC

M[2]

Figure 4. 32--Lead QFN (Top View)

GND

TEST

24

N/C

23

N[1]

22

N[0]

21

NC

20

XTAL_SEL

19

M[6]

18

M[5]

17

M[4]

N/C

M[3]

Exposed Pad (EP)

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3

XTAL2

OE

M[0]

P_LOAD

M[1]

M[2]

M[3]

N/C

Figure 3. 32--Lead LQFP (Top View)

NBC12439, NBC12439A

The following gives a brief description of the functionality of the NBC12439 and NBC12349A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pull--up or pulldownresistors. The PECLoutputs are capable of driving two series terminated 50 Ω transmission lines on the incident edge.

Table 3. PIN FUNCTION DESCRIPTION

Pin Name Function Description

INPUTS

XTAL1, XTAL2 Crystal Inputs These pins form an oscillator when connected to an external series--resonant

S_LOAD* CMOS/TTL Serial Latch Input

S_DATA* CMOS/TTL Serial Data Input

S_CLOCK* CMOS/TTL Serial Clock Input

P_LOAD** CMOS/TTL Parallel Latch Input

M[6:0]** CMOS/TTL PLL Loop Divider

N[1:0]** CMOS/TTL Output Divider Inputs

OE** CMOS/TTL Output Enable Input

FREF_EXT* CMOS/TTL Input

XTAL_SEL** CMOS/TTL Input

PWR_DOWN CMOS/TTL Input

OUTPUTS

FOUT,

FOUT PECL Differential Outputs These differential, positive--referenced ECL signals (PECL) are the outputs of the

TEST CMOS/TTL Output The function of this output is determined by the serial configuration bits T[2:0].

POWER

V

CC

PLL_V

CC

GND Negative Power Supply These pins are the negative supply for the chip and are normally all c onnected to

-- Exposed Pad for QFN--32 only The Exposed Pad (EP) on the QFN--32 package bottom is thermally connected to

* When left Open, these inputs will default LOW. ** When left Open, these inputs will default HIGH.

(Internal Pulldown Resistor)

(Internal Pullup Resistor)

Inputs (Internal Pullup Resistor)

(Internal Pullup Resistor)

(Internal Pulldown Resistor)

(Internal Pullup Resistor)

(Internal Pulldown Resistor)

Positive Supply for the Logic The positive supply for the internal logic and output buffer of the chip, and is con-

Positive Supply for the PLL This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.

crystal.

This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH--to--LOW transition of S_LOAD for proper operation.

This pin acts as the data input to the serial configuration shift registers.

This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.

This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this signal is LOW; therefore, the parallel data must be stable on the LOW--to--HIGH transition of P_LOAD tion.

These pins are used to configure the PLL loop divider. They are s ampled on the LOW--to--HIGH transition of P_LOAD

These pins are used to configure the output divider modulus. They are sampled on the LOW--to--HIGH transition of P_LOAD

Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output.

This pin can be used as the PLL Reference

This pin selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH selects the crystal input.

PWR_DOWN forces the FOUT outputs to synchronously reduce frequency by a factor of 16.

synthesizer.

nected to +3.3 V or +5.0 V.

ground.

the die for improved heat transfer out of package. The exposed pad must be attached to a heat--sinking conduit. The pad is electrically connected to GND.

. M[6] is the MSB, M[0] is the LSB.

.

for proper opera-

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NBC12439, NBC12439A

Table 4. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity (Note 1) Pb Pkg Pb--Free Pkg

PLCC LQFP

QFN

Level 1 Level 2 Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V--0 @ 0.125 in

Transistor Count 2269

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 5. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

CC

V

I

out

T

A

T

stg

θ

JA

θ

JC

θ

JA

θ

JC

θ

JA

θ

JC

T

sol

Stresses exceeding Maximum Ratings may damage the device. Maximu m Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to s tresses above the Recommended Operating Conditions may affect device reliability.

Positive Supply GND = 0 V 6 V

Input Voltage GND = 0 V VI± V

CC

Output Current Continuous

Surge

Operating Temperature Range

NB12439

NB12439A

Storage Temperature Range --65 to +150 °C

Thermal Resistance (Junction--to--Ambient) 0lfpm

500 lfpm

PLCC--28 PLCC--28

Thermal Resistance (Junction--to--Case) Standard Board PLCC--28 22 to 26 °C/W

Thermal Resistance (Junction--to--Ambient) 0lfpm

500 lfpm

LQFP--32 LQFP--32

Thermal Resistance (Junction--to--Case) Standard Board LQFP--32 12 to 17 °C/W

Thermal Resistance (Junction--to--Ambient) 0lfpm

500 lfpm

QFN--32 QFN--32

Thermal Resistance (Junction--to--Case) 2S2P QFN--32 12 °C/W

Wave Solder

<3 sec @ 248°C

Pb

Pb--Free

<3 sec @ 260°C

75 k Ω

37.5 k Ω

>2kV

> 150 V

>1kV

Level 1 Level 2 Level 1

-- 4 0 t o + 8 5

6 V

50

100

0to70

63.5

43.5

80 55

31 27

265 265

mA mA

°C

°C/W °C/W

°C

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NBC12439, NBC12439A

Table 6. DC CHARACTERISTICS (V

Symbol

V

IH

LVC M O S/

Input HIGH Voltage VCC=3.3V 2.0 V

=3.3V± 5%; TA=0°Cto70°C (NBC12439), TA=--40°Cto85°C (NBC12439A))

CC

Characteristic Condition Min Typ Max Unit

LVTTL

V

IL

LVC M O S/

Input LOW Voltage VCC=3.3V 0.8 V

LVTTL

I

IN

V

OH

Input Current 1.0 mA

Output HIGH Voltage

IOH=--0.8mA 2.5 V

TEST

V

OL

Output LOW Voltage

IOL=0.8mA 0.4 V

TEST

V

OH

PECL

Output HIGH Voltage

FOUT

VCC=3.3V (Notes 2, 3)

2.155 2.405 V

FOUT

V

OL

PECL

Output LOW Voltage

FOUT

VCC=3.3V (Notes 2, 3)

1.355 1.675 V

FOUT

I

CC

Power Supply Current

PLL_V

V

CC

441958238028mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

2. F

OUT/FOUT

3. F

OUT/FOUT

Table 7. DC CHARACTERISTICS (V

Symbol

V

IH

CMOS/

output levels will vary 1:1 with VCCvariation. outputs are terminated through a 50 Ω resistor to VCC-- 2.0 volts.

=5.0V± 5%; TA=0°Cto70°C (NBC12439), TA=--40°Cto85°C (NBC12439A))

CC

Characteristic Condition Min Typ Max Min Typ Max Min Typ Max Unit

Input HIGH Voltage VCC=5.0V 2.0 2.0 2.0 V

TTL

V

IL

CMOS/

Input LOW Voltage VCC=5.0V 0.8 0.8 0.8 V

TTL

I

IN

V

OH

Input Current 1.0 1.0 1.0 mA

Output HIGH Voltage

IOH=--0.8mA 2.5 2.5 2.5 V

TEST

V

OL

Output LOW Voltage

IOL=0.8mA 0.4 0.4 0.4 V

TEST

V

OH

PECL

Output HIGH Voltage

FOUT

VCC=5.0V (Notes 4, 5)

3.855 4.105 3.855 4.105 3.855 4.105 V

FOUT

V

OL

PECL

Output LOW Voltage

FOUT

VCC=5.0V (Notes 4, 5)

3.055 3.305 3.055 3.305 3.055 3.305 V

FOUT

I

CC

Power Supply Current

PLL_V

V

CC

47195824852847

60248528471960248528mA

19

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

4. F

5. F

OUT/FOUT OUT/FOUT

output levels will vary 1:1 with VCCvariation. outputs are terminated through a 50 Ω resistor to VCC-- 2.0 volts.

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