ON Semiconductor NBC12430, NBC12430A Technical data
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NBC12430, NBC12430A
3.3V/5VProgrammable PLL
Synthesized Clock
Generator
50 MHz to 800 MHz
The NBC12430 and NBC12430A are general purpose, PLL based
synthesized clock sources. The VCO will operate over a frequency
range of 400 MHz to 800 MHz. The VCO frequency is sent to the
N−output divider, where it can be configured to provide division ratios
of 1, 2, 4, or 8. The VCO and output frequency can be programmed
using the parallel or serial interfaces to the configuration logic. Output
frequency steps of 250 KHz, 500 KHz, 1.0 MHz, 2.0 MHz can be
achieved using a 16 MHz crystal, depending on the output dividers
settings. The PLL loop filter is fully integrated and does not require
any external components.
• Best−in−Class Output Jitter Performance, ±20 ps Peak−to−Peak
• 50 MHz to 800 MHz Programmable Differential PECL Outputs
• Fully Integrated Phase−Lock−Loop with Internal Loop Filter
• Parallel Interface for Programming Counter and Output Dividers
During Powerup
• Minimal Frequency Overshoot
• Serial 3−Wire Programming Interface
• Crystal Oscillator Interface
• Operating Range: V
• CMOS and TTL Compatible Control Inputs
• Pin and Function Compatible with Motorola MC12430 and
MPC9230
• 0°C to 70°C Ambient Operating Temperature (NBC12430)
• −40°C to 85°C Ambient Operating Temperature (NBC12430A)
• Pb−Free Packages are Available*
= 3.135 V to 5.25 V
CC
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MARKING
DIAGRAMS
128
NBC12430x
PLCC−28
FN SUFFIX
CASE 776
LQFP−32
FA SUFFIX
CASE 873A
x = Blank or A
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
AWLYYWW
NBC12430x
AWLYYWW
32
1
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2004
December, 2004 − Rev. 5
1 Publication Order Number:
NBC12430/D
XTAL_SEL
FREF_EXT
10−20MHz
S_LOAD
P_LOAD
OE
28
NBC12430, NBC12430A
+3.3 or 5.0 V
1
1 MHz F
16 MHz Crystal
16
with
REF
PHASE
DETECTOR
3
2
4
XTAL1
9−BIT M
COUNTER
2
OSC
5
6
XTAL2
LATCH
VCO
400−800
MHz
7
01
PLL_V
CC
N
(1, 2, 4, 8)
LATCH
01
LATCH
+3.3 or 5.0 V
21, 25
V
CC
24
23
20
F
OUT
F
OUT
TEST
S_DATA
S_CLOCK
27
26
Table 1. Output Division
N [1:0] Output Division
0 0
0 1
1 0
1 1
VCCF
25 24 23 22 21 20 19
CC
26
27
28
1
2
3
4
56 7891011
S_CLOCK
S_DATA
S_LOAD
PLL_V
FREF_EXT
XTAL_SEL
XTAL1
OUTFOUT
9−BIT SR
2−BIT SR 3−BIT SR
8 → 16
9
M[8:0]
Figure 1. Block Diagram (PLCC−28)
Table 2. XTAL_SEL And OE
2
4
8
1
CC
GND
V
TEST
GND
18
17
16
15
14
13
12
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
S_CLOCK
FREF_EXT
XTAL_SEL
17, 18 22, 19
2
N[1:0]
Input 0 1
XTAL_SEL
S_DATA
S_LOAD
PLL_V
PLL_V
XTAL1
CC
CC
OE
1
2
3
4
5
6
7
8
FREF_EXT
Outputs Disabled
CC
OUTFOUT
F
V
32 31 30 29 28 27 26 25
910111213141516
GND
VCCV
XTAL
Outputs Enabled
CC
GND
TEST
24
23
22
21
20
19
18
17
N/C
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
OE
XTAL2
M[0]
P_LOAD
M[1]
M[2]
Figure 2. 28−Lead PLCC (Top View)
M[3]
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2
XTAL2
OE
M[0]
P_LOAD
M[1]
M[2]
M[3]
N/C
Figure 3. 32−Lead LQFP (Top View)
NBC12430, NBC12430A
The following gives a brief description of the functionality of the NBC12430 and NBC12430A Inputs and Outputs. Unless
explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable
of driving two series terminated 50 transmission lines on the incident edge.
PIN FUNCTION DESCRIPTION
Pin Name Function Description
INPUTS
XTAL1, XTAL2
S_LOAD* CMOS/TTL Serial Latch Input
S_DATA* CMOS/TTL Serial Data Input
S_CLOCK* CMOS/TTL Serial Clock Input
P_LOAD** CMOS/TTL Parallel Latch Input
M[8:0]** CMOS/TTL PLL Loop Divider
N[1:0]** CMOS/TTL Output Divider Inputs
OE** CMOS/TTL Output Enable Input
FREF_EXT* CMOS/TTL Input
XTAL_SEL** CMOS/TTL Input
OUTPUTS
F
, F
OUT
OUT
TEST PECL Output The function of this output is determined by the serial configuration bits T[2:0].
POWER
V
CC
PLL_V
CC
GND Negative Power Supply These pins are the negative supply for the chip and are normally all connected to
* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
Crystal Inputs These pins form an oscillator when connected to an external series−resonant
(Internal Pulldown Resistor)
(Internal Pulldown Resistor)
(Internal Pulldown Resistor)
(Internal Pullup Resistor)
Inputs (Internal Pullup Resistor)
(Internal Pullup Resistor)
(Internal Pullup Resistor)
(Internal Pulldown Resistor)
(Internal Pullup Resistor)
PECL Differential Outputs These differential, positive−referenced ECL signals (PECL) are the outputs of the
Positive Supply for the Logic The positive supply for the internal logic and output buffer of the chip, and is con-
Positive Supply for the PLL This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
crystal.
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH−to−LOW transition of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW−to−HIGH transition of P_LOAD
tion.
These pins are used to configure the PLL loop divider. They are sampled on the
LOW−to−HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled
on the LOW−to−HIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the F
This pin can be used as the PLL Reference
This pin selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH selects the crystal input.
synthesizer.
nected to +3.3 V or +5.0 V.
ground.
OUT
output.
for proper opera-
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NBC12430, NBC12430A
ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 k
Internal Input Pullup Resistor 37.5 k
ESD Protection Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
PLCC
LQFP
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @
Transistor Count 2011
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Units
V
CC
V
I
I
out
T
A
T
stg
JA
JC
JA
JC
T
sol
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Positive Supply GND = 0 V 6 V
Input Voltage GND = 0 V VI V
CC
Output Current Continuous
Surge
Operating Temperature Range
NBC12430
NBC12430A
Storage Temperature Range −65 to +150 °C
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
PLCC−28
PLCC−28
Thermal Resistance (Junction−to−Case) Standard Board PLCC−28 22 to 26 °C/W
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
LQFP−32
LQFP−32
Thermal Resistance (Junction−to−Case) Standard Board LQFP−32 12 to 17 °C/W
Wave Solder
Pb
Pb−Free
<3 sec @ 248°C
<3 sec @ 260°C
> 2 kV
> 150 V
> 1 kV
Level 1
Level 2
0.125 in
6 V
50
100
0 to 70
−40 to +85
63.5
43.5
80
55
265
265
mA
mA
°C
°C/W
°C/W
°C/W
°C/W
°C
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NBC12430, NBC12430A
DC CHARACTERISTICS (V
Symbol
V
IH
LVCMOS/
Input HIGH Voltage VCC = 3.3 V 2.0 V
= 3.3 V ± 5%; TA = 0°C to 70°C (NBC12430), TA = −40°C to 85°C (NBC12430A))
CC
Characteristic Condition Min Typ Max Unit
LVTTL
V
IL
LVCMOS/
Input LOW Voltage VCC = 3.3 V 0.8 V
LVTTL
I
IN
V
OH
PECL
Input Current 1.0 mA
Output HIGH Voltage
F
F
OUT
OUT
VCC = 3.3 V
(Notes 2, 3)
2.155 2.405 V
TEST
V
OL
PECL
Output LOW Voltage
F
F
OUT
OUT
VCC = 3.3 V
(Notes 2, 3)
1.355 1.605 V
TESt
I
CC
Power Supply Current
PLL_V
V
CC
CC
451758258030mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. F
3. F
OUT/FOUT
OUT/FOUT
and TEST output levels will vary 1:1 with VCC variation.
and TEST outputs are terminated through a 50 resistor to VCC − 2.0 V.
mA
DC CHARACTERISTICS (V
Symbol
V
IH
CMOS/
Input HIGH Voltage VCC = 5.0 V 2.0 V
= 5.0 V ± 5%; TA = 0°C to 70°C (NBC12430), TA = −40°C to 85°C (NBC12430A))
CC
Characteristic Condition Min Typ Max Unit
TTL
V
IL
CMOS/
Input LOW Voltage VCC = 5.0 V 0.8 V
TTL
I
IN
V
OH
PECL
Input Current 1.0 mA
Output HIGH Voltage
F
F
OUT
OUT
VCC = 5.0 V
(Notes 4, 5)
3.855 4.105 V
TEST
V
OL
PECL
Output LOW Voltage
F
F
OUT
OUT
VCC = 5.0 V
(Notes 4, 5)
3.055 3.305 V
TEST
I
CC
Power Supply Current
PLL_V
V
CC
CC
501860248530mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. F
5. F
OUT/FOUT
OUT/FOUT
and TEST output levels will vary 1:1 with VCC variation.
and TEST outputs are terminated through a 50 resistor to VCC − 2.0 V.
mA
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NBC12430, NBC12430A
AC CHARACTERISTICS (V
Symbol
F
MAXI
F
MAXO
t
LOCK
t
jitter(pd)
t
jitter(cyc−cyc)
t
s
t
h
tpw
MIN
Maximum Input Frequency S_CLOCK
Maximum Output Frequency VCO (Internal)
Maximum PLL Lock Time 10 ms
Period Jitter (RMS) (1) 50 MHz f
Cycle−to−Cycle Jitter (Peak−to−Peak) (8) 50 MHz f
Setup Time S_DATA to S_CLOCK
Hold Time S_DATA to S_CLOCK
Minimum Pulse Width S_LOAD
= 3.135 V to 5.25 V ± 5%; TA = 0°C to 70°C (NBC12430), TA = −40°C to 85°C (NBC12430A)) (Note 7)
CC
Characteristic Condition Min Max Unit
XTAL Oscillator
FREF_EXT (Note 8)
F
OUT
(Note 6)
100 MHz f
100 MHz f
< 100 MHz
OUT
< 800 MHz
OUT
< 100 MHz
OUT
< 800 MHz
OUT
10
10
400
50
10
20
20
800
800
8
5
40
20
20
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
M, N to P_LOAD
20
50
P_LOAD
50
MHz
MHz
ps
ps
ns
ns
ns
DCO Output Duty Cycle 47.5 52.5 %
tr, t
f
Output Rise/Fall F
20%−80% 175 425 ps
OUT
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as
a test clock in TEST_MODE 6.
7. F
OUT/FOUT
8. Maximum frequency on FREF_EXT is a function of setting the appropriate M counter value, 160 M 511, for the VCO to operate within
the valid range of 400 MHz f
and TEST outputs are terminated through a 50 resistor to VCC − 2.0 V.
800 MHz. (See Table 5)
VCO
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