Datasheet NBC12430, NBC12430A Datasheet (ON Semiconductor)

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NBC12430, NBC12430A

3.3V/5VProgrammable PLL
Synthesized Clock
Generator

50 MHz to 800 MHz

The NBC12430 and NBC12430A are general purpose, PLL based
synthesized clock sources. The VCO will operate over a frequency
range of 400 MHz to 800 MHz. The VCO frequency is sent to the
N−output divider, where it can be configured to provide division ratios
of 1, 2, 4, or 8. The VCO and output frequency can be programmed
using the parallel or serial interfaces to the configuration logic. Output
frequency steps of 250 KHz, 500 KHz, 1.0 MHz, 2.0 MHz can be
achieved using a 16 MHz crystal, depending on the output dividers
settings. The PLL loop filter is fully integrated and does not require
any external components.

• Best−in−Class Output Jitter Performance, ±20 ps Peak−to−Peak

• 50 MHz to 800 MHz Programmable Differential PECL Outputs

• Fully Integrated Phase−Lock−Loop with Internal Loop Filter

• Parallel Interface for Programming Counter and Output Dividers

During Powerup

• Minimal Frequency Overshoot

• Serial 3−Wire Programming Interface

• Crystal Oscillator Interface

• Operating Range: V

• CMOS and TTL Compatible Control Inputs

• Pin and Function Compatible with Motorola MC12430 and

MPC9230

• 0°C to 70°C Ambient Operating Temperature (NBC12430)

• −40°C to 85°C Ambient Operating Temperature (NBC12430A)

• Pb−Free Packages are Available*

= 3.135 V to 5.25 V

CC

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MARKING

DIAGRAMS

128

NBC12430x

PLCC−28

FN SUFFIX

CASE 776

LQFP−32

FA SUFFIX

CASE 873A

x = Blank or A
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.

AWLYYWW

NBC12430x
AWLYYWW

32

1

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2004

December, 2004 − Rev. 5

1 Publication Order Number:

NBC12430/D

XTAL_SEL

FREF_EXT

10−20MHz

S_LOAD
P_LOAD

OE

28

NBC12430, NBC12430A

+3.3 or 5.0 V

1

1 MHz F

16 MHz Crystal

 16

with

REF

PHASE

DETECTOR

3
2

4

XTAL1

9−BIT  M
COUNTER

 2

OSC

5
6

XTAL2

LATCH

VCO

400−800

MHz

7

01

PLL_V

CC

 N

(1, 2, 4, 8)

LATCH

01

LATCH

+3.3 or 5.0 V

21, 25

V

CC

24
23

20

F

OUT

F

OUT

TEST

S_DATA

S_CLOCK

27

26

Table 1. Output Division

N [1:0] Output Division

0 0
0 1
1 0
1 1

VCCF

25 24 23 22 21 20 19

CC

26

27

28

1

2

3

4

56 7891011

S_CLOCK

S_DATA

S_LOAD

PLL_V

FREF_EXT

XTAL_SEL

XTAL1

OUTFOUT

9−BIT SR

2−BIT SR 3−BIT SR

8 → 16

9

M[8:0]

Figure 1. Block Diagram (PLCC−28)

Table 2. XTAL_SEL And OE

2
4
8
1

CC

GND

V

TEST

GND

18

17

16

15

14

13

12

N[1]

N[0]

M[8]

M[7]

M[6]

M[5]

M[4]

S_CLOCK

FREF_EXT

XTAL_SEL

17, 18 22, 19

2

N[1:0]

Input 0 1

XTAL_SEL

S_DATA

S_LOAD

PLL_V
PLL_V

XTAL1

CC
CC

OE

1
2
3
4
5
6
7
8

FREF_EXT

Outputs Disabled

CC

OUTFOUT

F

V

32 31 30 29 28 27 26 25

910111213141516

GND

VCCV

XTAL

Outputs Enabled

CC

GND

TEST

24
23
22
21
20
19
18
17

N/C
N[1]

N[0]
M[8]
M[7]
M[6]
M[5]
M[4]

OE

XTAL2

M[0]

P_LOAD

M[1]

M[2]

Figure 2. 28−Lead PLCC (Top View)

M[3]

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2

XTAL2

OE

M[0]

P_LOAD

M[1]

M[2]

M[3]

N/C

Figure 3. 32−Lead LQFP (Top View)

NBC12430, NBC12430A

The following gives a brief description of the functionality of the NBC12430 and NBC12430A Inputs and Outputs. Unless
explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable
of driving two series terminated 50  transmission lines on the incident edge.

PIN FUNCTION DESCRIPTION

Pin Name Function Description

INPUTS

XTAL1, XTAL2

S_LOAD* CMOS/TTL Serial Latch Input

S_DATA* CMOS/TTL Serial Data Input

S_CLOCK* CMOS/TTL Serial Clock Input

P_LOAD** CMOS/TTL Parallel Latch Input

M[8:0]** CMOS/TTL PLL Loop Divider

N[1:0]** CMOS/TTL Output Divider Inputs

OE** CMOS/TTL Output Enable Input

FREF_EXT* CMOS/TTL Input

XTAL_SEL** CMOS/TTL Input

OUTPUTS

F

, F

OUT

OUT

TEST PECL Output The function of this output is determined by the serial configuration bits T[2:0].

POWER

V

CC

PLL_V

CC

GND Negative Power Supply These pins are the negative supply for the chip and are normally all connected to

* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.

Crystal Inputs These pins form an oscillator when connected to an external series−resonant

(Internal Pulldown Resistor)

(Internal Pulldown Resistor)

(Internal Pulldown Resistor)

(Internal Pullup Resistor)

Inputs (Internal Pullup Resistor)

(Internal Pullup Resistor)

(Internal Pullup Resistor)

(Internal Pulldown Resistor)

(Internal Pullup Resistor)

PECL Differential Outputs These differential, positive−referenced ECL signals (PECL) are the outputs of the

Positive Supply for the Logic The positive supply for the internal logic and output buffer of the chip, and is con-

Positive Supply for the PLL This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.

crystal.
This pin loads the configuration latches with the contents of the shift registers. The

latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH−to−LOW transition of S_LOAD for proper operation.

This pin acts as the data input to the serial configuration shift registers.

This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.

This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW−to−HIGH transition of P_LOAD
tion.

These pins are used to configure the PLL loop divider. They are sampled on the
LOW−to−HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.

These pins are used to configure the output divider modulus. They are sampled
on the LOW−to−HIGH transition of P_LOAD.

Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the F

This pin can be used as the PLL Reference

This pin selects between the crystal and the FREF_EXT source for the PLL refer­ence signal. A HIGH selects the crystal input.

synthesizer.

nected to +3.3 V or +5.0 V.

ground.

OUT

output.

for proper opera-

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3

NBC12430, NBC12430A

ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 k
Internal Input Pullup Resistor 37.5 k
ESD Protection Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity (Note 1)

PLCC
LQFP

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @

Transistor Count 2011
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Units

V

CC

V

I

I

out

T

A

T

stg



JA



JC



JA



JC

T

sol

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

Positive Supply GND = 0 V 6 V
Input Voltage GND = 0 V VI  V

CC

Output Current Continuous

Surge

Operating Temperature Range

NBC12430

NBC12430A
Storage Temperature Range −65 to +150 °C
Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

PLCC−28

PLCC−28
Thermal Resistance (Junction−to−Case) Standard Board PLCC−28 22 to 26 °C/W
Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

LQFP−32

LQFP−32
Thermal Resistance (Junction−to−Case) Standard Board LQFP−32 12 to 17 °C/W
Wave Solder

Pb

Pb−Free

<3 sec @ 248°C
<3 sec @ 260°C

> 2 kV

> 150 V

> 1 kV

Level 1
Level 2

0.125 in

6 V

50

100

0 to 70

−40 to +85

63.5

43.5

80
55

265
265

mA
mA

°C

°C/W
°C/W

°C/W
°C/W

°C

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4

NBC12430, NBC12430A

DC CHARACTERISTICS (V

Symbol

V

IH

LVCMOS/

Input HIGH Voltage VCC = 3.3 V 2.0 V

= 3.3 V ± 5%; TA = 0°C to 70°C (NBC12430), TA = −40°C to 85°C (NBC12430A))

CC

Characteristic Condition Min Typ Max Unit

LVTTL
V

IL

LVCMOS/

Input LOW Voltage VCC = 3.3 V 0.8 V

LVTTL
I

IN

V

OH

PECL

Input Current 1.0 mA
Output HIGH Voltage

F
F

OUT
OUT

VCC = 3.3 V
(Notes 2, 3)

2.155 2.405 V

TEST

V

OL

PECL

Output LOW Voltage

F
F

OUT
OUT

VCC = 3.3 V
(Notes 2, 3)

1.355 1.605 V

TESt

I

CC

Power Supply Current

PLL_V

V

CC
CC

451758258030mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

2. F

3. F

OUT/FOUT
OUT/FOUT

and TEST output levels will vary 1:1 with VCC variation.
and TEST outputs are terminated through a 50  resistor to VCC − 2.0 V.

mA

DC CHARACTERISTICS (V

Symbol

V

IH

CMOS/

Input HIGH Voltage VCC = 5.0 V 2.0 V

= 5.0 V ± 5%; TA = 0°C to 70°C (NBC12430), TA = −40°C to 85°C (NBC12430A))

CC

Characteristic Condition Min Typ Max Unit

TTL
V

IL

CMOS/

Input LOW Voltage VCC = 5.0 V 0.8 V

TTL
I

IN

V

OH

PECL

Input Current 1.0 mA
Output HIGH Voltage

F
F

OUT
OUT

VCC = 5.0 V
(Notes 4, 5)

3.855 4.105 V

TEST

V

OL

PECL

Output LOW Voltage

F
F

OUT
OUT

VCC = 5.0 V
(Notes 4, 5)

3.055 3.305 V

TEST

I

CC

Power Supply Current

PLL_V

V

CC
CC

501860248530mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

4. F

5. F

OUT/FOUT
OUT/FOUT

and TEST output levels will vary 1:1 with VCC variation.
and TEST outputs are terminated through a 50  resistor to VCC − 2.0 V.

mA

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NBC12430, NBC12430A

AC CHARACTERISTICS (V

Symbol

F

MAXI

F

MAXO

t

LOCK

t

jitter(pd)

t

jitter(cyc−cyc)

t

s

t

h

tpw

MIN

Maximum Input Frequency S_CLOCK

Maximum Output Frequency VCO (Internal)

Maximum PLL Lock Time 10 ms
Period Jitter (RMS) (1) 50 MHz  f

Cycle−to−Cycle Jitter (Peak−to−Peak) (8) 50 MHz  f

Setup Time S_DATA to S_CLOCK

Hold Time S_DATA to S_CLOCK

Minimum Pulse Width S_LOAD

= 3.135 V to 5.25 V ± 5%; TA = 0°C to 70°C (NBC12430), TA = −40°C to 85°C (NBC12430A)) (Note 7)

CC

Characteristic Condition Min Max Unit

XTAL Oscillator

FREF_EXT (Note 8)

F

OUT

(Note 6)

100 MHz  f

100 MHz  f

< 100 MHz

OUT

< 800 MHz

OUT

< 100 MHz

OUT

< 800 MHz

OUT

10
10

400

50

10
20
20

800
800

8
5

40
20

20

S_CLOCK to S_LOAD

M, N to P_LOAD

20
20

20

M, N to P_LOAD

20
50

P_LOAD

50

MHz

MHz

ps

ps

ns

ns

ns

DCO Output Duty Cycle 47.5 52.5 %
tr, t

f

Output Rise/Fall F

20%−80% 175 425 ps

OUT

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

6. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as
a test clock in TEST_MODE 6.

7. F

OUT/FOUT

8. Maximum frequency on FREF_EXT is a function of setting the appropriate M counter value, 160  M  511, for the VCO to operate within
the valid range of 400 MHz  f

and TEST outputs are terminated through a 50  resistor to VCC − 2.0 V.

 800 MHz. (See Table 5)

VCO

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6

NBC12430, NBC12430A

M

FUNCTIONAL DESCRIPTION

The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the
reference oscillator is divided by 16 before being sent to the
phase detector. With a 16 MHz crystal, this provides a
reference frequency of 1 MHz. Although this data sheet
illustrates functionality only for a 16 MHz crystal, Table 3,
any crystal in the 10−20 MHz range can be used, Table 5.

The VCO within the PLL operates over a range of 400 to
800 MHz. Its output is scaled by a divider that is configured
by either the serial or parallel interfaces. The output of this
loop divider is also applied to the phase detector.

The phase detector and the loop filter force the VCO
output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve loop lock.

The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. This
output divider (N divider) is configured through either the
serial or the parallel interfaces and can provide one of four
division ratios (1, 2, 4, or 8). This divider extends the
performance of the part while providing a 50% duty cycle.

The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission lines
terminated into 50  to V

−2.0 V. The positive reference

CC

for the output driver and the internal logic is separated from
the power supply for the phase−locked loop to minimize
noise induced jitter.

The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the M[8:0]
and N[1:0] inputs to configure the internal counters.
Normally upon system reset, the P_LOAD

input is held
LOW until sometime after power becomes valid. On the
LOW−to−HIGH transition of P_LOAD

, the parallel inputs
are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the
M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.

The serial interface logic is implemented with a fourteen
bit shift register scheme. The register shifts once per rising
edge of the S_CLOCK input. The serial input S_DATA must
meet setup and hold timing as specified in the AC
Characteristics section of this document. With P_LOAD
held high, the configuration latches will capture the value of
the shift register on the HIGH−to−LOW edge of the
S_LOAD input. See the programming section for more
information.

The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream. See
the programming section for more information.

Table 3. Programming VCO Frequency Function Table with 16 MHz Crystal.

VCO

Frequency

(MHz)

400
402
404
406

•

•

•

794
796
798
800

Count

Divisor

200
201
202
203

•

•

•

397
398
399
400

256

M8

0
0
0
0

•

•

•

1
1
1
1

128

M7

1
1
1
1

•

•

•

1
1
1
1

64

M6

32

M5

1
1
1
1

•

•

•

0
0
0
0

0
0
0
0

•

•

•

0
0
0
0

16

M4

0
0
0
0

•

•

•

0
0
0
1

M3

8

1
1
1
1

•

•

•

1
1
1
0

M2

4

0
0
0
0

•

•

•

1
1
1
0

M1

2

0
0
1
1

•

•

•

0
1
1
0

1

M0

0
1
0
1

•

•

•

1
0
1
0

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NBC12430, NBC12430A

PROGRAMMING INTERFACE

Programming the NBC12430 and NBC12430A is
accomplished by properly configuring the internal dividers
to produce the desired frequency at the outputs. The output
frequency can by represented by this formula:

F

OUT

where F

 ((F

is the crystal frequency, M is the loop divider

XTAL

XTAL

or F

REF_EXT

)  16) 2M  N

(eq. 1)

modulus, and N is the output divider modulus. Note that it
is possible to select values of M such that the PLL is unable
to achieve loop lock. To avoid this, always make sure that M
is selected to be 200 ≤ M ≤ 400 for a 16 MHz input reference.

Assuming that a 16 MHz reference frequency is used the
above equation reduces to:

F

OUT

 2M N

(eq. 2)

Substituting the four values for N (1, 2, 4, 8) yields:

Table 4. Programmable Output Divider Function Table

N

N1 N0

1 1 1 M  2 400−800 2 MHz
0 0 2 M 200−400 1 MHz
0 1 4 M  2 100−200 500 kHz
1 0 8 M  4 50−100 250 kHz

*For crystal frequency of 16 MHz.

Divider

F

OUT

Output

Frequency

Range (MHz)*

F

OUT

Step

The user can identify the proper M and N values for the
desired frequency from the above equations. The four output
frequency ranges established by N are 400−800 MHz,
200−400 MHz, 100−200 MHz a nd 5 0−100 MHz, respectively.
From these ranges, the user will establish the value of N
required. The value of M can then be calculated based on
equation 1. For example, if an output frequency of 1 31 MHz
was desired, t he f ollowing s teps w ould b e t aken t o i dentify t he
appropriate M and N values. 131 MHz falls within the
frequency range set by an N value of 4; thus, N [1:0] = 01.
For N = 4, F

= M ÷ 2 and M = 2 x F

OUT

. Therefore,

OUT

M = 131 x 2 = 262, so M[8:0] = 100000110. Following this
same procedure, a user can generate any whole frequency
desired between 50 and 800 MHz. Note that for N > 2,
fractional values of F

can be realized. The size of the

OUT

programmable frequency steps (and thus, t he i ndicator o f t he
fractional output frequencies achievable) will be equal to
F

÷ 16 ÷ N.

XTAL

For input reference frequencies other than 16 MHz, see
Table 5, which shows the usable VCO frequency and M
divider range.

The input frequency and the selection of the feedback
divider M is limited by the VCO frequency range and
F

. M must be configured to match the VCO frequency

XTAL

range of 400 to 800 MHz in order to achieve stable PLL
operation.

M

 f

min

M

max

VCOmin

 f

VCOmax

 2(f

 2(f

XTAL

XTAL

 16) and

 16)

(eq. 3)
(eq. 4)

The value for M falls within the constraints set for PLL
stability . If the value for M fell outside of the valid range, a
different N value would be selected to move M in the
appropriate direction.

The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is
controlled via the P_LOAD

signal such that a LOW to HIGH
transition will latch the information present on the M[8:0]
and N[1:0] inputs into the M and N counters. When the
P_LOAD signal is LOW, the input latches will be
transparent and any changes on the M[8:0] and N[1:0] inputs
will affect the F

output pair. To use the serial port, the

OUT

S_CLOCK signal samples the information on the S_DATA
line and loads it into a 14 bit shift register. Note that the
P_LOAD signal must be HIGH for the serial load operation
to function. The Test register is loaded with the first three
bits, the N register with the next two, and the M register with
the final nine bits of the data stream on the S_DATA input.
For each register, the most significant bit is loaded first (T2,
N1, and M8). A pulse on the S_LOAD pin after the shift
register is fully loaded will transfer the divide values into the
counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters.
Figures 4 and 5 illustrate the timing diagram for both a
parallel and a serial load of the device synthesizer.

M[8:0] and N[1:0] are normally specified once at
power−up through the parallel interface, and then possibly
again through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine−tune the clock as the ability to control the serial
interface becomes available.

The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. The T2, T1, and T0 control bits are preset
to ‘000’ when P_LOAD

is LOW so that the PECL F

OUT

outputs are as jitter−free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter
of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select on e
of the alternate functions for this pin.

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8

NBC12430, NBC12430A

Á

Á

Table 5. Frequency Operating Range

Output Frequency (MHz) for

F

ББББББББББББББББББББББ

M

VCO Frequency (MHz) Range for a Crystal Frequency (MHz) of:

M[8:0]

10

12

14

16

18

ББББББББ

20

1

160 010100000 400
170 010101010 425
180 010110100 405 450
190 010111110 427.5 475
200 011001000 400 450 500 400 200 100 50
210 011010010 420 472.5 525 420 210 105 52.5
220 011011100 440 495 550 440 220 110 55
230 011100110 402.5 460 517.5 575 460 230 115 57.5
240 011110000 420 480 540 600 480 240 120 60
250 011111010 437.5 500 562.5 625 500 250 125 62.5
260 100000100 455 520 585 650 520 260 130 65
270 100001110 405 472.5 540 607.5 675 540 270 135 67.5
280 100011000 420 490 560 630 700 560 280 140 70
290 100100010 435 507.5 580 652.5 725 580 290 145 72.5
300 100101100 450 525 600 675 750 600 300 150 75
310 100110110 465 542.5 620 697.5 775 620 310 155 77.5
320 101000000 400 480 560 640 720 800 640 320 160 80
330 101001010 412.5 495 577.5 660 742.5 660 330 165 82.5
340 101010100 425 510 595 680 765 680 340 170 85
350 101011110 437.5 525 612.5 700 787.5 700 350 175 87.5
360 101101000 450 540 630 720 720 360 180 90
370 101110010 462.5 555 647.5 740 740 370 185 92.5
380 101111100 475 570 665 760 760 380 190 95
390 110000110 487.5 585 682.5 780 780 390 195 97.5
400 110010000 500 600 700 800 800 400 200 100
410 110011010 512.5 615 717.5
420 110100100 525 630 735
430 110101110 537.5 645 752.5
440 110111000 550 660 770
450 111000010 562.5 675 787.5
460 111001100 575 690
470 111010110 587.5 705
480 111100000 600 720
490 111101010 612.5 735
500 111110100 625 750
510 111111110 637.5 765

= 16 MHz and for N =

XTAL

2

4

8

http://onsemi.com

9

NBC12430, NBC12430A

Most of the signals available on the TEST output pin are
useful only for performance verification of the device itself.
However, the PLL bypass mode may be of interest at the
board level for functional debug. When T[2:0] is set to 110,
the device is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers.
The N divider drives the F

differential pair and the M

OUT

counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
F

directly gives the user more control on the test clocks

OUT

sent through the clock tree. Figure 6 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the F

pin can be toggled via

OUT

the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TEST output will not be a 50% duty cycle due to the way the
divider is implemented.

S_CLOCK

S_DATA

T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1

T2 T1 T0 TEST (Pin 20)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

M[8:0]
N[1:0]

P_LOAD

0

SHIFT REGISTER OUT

1

HIGH

0

FREF

1

M COUNTER OUT

0

F
1
0
1

OUT

LOW

PLL BYPASS

F

OUT

M, N

 4

Figure 4. Parallel Interface Timing Diagram

M0

S_LOAD

SCLOCK

SDATA

First

Bit

Figure 5. Serial Interface Timing Diagram

FREF_EXT

MCNT

SHIFT

REG

14−BIT

PLL 12430

M COUNTER

T0
T1
T2

SLOAD

DECODE

VCO_CLK

LATCH

Reset

PLOAD

0
1

SEL_CLK

(1, 2, 4, 8)

FDIV4

MCNT

LOW
F

OUT

MCNT

FREF

HIGH

• T2=T1=1, T0=0: Test Mode

• SCLOCK is selected, MCNT is on TEST output, SCLOCK  N is on F

acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.

PLOAD

N 

OUT

pin.

(VIA ENABLE GATE)

7

TEST

MUX

0

Last

Bit

F

TEST

OUT

Figure 6. Serial Test Clock Block Diagram

http://onsemi.com

10

NBC12430, NBC12430A

APPLICATIONS INFORMATION

Using the On−Board Crystal Oscillator

The NBC12430 and NBC12430A feature a fully
integrated on−board crystal oscillator to minimize system
implementation costs. The oscillator is a series resonant,
multivibrator type design as opposed to the more common
parallel resonant oscillator design. The series resonant
design provides better stability and eliminates the need for
large on chip capacitors. The oscillator is totally self
contained so that the only external component required is the
crystal. As the oscillator is somewhat sensitive to loading on
its inputs, the user is advised to mount the crystal as close to
the device as possible to avoid any board level parasitics. To
facilitate co−location, surface mount crystals are
recommended, but not required. Because the series resonant
design is affected by capacitive loading on the crystal
terminals, loading variation introduced by crystals from
different vendors could be a potential issue. For crystals with
a higher shunt capacitance, it may be required to place a
resistance across the terminals to suppress the third
harmonic. Although typically not required, it is a good idea
to layout the PCB with the provision of adding this external
resistor. The resistor value will typically be between 500 
and 1 K.

The oscillator circuit is a series resonant circuit and thus,
for optimum performance, a series resonant crystal should
be used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the device with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified (a few hundred ppm
translates to kHz inaccuracies). In a general computer
application, this level of inaccuracy is immaterial. Table 6
below specifies the performance requirements of the
crystals to be used with the device.

T able 6. Crystal Specifications

Parameter Value

Crystal Cut Fundamental AT Cut
Resonance Series Resonance*
Frequency Tolerance ±75 ppm at 25°C
Frequency/Temperature Stability ±150 ppm 0 to 70°C
Operating Range 0 to 70°C
Shunt Capacitance 5−7 pF
Equivalent Series Resistance (ESR) 50 to 80 
Correlation Drive Level 100 W
Aging 5 ppm/Yr

(First 3 Years)

* See accompanying text for series versus parallel resonant

discussion.

Power Supply Filtering

The NBC12430 and NBC12430A are mixed
analog/digital product and as such, it exhibits some
sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power
supply pins. The NBC12430 and NBC12430A provide
separate power supplies for the digital circuitry (V

CC

) and
the internal PLL (PLL_VCC) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog phase−locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more d ifficult to minimize noise on
the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply
filter on the PLL_V

pin for the NBC12430 and

CC

NBC12430A .

Figure 7 illustrates a typical power supply filter scheme.
The NBC12430 and NBC12430A are most susceptible to
noise with spectral content in the 1 KHz to 1 MHz range.
Therefore, the filter should be designed to target this range.
The key parameter that needs to be met in the final filter
design is the DC voltage drop that will be seen between the
V

supply and the PLL_VCC pin of the NBC12430 and

CC

NBC12430A . From the data sheet, the PLL_VCC current
(the current sourced through the PLL_VCC pin) is typically
24 mA (30 mA maximum). Assuming that a minimum of

2.8 V must be maintained on the PLL_VCC pin, very little
DC voltage drop can be tolerated when a 3.3 V V

CC

supply
is used. The resistor shown in Figure 7 must have a
resistance of 10−15  to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20 KHz. As the noise frequency crosses the
series resonant point of an individual capacitor, it’s overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL.

3.3 V or

5.0 V

L=1000 H
R=15 

PLL_V

NBC12430

NBC12430A

3.3 V or

5.0 V

R

= 10−15 

S

CC

22 F

0.01 F

V

CC

0.01 F

Figure 7. Power Supply Filter

http://onsemi.com

11

NBC12430, NBC12430A

A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. Figure 7
shows a 1000 H choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_V

pin, a low DC resistance

CC

inductor is required (less than 15 ). Generally, the
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.

The NBC12430 and NBC12430A provide
sub−nanosecond output edge rates and therefore a good
power supply bypassing scheme is a must. Figure 8 shows
a representative board layout for the NBC12430 and
NBC12430A . There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 8 is the low impedance connections
between V

and GND for the bypass capacitors.

CC

Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the device outputs. It is
imperative that low inductance chip capacitors are used. It
is equally important that the board layout not introduce any
of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.

Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on−board oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.

Although the NBC12430 and NBC12430A have several
design features to minimize the susceptibility to power
supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter and bypass schemes
discussed in this section should be adequate to eliminate
power supply noise−related problems in most designs.

Jitter Performance

Jitter is a common parameter associated with clock
generation and distribution. Clock jitter can be defined as the
deviation in a clock’s output transition from its ideal
position.

Cycle−to−Cycle Jitter (short−term) is the period
variation between two adjacent cycles over a defined
number of observed cycles. The number of cycles observed
is application dependent but the JEDEC specification is
1000 cycles.

C1 C1

R1

1

C3

XTAL

Figure 8. PCB Board Layout (PLCC−28)

C2

R1 = 10−15 
C1 = 0.01 F
C2 = 22 F
C3 = 0.1 F

= V

CC

= GND
= Via

T

0

T

JITTER(cycle−cycle)

Figure 9. Cycle−to−Cycle Jitter

T

1

= T1 − T

0

Peak−to−Peak Jitter is the difference between the
highest and lowest acquired value and is represented as the
width of the Gaussian base.

RMS
or one
Sigma

Jitter Amplitude

Time

Figure 10. Peak−to−Peak Jitter

Jitter

Typical
Gaussian
Distribution

Peak−to−Peak Jitter (8 )

http://onsemi.com

12

NBC12430, NBC12430A

There are different ways to measure jitter and often they
are confused with one another. The typical method of
measuring jitter is to look at the timing signal with an
oscilloscope and observe the variations in period−to−period
or cycle−to−cycle. If the scope is set up to trigger on every
rising or falling edge, set to infinite persistence mode and
allowed to trace sufficient cycles, it is possible to determine
the maximum and minimum periods of the timing signal.
Digital scopes can accumulate a large number of cycles,
create a histogram of the edge placements and record
peak−to−peak as well as standard deviations of the jitter.
Care must be taken that the measured edge is the edge
immediately following the trigger edge. These scopes can
also store a finite number of period durations and
post−processing software can analyze the data to find the
maximum and minimum periods.

Recent hardware and software developments have
resulted in advanced jitter measurement techniques. The
Tektronix TDS−series oscilloscopes have superb jitter
analysis capabilities on non−contiguous clocks with their
histogram and statistics capabilities. The Tektronix
TDSJIT2/3 Jitter Analysis software provides many key
timing parameter measurements and will extend that
capability by making jitter measurements on contiguous
clock and data cycles from single−shot acquisitions.

M1 by Amherst was used as well and both test methods
correlated.

This test process can be correlated to earlier test methods
and is more accurate. All of the jitter data reported on the
NBC12430 and NBC12430A was collected in this manner.

Figure 12 shows the jitter as a function of the output
frequency. The graph shows that for output frequencies from
50 to 800 MHz the jitter falls within the 20 ps
peak−to−peak specification. The general trend is that as the
output frequency is increased, the output edge jitter will
decrease.

Figure 11 illustrates the RMS jitter performance of the
NBC12430 and NBC12430A across its specified VCO
frequency range. Note that the jitter is a function of both the
output frequency as well as the VCO frequency. However,
the VCO frequency shows a much stronger dependence. The
data presented has not been compensated for trigger jitter.

Long−Term Period Jitter is the maximum jitter
observed at the end of a period’s edge when compared to the
position of the perfect reference clock’s edge and is specified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
varies by application but the JEDEC spec is 10,000 observed
cycles.

The NBC12430 and NBC12430A exhibit long term and
cycle−to−cycle jitter, which rivals that of SAW based
oscillators. This jitter performance comes with the added
flexibility associated with a synthesizer over a fixed
frequency oscillator. The jitter data presented should
provide users with enough information to determine the
effect on their overall timing budget. The jitter performance
meets the needs of most system designs while adding the
flexibility of frequency margining and field upgrades. These
features are not available with a fixed frequency SAW
oscillator.

25

20

15

10

N = 8

RMS JITTER (ps)

5

N = 1

0

400 500 600 700 800

Figure 11. RMS Jitter vs. VCO Frequency

N = 4

N = 2

VCO FREQUENCY (MHz)

25

20

15

10

RMS JITTER (ps)

5

0

800700600500400300200100

OUTPUT FREQUENCY (MHz)

Figure 12. RMS Jitter vs. Output Frequency

http://onsemi.com

13

S_DATA

S_CLOCK

S_DATA

S_LOAD

NBC12430, NBC12430A

t

t

SETUP

Figure 13. Setup and Hold

t

SETUP

HOLD

t

HOLD

F

F

OUT

OUT

M[8:0]

N[1:0]

P_

LOAD

Figure 14. Setup and Hold

t

t

SETUP

HOLD

Figure 15. Setup and Hold

Pulse Width

t

PERIOD

Figure 16. Output Duty Cycle

http://onsemi.com

14

DCO 

pw

PERIOD

Driver
Device

NBC12430, NBC12430A

F

OUT

F

OUT

D

Receiver
Device

D

50



V

TT

50



V

TT
V

=

CC

− 2.0 V

Figure 17. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 − Termination of ECL Logic Devices.)

ORDERING INFORMATION

Device Package Shipping

NBC12430FA LQFP−32 250 Units / Tray
NBC12430FAG LQFP−32

(Pb−Free)
NBC12430FAR2 LQFP−32 2000 / Tape & Reel
NBC12430FAR2G LQFP−32

(Pb−Free)
NBC12430FN PLCC−28 37 Units / Rail
NBC12430FNG PLCC−28

(Pb−Free)
NBC12430FNR2 PLCC−28 500 / Tape & Reel
NBC12430AFA LQFP−32 250 Units / Tray
NBC12430AFAR2 LQFP−32 2000 / Tape & Reel
NBC12430AFN PLCC−28 37 Units / Rail
NBC12430AFNR2 PLCC−28 500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

250 Units / Tray

2000 / Tape & Reel

37 Units / Rail

†

Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPS I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1642/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices

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15

NBC12430, NBC12430A

PACKAGE DIMENSIONS

PLCC−28

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 776−02

ISSUE E

−L−

−N−

28 1

Z

C

G

G1

S

0.010 (0.250) N

L−M

T

S

L−M

T

M

S

S

L−M

T

S

Y BRK

0.007 (0.180) N

B

0.007 (0.180) N

U

M

D

Z

−M−

W

D

V

0.010 (0.250) N

G1X

S

S

L−M

T

S

VIEW D−D

A

0.007 (0.180) N

0.007 (0.180) N

R

E

M

M

S

L−M

T

L−M

T

S

S

S

H

0.007 (0.180) N

M

S

L−M

T

S

K1

0.004 (0.100)

SEATING

J

−T−

PLANE

VIEW S

S

S

K

VIEW S

0.007 (0.180) N

F

M

S

L−M

T

S

NOTES:

1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS

0.010 (0.250) PER SIDE.

4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).

http://onsemi.com

DIM MIN MAX MIN MAX

A 0.485 0.495 12.32 12.57
B 0.485 0.495 12.32 12.57
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC 1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 −−− 0.51 −−−
K 0.025 −−− 0.64 −−−
R 0.450 0.456 11.43 11.58
U 0.450 0.456 11.43 11.58
V 0.042 0.048 1.07 1.21

W 0.042 0.048 1.07 1.21

X 0.042 0.056 1.07 1.42
Y −−− 0.020 −−− 0.50
Z 2 10 2 10

 

G1 0.410 0.430 10.42 10.92

K1 0.040 −−− 1.02 −−−

16

MILLIMETERSINCHES

NBC12430, NBC12430A

PACKAGE DIMENSIONS

LQFP−32

FA SUFFIX

PLASTIC LQFP PACKAGE

CASE 873A−02

ISSUE A

SEATING

PLANE

9

−T−

B1

−AB−

−AC−

A

A1

32

1

4X

25

−U−

T−U0.20 (0.008) ZAB

P

−T−, −U−, −Z−

AE

VB

AE

DETAIL Y

8

9

−Z−

S1

V1

17

4X

T−U0.20 (0.008) Z

AC

DETAIL Y

BASE

METAL

N

T−U

M

DF

S



M

8X

G

DETAIL AD

E

C

R

J

SECTION AE−AE

0.20 (0.008) ZAC

0.10 (0.004) AC

H

W



Q

K

X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED
AT DATUM PLANE −AB−.

5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −AC−.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.

7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.

http://onsemi.com

17

DETAIL AD

MILLIMETERS

DIMAMIN MAX MIN MAX

7.000 BSC 0.276 BSC

A1 3.500 BSC 0.138 BSC

B 7.000 BSC 0.276 BSC

B1 3.500 BSC 0.138 BSC

C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
G 0.800 BSC 0.031 BSC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028



M 12 REF 12 REF
N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
Q 1 5 1 5



R 0.150 0.250 0.006 0.010
S 9.000 BSC 0.354 BSC

S1 4.500 BSC 0.177 BSC

V 9.000 BSC 0.354 BSC

V1 4.500 BSC 0.177 BSC

W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF

INCHES

0.250 (0.010)

GAUGE PLANE

NBC12430, NBC12430A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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For additional information, please contact your
local Sales Representative.

NBC12430/D

18