Datasheet NBC12429 Datasheet (ON Semiconductor)

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NBC12429

3.3V/5VProgrammable PLL
Synthesized Clock
Generator

25 MHz to 400 MHz

The NBC12429 is a general purpose, PLL based synthesized clock
source. The VCO will operate over a frequency range of 200 MHz to
400 MHz. The VCO frequency is sent to the N-output divider, where
it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO
and output frequency can be programmed using the parallel or serial
interfaces to the configuration logic. Output frequency steps of

1.0 MHz can be achieved using a 16 MHz crystal, depending on the
output dividers. The PLL loop filter is fully integrated and does not
require any external components.

• Best-in-Class Output Jitter Performance, ±20 ps Peak-to-Peak

• 25 MHz to 400 MHz Programmable Differential PECL Outputs

• Fully Integrated Phase-Lock-Loop with Internal Loop Filter

• Parallel Interface for Programming Counter and Output Dividers

During Power-Up

• Minimal Frequency Overshoot

• Serial 3-Wire Programming Interface

• Crystal Oscillator Interface

• Operating Range: V

• CMOS and TTL Compatible Control Inputs

• Drop-in Replacement for Motorola MC12429

= 3.135 V to 5.25 V

CC

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PLCC-28

FN SUFFIX

CASE 776

LQFP-32

FA SUFFIX

CASE 873A

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

MARKING

DIAGRAMS

128

NBC12429

AWLYYWW

NBC12429

AWLYYWW

32

1

 Semiconductor Components Industries, LLC, 2003

January, 2003 - Rev. 2

ORDERING INFORMATION

Device Package Shipping

NBC12429FN PLCC-28 37 Units/Rail
NBC12429FNR2 PLCC-28

NBC12429FA LQFP-32 250 Units/Tray
NBC12429FAR2 LQFP-32 2000 Tape & Reel

1 Publication Order Number:

500 Tape & Reel

NBC12429/D

10-20 MHz

OE

NBC12429

+3.3 or 5.0 V

1

PLL_V

 N

CC

+3.3 or 5.0 V

V

21, 25

CC

24
23

20

F

OUT

F

OUT

TEST

1 MHz

F

 16

REF

4

XTAL1

OSC

5

XTAL2

PHASE

DETECTOR

9-BIT  M
COUNTER

VCO

200-400

MHz

(1, 2, 4, 8)

6

LATCH

LATCH

S_LOAD
P_LOAD

S_DATA

S_CLOCK

S_CLOCK

S_DATA

S_LOAD

PLL_V

CC

NC

NC

XTAL1

28

7

27

9- BIT SR

26

Figure 1. NBC12429 Block Diagram (28-Lead PLCC)

VCCFOUT

25 24 23 22 21 20 19

26

27

28

1

2

3

4

56 7891011

FOUT

GND

CC

V

01

8 → 16

9

M[8:0]

GND

TEST

18

N[1]

17

N[0]

16

M[8]

15

M[7]

14

M[6]

13

M[5]

12

M[4]

LATCH

01

2- BIT SR 3- BIT SR

17, 18 22, 19

2

N[1:0]

CC

OUTFOUT

F

V

32 31 30 29 28 27 26 25

S_CLOCK

S_DATA

S_LOAD

PLL_V

CC

PLL_V

CC

N/C
N/C

XTAL1

1
2
3
4
5
6
7
8

910111213141516

GND

VCCV

CC

TEST

GND

24
23
22
21
20
19
18
17

N/C
N[1]

N[0]
M[8]
M[7]
M[6]
M[5]
M[4]

OE

XTAL2

M[0]

P_LOAD

M[1]

M[2]

Figure 2. 28-Lead PLCC (Top View)

M[3]

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2

XTAL2

OE

M[0]

P_LOAD

M[1]

M[2]

M[3]

N/C

Figure 3. 32-Lead LQFP (Top View)

NBC12429

The following gives a brief description of the functionality of the NBC12429 Inputs and Outputs. Unless explicitly stated,
all inputs are CMOS/TTL compatible with either pull-up or pulldown resistors. The PECL outputs are capable of driving two
series terminated 50  transmission lines on the incident edge.

PIN FUNCTION DESCRIPTION

Pin Name Function Description

INPUTS

XTAL1, XTAL2

S_LOAD* CMOS/TTL Serial Latch Input

S_DATA* CMOS/TTL Serial Data Input

S_CLOCK* CMOS/TTL Serial Clock Input

P_LOAD** CMOS/TTL Parallel Latch Input

M[8:0]** CMOS/TTL PLL Loop Divider

N[1:0]** CMOS/TTL Output Divider Inputs

OE** CMOS/TTL Output Enable Input

OUTPUTS

F

, F

OUT

OUT

TEST CMOS/TTL Output The function of this output is determined by the serial configuration bits T[2:0].

POWER

V

CC

PLL_V

CC

GND Negative Power Supply These pins are the negative supply for the chip and are normally all connected to

* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.

Crystal Inputs These pins form an oscillator when connected to an external series-resonant

(Internal Pulldown Resistor)

(Internal Pulldown Resistor)

(Internal Pulldown Resistor)

(Internal Pullup Resistor)

Inputs (Internal Pullup Resistor)

(Internal Pullup Resistor)

(Internal Pullup Resistor)

PECL Differential Outputs These differential, positive-referenced ECL signals (PECL) are the outputs of the

Positive Supply for the Logic The positive supply for the internal logic and output buffer of the chip, and is con-

Positive Supply for the PLL This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.

crystal.
This pin loads the configuration latches with the contents of the shift registers. The

latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH-to-LOW transition of S_LOAD for proper operation.

This pin acts as the data input to the serial configuration shift registers.

This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.

This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW-to-HIGH transition of P_LOAD
tion.

These pins are used to configure the PLL loop divider. They are sampled on the
LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.

These pins are used to configure the output divider modulus. They are sampled
on the LOW-to-HIGH transition of P_LOAD

Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the FOUT output.

synthesizer.

nected to +3.3 V or +5.0 V.

ground.

.

for proper opera-

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3

NBC12429

ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 k
Internal Input Pullup Resistor 37.5 k
ESD Protection Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity (Note 1) PLCC

Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in
Transistor Count 2035
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

MAXIMUM RATINGS (Note 2)

Symbol

V

CC

V

I

I

out

Positive Supply GND = 0 V - 6 V
Input Voltage GND = 0 V VI  V
Output Current Continuous

TA Operating Temperature Range - - 0 to +70 °C
T

stg



JA



JC



JA



JC

T

sol

Storage Temperature Range - - -65 to +150 °C
Thermal Resistance (Junction-to-Ambient) 0 LFPM

Thermal Resistance (Junction-to-Case) std bd 28 PLCC 22 to 26 °C/W
Thermal Resistance (Junction-to-Ambient) 0 LFPM

Thermal Resistance (Junction-to-Case) std bd 32 LQFP 12 to 17 °C/W
Wave Solder < 2 to 3 sec @ 248°C - 265 °C

2. Maximum Ratings are those values beyond which device damage may occur.

Parameter Condition 1 Condition 2 Rating Unit

CC

-

Surge

-

28 PLCC

500 LFPM

28 PLCC

32 LQFP

500 LFPM

32 LQFP

LQFP

> 2 kV

> 150 V

> 1 kV

Level 1
Level 2

6 V

50

100

63.5

43.5

80
55

mA
mA

°C/W
°C/W

°C/W
°C/W

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NBC12429

DC CHARACTERISTICS (V

= 3.3 V ± 5%)

CC

Symbol Characteristic Condition

V

IH

LVCMOS/

Input HIGH Voltage VCC = 3.3 V 2.0 - - 2.0 - - 2.0 - - V

LVTTL
V

IL

LVCMOS/

Input LOW Voltage VCC = 3.3 V - - 0.8 - - 0.8 - - 0.8 V

LVTTL
I

IN

V

V

V
PECL

V
PECL

I

CC

3. F

4. F

OH

OL

OH

OL

OUT/FOUT
OUT/FOUT

Input Current - - 1.0 - - 1.0 - - 1.0 mA
Output HIGH Voltage

IOH = -0.8 mA 2.5 - - 2.5 - - 2.5 - - V

TEST

Output LOW Voltage

IOL = 0.8 mA - - 0.4 - - 0.4 - - 0.4 V

TEST

Output HIGH Voltage F

Output LOW Voltage F

Power Supply Current V

PLL_V

F

F

OUT
OUT

OUT
OUT

VCC = 3.3 V
(Notes 3, 4)

VCC = 3.3 V
(Notes 3, 4)

CC
CC

output levels will vary 1:1 with VCC variation.
outputs are terminated through a 50  resistor to VCC - 2.0 V.

0°C 25°C 70°C

Min Typ Max Min Typ Max Min Typ Max

Unit

2.155 - 2.405 2.155 - 2.405 2.155 - 2.405 V

1.355 - 1.605 1.355 - 1.605 1.355 - 1.605 V

481856227026481858227026481861227026mA

mA

DC CHARACTERISTICS (V

= 5.0 V ± 5%)

CC

Symbol Characteristic Condition

V

IH

CMOS/

Input HIGH Voltage VCC = 5.0 V 2.0 - - 2.0 - - 2.0 - - V

TTL
V

IL

CMOS/

Input LOW Voltage VCC = 5.0 V - - 0.8 - - 0.8 - - 0.8 V

TTL
I

IN

V
V
V

PECL
V

PECL
I

CC

5. F

6. F

OH
OL
OH

OL

Input Current - - 1.0 - - 1.0 - - 1.0 mA
Output HIGH Voltage TEST IOH = -0.8 mA 2.5 - - 2.5 - - 2.5 - - V
Output LOW Voltage TEST IOL = 0.8 mA - - 0.4 - - 0.4 - - 0.4 V
Output HIGH Voltage F

Output LOW Voltage F

Power Supply Current V

OUT/FOUT
OUT/FOUT

output levels will vary 1:1 with VCC variation.
outputs are terminated through a 50  resistor to VCC - 2.0 volts.

PLL_V

F

F

OUT
OUT

OUT
OUT

VCC = 5.0 V
(Notes 5, 6)

VCC = 5.0 V
(Notes 5, 6)

CC
CC

0°C 25°C 70°C

Min Typ Max Min Typ Max Min Typ Max

Unit

3.855 - 4.105 3.855 - 4.105 3.855 - 4.105 V

3.055 - 3.305 3.055 - 3.305 3.055 - 3.305 V

501958237527501960237527501965237527mA

mA

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5

NBC12429

AC CHARACTERISTICS (V

Symbol

F

MAXI

F

MAXO

t

LOCK

t

jitter

t

s

t

h

t

pwMIN

Maximum Input Frequency S_CLOCK

Maximum Output Frequency VCO (Internal)

Maximum PLL Lock Time - 10 ms
Cycle-to-Cycle Jitter (1 ) See Applications Section - 20 ps
Setup Time S_DATA to S_CLOCK

Hold Time S_DATA to S_CLOCK

Minimum Pulse Width S_LOAD

= 3.125 V to 5.25 V ± 5%; TA = 0° to 70°C) (Note 8)

CC

Characteristic Condition Min Max Unit

Xtal Oscillator

F

OUT

S_CLOCK to S_LOAD

M, N to P_LOAD

M, N to P_LOAD

P_LOAD

(Note 7) -

10

200

25

20
20
20

20
20

50
50

10
20

400
400

-

-

-

-

-

-

-

MHz

MHz

ns

ns

ns

DCO Output Duty Cycle 47.5 52.5 %
tr, t

f

Output Rise/Fall F

20%-80% 175 425 ps

OUT

7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as

a test clock in TEST_MODE 6.

8. F

OUT/FOUT

outputs are terminated through a 50  resistor to VCC - 2.0 V.

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6

NBC12429

FUNCTIONAL DESCRIPTION

The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the
reference oscillator is divided by 16 before being sent to the
phase detector. With a 16 MHz crystal, this provides a
reference frequency of 1 MHz. Although this data sheet
illustrates functionality only for a 16 MHz crystal, Table 1,
any crystal in the 10-20 MHz range can be used, Table 3.

The VCO within the PLL operates over a range of 200 to
400 MHz. Its output is scaled by a divider that is configured
by either the serial or parallel interfaces. The output of this
loop divider is also applied to the phase detector.

The phase detector and the loop filter force the VCO
output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve loop lock.

The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. This
output divider (N divider) is configured through either the
serial or the parallel interfaces and can provide one of four
division ratios (1, 2, 4, or 8). This divider extends the
performance of the part while providing a 50% duty cycle.

The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission lines
terminated into 50  to V

-2.0 V. The positive reference

CC

for the output driver and the internal logic is separated from
the power supply for the phase-locked loop to minimize
noise induced jitter.

The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the M[8:0]
and N[1:0] inputs to configure the internal counters.
Normally upon system reset, the P_LOAD

input is held
LOW until sometime after power becomes valid. On the
LOW-to-HIGH transition of P_LOAD

, the parallel inputs
are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the
M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.

The serial interface logic is implemented with a fourteen
bit shift register scheme. The register shifts once per rising
edge of the S_CLOCK input. The serial input S_DATA must
meet setup and hold timing as specified in the AC
Characteristics section of this document. With P_LOAD
held high, the configuration latches will capture the value of
the shift register on the HIGH-to-LOW edge of the
S_LOAD input. See the programming section for more
information.

The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream. See
the programming section for more information.

Table 1. Programming VCO Frequency Function Table

VCO

Frequency

(MHz)

200
201
202
203

•

•

•

397
398
399
400

*With 16 MHz crystal.

M Count*

200
201
202
203

•

•

•

397
398
399
400

256

M8

0
0
0
0

•

•

•

1
1
1
1

128

M7

64

M6

1
1
1
1

•

•

•

1
1
1
1

32
M5

1
1
1
1

•

•

•

0
0
0
0

0
0
0
0

•

•

•

0
0
0
0

16

M4

8

M3

0
0
0
0

•

•

•

0
0
0
1

1
1
1
1

•

•

•

1
1
1
0

M2

4

0
0
0
0

•

•

•

1
1
1
0

M1

2

0
0
1
1

•

•

•

0
1
1
0

1

M0

0
1
0
1

•

•

•

1
0
1
0

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7

NBC12429

Á

Á

ÁÁÁÁ

Á

Á

Á

Á
ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

PROGRAMMING INTERFACE

Programming the NBC12429 is accomplished by
properly configuring the internal dividers to produce the
desired frequency at the outputs. The output frequency can
by represented by this formula:

(eq. 1)

where F

FOUT  (F

is the crystal frequency, M is the loop divider

XTAL

 16)  M N

XTAL

modulus, and N is the output divider modulus. Note that it
is possible to select values of M such that the PLL is unable
to achieve loop lock. To avoid this, always make sure that M
is selected to be 200 ≤ M ≤ 400 for a 16 MHz input reference.

Assuming that a 16 MHz reference frequency is used the
above equation reduces to:

FOUT  M  N

(eq. 2)

Substituting the four values for N (1, 2, 4, 8) yields:

Table 2. Programmable Output Divider Function Table

Output Frequency

N1

N0

Á

0
1
0
1

N Divider

ÁÁ

1
2
4
8

Á

0

0

1

1
*For crystal frequency of 16 MHz.

F

ÁÁ

M  2
M  4
M  8

OUT

M

Range (MHz)*

БББББ

200-400
100-200

50-100

25-50

The user can identify the proper M and N values for the
desired frequency from the above equations. The four output
frequency ranges established by N are 200-400 MHz,
100-200 MHz, 50-100 MHz and 25-50 MHz, respectively.
From these ranges, the user will establish the value of N
required. The value of M can then be calculated based on
equation 1. For example, if an output frequency of 131 MHz
was desired, the following steps would be taken to identify
the appropriate M and N values. 131 MHz falls within the
frequency range set by an N value of 2; thus, N [1:0] = 01.
For N = 2, F

= M ÷ 2 and M = 2 x F

OUT

. Therefore,

OUT

M = 131 x 2 = 262, so M[8:0] = 100000110. Following this
same procedure, a user can generate any whole frequency
desired between 25 and 400 MHz. Note that for N > 2,
fractional values of F

can be realized. The size of the

OUT

programmable frequency steps (and thus, the indicator of
the fractional output frequencies achievable) will be equal
to F

XTAL

÷ 16 ÷ N.

For input reference frequencies other than 16 MHz, see
Table 3, which shows the usable VCO frequency and M
divider range.

The input frequency and the selection of the feedback
divider M is limited by the VCO frequency range and
F

. M must be configured to match the VCO frequency

XTAL

range of 200 to 400 MHz in order to achieve stable PLL
operation.

M
M

min
max

 f

 f

VCOmin

VCOmax

 (f

 (f

XTAL

XTAL

 16) and

 16)

(eq. 3)
(eq. 4)

The value for M falls within the constraints set for PLL
stability . If the value for M fell outside of the valid range, a
different N value would be selected to move M in the
appropriate direction.

The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is
controlled via the P_LOAD

signal such that a LOW to HIGH
transition will latch the information present on the M[8:0]
and N[1:0] inputs into the M and N counters. When the
P_LOAD

signal is LOW, the input latches will be
transparent and any changes on the M[8:0] and N[1:0] inputs
will affect the F

output pair. To use the serial port, the

OUT

S_CLOCK signal samples the information on the S_DATA
line and loads it into a 14 bit shift register. Note that the
P_LOAD

signal must be HIGH for the serial load operation
to function. The Test register is loaded with the first three
bits, the N register with the next two, and the M register with
the final nine bits of the data stream on the S_DATA input.
For each register, the most significant bit is loaded first (T2,
N1, and M8). A pulse on the S_LOAD pin after the shift
register is fully loaded will transfer the divide values into the
counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters.
Figures 4 and 5 illustrate the timing diagram for both a
parallel and a serial load of the NBC12429 synthesizer.

M[8:0] and N[1:0] are normally specified once at
power-up through the parallel interface, and then possibly
again through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine-tune the clock as the ability to control the serial
interface becomes available.

The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. The T2, T1, and T0 control bits are preset
to ‘000’ when P_LOAD

is LOW so that the PECL F

OUT

outputs are as jitter-free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter
of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin.

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8

NBC12429

Á

Á

Table 3. NBC12429 Frequency Operating Range

Output Frequency for F

ББББББББББББББББББББББ

M

VCO Frequency Range for a Crystal Frequency of:

M[8:0]

10

12

14

16

18

20

ББББББББ

16 MHz and for N =

1

2

160 010100000 200
170 010101010 212.5
180 010110100 202.5 225
190 010111110 213.75 237.5
200 011001000 200 225 250 200 100 50 25
210 011010010 210 236.25 262.5 210 105 52.5 26.25
220 011011100 220 247.5 275 220 110 55 27.5
230 011100110 201.25 230 258.75 287.5 230 115 57.5 28.75
240 011110000 210 240 270 300 240 120 60 30
250 011111010 218.75 250 281.25 312.5 250 125 62.5 31.25
260 100000100 227.5 260 292.5 325 260 130 65 32.5
270 100001110 202.5 236.25 270 303.75 337.5 270 135 67.5 33.75
280 100011000 210 245 280 315 350 280 140 70 35
290 100100010 217.5 253.75 290 326.25 362.5 290 145 72.5 36.25
300 100101100 225 262.5 300 337.5 375 300 150 75 37.5
310 100110110 232.5 271.25 310 348.75 387.5 310 155 77.5 38.75
320 101000000 200 240 280 320 360 400 320 160 80 40
330 101001010 206.25 247.5 288.75 330 371.25 330 165 82.5 41.25
340 101010100 212.5 255 297.5 340 382.5 340 170 85 42.5
350 101011110 218.75 262.5 306.25 350 393.75 350 175 87.5 43.75
360 101101000 225 270 315 360 360 180 90 45
370 101110010 231.25 277.5 323.75 370 370 185 92.5 46.25
380 101111100 237.5 285 332.5 380 380 190 95 47.5
390 110000110 243.75 292.5 341.25 390 390 195 97.5 48.75
400 110010000 250 300 350 400 400 200 100 50
410 110011010 256.25 307.5 358.75
420 110100100 262.5 315 367.5
430 110101110 268.75 322.5 376.25
440 110111000 275 330 385
450 111000010 281.25 337.5 393.75
460 111001100 287.5 345
470 111010110 293.75 352.5
480 111100000 300 360
490 111101010 306.25 367.5
500 111110100 312.5 375
510 111111110 318.75 382.5

XTAL

4

=

8

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9

NBC12429

Most of the signals available on the TEST output pin are
useful only for performance verification of the NBC12429
itself. However, the PLL bypass mode may be of interest at
the board level for functional debug. When T[2:0] is set to
110, the NBC12429 is placed in PLL bypass mode. In this
mode the S_CLOCK input is fed directly into the M and N
dividers. The N divider drives the F

differential pair and

OUT

the M counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
F

directly gives the user more control on the test clocks

OUT

sent through the clock tree. Figure 6 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the F

pin can be toggled via

OUT

the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TEST output will not be a 50% duty cycle due to the way the
divider is implemented.

S_CLOCK

S_DATA

T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1

T2 T1 T0 TEST (Pin 20)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

M[8:0]
N[1:0]

P_LOAD

0

SHIFT REGISTER OUT

1

HIGH

0

F
1
0
1
0
1

REF

M COUNTER OUT

F

OUT

LOW

PLL BYPASS

F

OUT

M, N

 4

Figure 4. Parallel Interface Timing Diagram

M0

S_LOAD

SCLOCK

First

Bit

Figure 5. Serial Interface Timing Diagram

SDATA

FREF

MCNT

SHIFT

REG

14- BIT

PLL 12429

M COUNTER

T0
T1
T2

SLOAD

DECODE

VCO_CLK

LATCH

Reset

PLOAD

0
1

SEL_CLK

N 

(1, 2, 4, 8)

FDIV4
MCNT

LOW

FOUT

MCNT

FREF

HIGH

• T2=T1=1, T0=0: Test Mode

• SCLOCK is selected, MCNT is on TEST output, SCLOCK  N is on FOUT pin.

acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.

PLOAD

(VIA ENABLE GATE)

7

TEST

MUX

0

Last

Bit

FOUT

TEST

Figure 6. Serial Test Clock Block Diagram

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10

NBC12429

APPLICATIONS INFORMATION

Using the On-Board Crystal Oscillator

The NBC12429 features a fully integrated on-board
crystal oscillator to minimize system implementation costs.
The oscillator is a series resonant, multivibrator type design
as opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs, the user is
advised to mount the crystal as close to the NBC12429 as
possible to avoid any board level parasitics. To facilitate
co-location, surface mount crystals are recommended, but
not required. Because the series resonant design is affected
by capacitive loading on the crystal terminals, loading
variation introduced by crystals from different vendors
could be a potential issue. For crystals with a higher shunt
capacitance, it may be required to place a resistance across
the terminals to suppress the third harmonic. Although
typically not required, it is a good idea to layout the PCB
with the provision of adding this external resistor. The
resistor value will typically be between 500 and 1 K.

The oscillator circuit is a series resonant circuit and thus,
for optimum performance, a series resonant crystal should
be used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the NBC12429 with only a minor error in the
desired frequency. A parallel resonant mode crystal used in
a series resonant circuit will exhibit a frequency of
oscillation a few hundred ppm lower than specified (a few
hundred ppm translates to kHz inaccuracies). In a general
computer application, this level of inaccuracy is immaterial.
Table 4 below specifies the performance requirements of the
crystals to be used with the NBC12429.

T able 4. Crystal Specifications

Parameter Value

Crystal Cut Fundamental AT Cut
Resonance Series Resonance*
Frequency Tolerance ±75 ppm at 25°C
Frequency/Temperature Stability ±150 ppm 0 to 70°C
Operating Range 0 to 70°C
Shunt Capacitance 5-7 pF
Equivalent Series Resistance (ESR) 50 to 80 
Correlation Drive Level 100 W
Aging 5 ppm/Yr

(First 3 Years)

* See accompanying text for series versus parallel resonant

discussion.

Power Supply Filtering

The NBC12429 is a mixed analog/digital product and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NBC12429 provides
separate power supplies for the digital circuitry (V

CC

) and
the internal PLL (PLL_VCC) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog phase-locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more d ifficult to minimize noise on
the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply
filter on the PLL_V

pin for the NBC12429.

CC

Figure 7 illustrates a typical power supply filter scheme.
The NBC12429 is most susceptible to noise with spectral
content in the 1 KHz to 1 MHz range. Therefore, the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the V

supply and the

CC

PLL_VCC pin of the NBC12429. From the data sheet, the
PLL_VCC current (the current sourced through the
PLL_V

pin) is typically 23 mA (27 mA maximum).

CC

Assuming that a minimum of 2.8 V must be maintained on
the PLL_VCC pin, very little DC voltage drop can be
tolerated when a 3.3 V VCC supply is used. The resistor
shown in Figure 7 must have a resistance of 10-15  to meet
the voltage drop criteria. The RC filter pictured will provide
a broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor, it’s overall impedance begins to look inductive
and thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.

3.3 V or

5.0 V

L=1000 H
R=15 

PLL_V

NBC12429

3.3 V or

5.0 V

R

= 10-15 

S

CC

22 F

0.01 F

V

CC

0.01 F

Figure 7. Power Supply Filter

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11

NBC12429

A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. Figure 7
shows a 1000 H choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_V

pin, a low DC resistance

CC

inductor is required (less than 15). Generally, the
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.

The NBC12429 provides sub-nanosecond output edge
rates and therefore a good power supply bypassing scheme
is a must. Figure 8 shows a representative board layout for
the NBC12429. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 8 is the low impedance connections

C1 C1

R1

1

C3

C2

between V

and GND for the bypass capacitors.

CC

Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the NBC12429 outputs.
It is imperative that low inductance chip capacitors are used.
It is equally important that the board layout not introduce
any of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.

R1 = 10-15 
C1 = 0.01 F
C2 = 22 F
C3 = 0.1 F

Xtal

Figure 8. PCB Board Layout for NBC12429 (28 PLCC)

Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on-board oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.

= V

CC

= GND
= Via

Although the NBC12429 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL), there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise-related
problems in most designs.

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12

NBC12429

Jitter Performance of the NBC12429

Jitter is a common parameter associated with clock
generation and distribution. Clock jitter can be defined as the
deviation in a clock’s output transition from its ideal
position.

Cycle-to-Cycle Jitter (short-term) is the period
variation between two adjacent cycles over a defined
number of observed cycles. The number of cycles observed
is application dependent but the JEDEC specification is
1000 cycles.

T

0

T

JITTER(cycle-cycle)

Figure 9. Cycle-to-Cycle Jitter

T

1

= T1 - T

0

Peak-to-Peak Jitter is the difference between the
highest and lowest acquired value and is represented as the
width of the Gaussian base.

RMS
or one
Sigma

Jitter Amplitude

Time

Figure 10. Peak-to-Peak Jitter

Jitter

Typical
Gaussian
Distribution

There are different ways to measure jitter and often they
are confused with one another. The typical method of
measuring jitter is to look at the timing signal with an
oscilloscope and observe the variations in period-to-period
or cycle-to-cycle. If the scope is set up to trigger on every
rising or falling edge, set to infinite persistence mode and
allowed to trace sufficient cycles, it is possible to determine
the maximum and minimum periods of the timing signal.
Digital scopes can accumulate a large number of cycles,
create a histogram of the edge placements and record
peak-to-peak as well as standard deviations of the jitter.

Care must be taken that the measured edge is the edge
immediately following the trigger edge. These scopes can
also store a finite number of period durations and
post-processing software can analyze the data to find the
maximum and minimum periods.

Recent hardware and software developments have
resulted in advanced jitter measurement techniques. The
Tektronix TDS-series oscilloscopes have superb jitter
analysis capabilities on non-contiguous clocks with their
histogram and statistics capabilities. The Tektronix
TDSJIT2/3 Jitter Analysis software provides many key
timing parameter measurements and will extend that
capability by making jitter measurements on contiguous
clock and data cycles from single-shot acquisitions.

M1 by Amherst was used as well and both test methods
correlated.

This test process can be correlated to earlier test methods
and is more accurate. All of the jitter data reported on the
NBC12429 was collected in this manner. Figure 11 shows
the jitter as a function of the output frequency. The graph
shows that for output frequencies from 25 to 400 MHz the
jitter falls within the 20 ps peak-to-peak specification.
The general trend is that as the output frequency is increased,
the output edge jitter will decrease.

Figure 12 illustrates the RMS jitter performance of the
NBC12429 across its specified VCO frequency range. Note
that the jitter is a function of both the output frequency as
well as the VCO frequency. However, the VCO frequency
shows a much stronger dependence. The data presented has
not been compensated for trigger jitter.

Long-Term Period Jitter is the maximum jitter
observed at the end of a period’s edge when compared to the

Peak-to-Peak Jitter (6 sigma)

position of the perfect reference clock’s edge and is specified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
varies by application but the JEDEC spec is 10,000 observed
cycles.

The NBC12429 exhibits long term and cycle-to-cycle
jitter, which rivals that of SAW based oscillators. This jitter
performance comes with the added flexibility associated
with a synthesizer over a fixed frequency oscillator. The
jitter data presented should provide users with enough
information to determine the effect on their overall timing
budget. The jitter performance meets the needs of most
system designs while adding the flexibility of frequency
margining and field upgrades. These features are not
available with a fixed frequency SAW oscillator.

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13

NBC12429

25

20

15

10

N = 8

RMS JITTER (ps)

5

N = 1

0

200 250 300 350 400

N = 4

N = 2

VCO FREQUENCY (MHz)

Figure 11. RMS Jitter vs. VCO Frequency

25

20

15

10

RMS JITTER (ps)

5

0

40035030025020015010050

OUTPUT FREQUENCY (MHz)

Figure 12. RMS Jitter vs. Output Frequency

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14

S_DATA

S_CLOCK

S_DATA

S_LOAD

NBC12429

t

t

SET- UP

Figure 13. Set-Up and Hold

t

SET- UP

HOLD

t

HOLD

F

F

OUT

OUT

M[8:0]

N[1:0]

P_

LOAD

Figure 14. Set-Up and Hold

t

t

SET- UP

HOLD

Figure 15. Set-Up and Hold

Pulse Width

t

PERIOD

Figure 16. Output Duty Cycle

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15

DCO





pw



PERIOD

Driver
Device

F

F

OUT

OUT

NBC12429

D

Receiver
Device

D

50



V

TT

50



V

TT
V

=

CC

- 2.0 V

Figure 17. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 - Termination of ECL Logic Devices.)

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16

NBC12429

PACKAGE DIMENSIONS

PLCC-28

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 776-02

ISSUE E

-L-

-N-

28 1

Z

C

G

G1

S

0.010 (0.250) N

L−M

T

S

L−M

T

M

S

S

L−M

T

S

Y BRK

0.007 (0.180) N

B

0.007 (0.180) N

U

M

D

Z

-M-

W

D

V

0.010 (0.250) N

G1X

S

S

L−M

T

S

VIEW D-D

A

0.007 (0.180) N

0.007 (0.180) N

R

E

M

M

S

L−M

T

L−M

T

S

S

S

H

0.007 (0.180) N

M

S

L−M

T

S

K1

0.004 (0.100)

SEATING

J

-T-

PLANE

VIEW S

S

S

K

VIEW S

0.007 (0.180) N

F

M

S

L−M

T

S

NOTES:

1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS

0.010 (0.250) PER SIDE.

4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).

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DIM MIN MAX MIN MAX

A 0.485 0.495 12.32 12.57
B 0.485 0.495 12.32 12.57
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC 1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 −−− 0.51 −−−
K 0.025 −−− 0.64 −−−
R 0.450 0.456 11.43 11.58
U 0.450 0.456 11.43 11.58
V 0.042 0.048 1.07 1.21

W 0.042 0.048 1.07 1.21

X 0.042 0.056 1.07 1.42
Y −−− 0.020 −−− 0.50
Z 2 10 2 10

 

G1 0.410 0.430 10.42 10.92

K1 0.040 −−− 1.02 −−−

17

MILLIMETERSINCHES

NBC12429

PACKAGE DIMENSIONS

LQFP-32

FA SUFFIX

PLASTIC LQFP PACKAGE

CASE 873A-02

ISSUE A

SEATING

PLANE

9

B1

-AB-

-AC-

-T-

A

A1

32

1

4X

25

-U-

T−U0.20 (0.008) ZAB

P

-T-, -U-, -Z-

AE

VB

AE

DETAIL Y

8

9

-Z-

S1

V1

17

4X

T−U0.20 (0.008) Z

AC

DETAIL Y

BASE

METAL

N

T−U

M

DF

S



M

8X

G

DETAIL AD

E

C

R

J

SECTION AE-AE

0.20 (0.008) ZAC

0.10 (0.004) AC

H

W



Q

K

X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED
AT DATUM PLANE −AB−.

5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −AC−.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.

7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.

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18

DETAIL AD

MILLIMETERS

DIMAMIN MAX MIN MAX

7.000 BSC 0.276 BSC

A1 3.500 BSC 0.138 BSC

B 7.000 BSC 0.276 BSC

B1 3.500 BSC 0.138 BSC

C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
G 0.800 BSC 0.031 BSC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028



M 12 REF 12 REF
N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
Q 1 5 1 5

 

R 0.150 0.250 0.006 0.010
S 9.000 BSC 0.354 BSC

S1 4.500 BSC 0.177 BSC

V 9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
W 0.200 REF 0.008 REF

X 1.000 REF 0.039 REF

INCHES

0.250 (0.010)

GAUGE PLANE

Notes

NBC12429

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19

NBC12429

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make

changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

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P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800-344-3860 Toll Free USA/Canada
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JAPAN: ON Semiconductor, Japan Customer Focus Center

2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

NBC12429/D

20