ON Semiconductor NBC12429 Technical data

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NBC12429

3.3V/5VProgrammable PLL Synthesized Clock Generator

25 MHz to 400 MHz

The NBC12429 is a general purpose, PLL based synthesized clock source. The VCO will operate over a frequency range of 200 MHz to 400 MHz. The VCO frequency is sent to the N-output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of

1.0 MHz can be achieved using a 16 MHz crystal, depending on the output dividers. The PLL loop filter is fully integrated and does not require any external components.

• Best-in-Class Output Jitter Performance, ±20 ps Peak-to-Peak

• 25 MHz to 400 MHz Programmable Differential PECL Outputs

• Fully Integrated Phase-Lock-Loop with Internal Loop Filter

• Parallel Interface for Programming Counter and Output Dividers

During Power-Up

• Minimal Frequency Overshoot

• Serial 3-Wire Programming Interface

• Crystal Oscillator Interface

• Operating Range: V

• CMOS and TTL Compatible Control Inputs

• Drop-in Replacement for Motorola MC12429

= 3.135 V to 5.25 V

CC

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PLCC-28

FN SUFFIX

CASE 776

LQFP-32

FA SUFFIX

CASE 873A

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

MARKING

DIAGRAMS

128

NBC12429

AWLYYWW

NBC12429

AWLYYWW

32

1

 Semiconductor Components Industries, LLC, 2003

January, 2003 - Rev. 2

ORDERING INFORMATION

Device Package Shipping

NBC12429FN PLCC-28 37 Units/Rail NBC12429FNR2 PLCC-28

NBC12429FA LQFP-32 250 Units/Tray NBC12429FAR2 LQFP-32 2000 Tape & Reel

1 Publication Order Number:

500 Tape & Reel

NBC12429/D

10-20 MHz

OE

NBC12429

+3.3 or 5.0 V

1

PLL_V

 N

CC

+3.3 or 5.0 V

V

21, 25

CC

24 23

20

F

OUT

F

OUT

TEST

1 MHz

F

 16

REF

4

XTAL1

OSC

5

XTAL2

PHASE

DETECTOR

9-BIT  M COUNTER

VCO

200-400

MHz

(1, 2, 4, 8)

6

LATCH

S_LOAD P_LOAD

S_DATA

S_CLOCK

S_DATA

S_LOAD

PLL_V

CC

NC

XTAL1

28

7

27

9- BIT SR

26

Figure 1. NBC12429 Block Diagram (28-Lead PLCC)

VCCFOUT

25 24 23 22 21 20 19

26

27

28

1

2

3

4

56 7891011

FOUT

GND

CC

V

01

8 → 16

9

M[8:0]

GND

TEST

18

N[1]

17

N[0]

16

M[8]

15

M[7]

14

M[6]

13

M[5]

12

M[4]

LATCH

01

2- BIT SR 3- BIT SR

17, 18 22, 19

2

N[1:0]

CC

OUTFOUT

F

V

32 31 30 29 28 27 26 25

S_CLOCK

S_DATA

S_LOAD

PLL_V

CC

PLL_V

CC

N/C N/C

XTAL1

1 2 3 4 5 6 7 8

910111213141516

GND

VCCV

CC

TEST

GND

24 23 22 21 20 19 18 17

N/C N[1]

N[0] M[8] M[7] M[6] M[5] M[4]

OE

XTAL2

M[0]

P_LOAD

M[1]

M[2]

Figure 2. 28-Lead PLCC (Top View)

M[3]

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2

XTAL2

OE

M[0]

P_LOAD

M[1]

M[2]

M[3]

N/C

Figure 3. 32-Lead LQFP (Top View)

NBC12429

The following gives a brief description of the functionality of the NBC12429 Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pull-up or pulldown resistors. The PECL outputs are capable of driving two series terminated 50  transmission lines on the incident edge.

PIN FUNCTION DESCRIPTION

Pin Name Function Description

INPUTS

XTAL1, XTAL2

S_LOAD* CMOS/TTL Serial Latch Input

S_DATA* CMOS/TTL Serial Data Input

S_CLOCK* CMOS/TTL Serial Clock Input

P_LOAD** CMOS/TTL Parallel Latch Input

M[8:0]** CMOS/TTL PLL Loop Divider

N[1:0]** CMOS/TTL Output Divider Inputs

OE** CMOS/TTL Output Enable Input

OUTPUTS

F

, F

OUT

TEST CMOS/TTL Output The function of this output is determined by the serial configuration bits T[2:0].

POWER

V

CC

PLL_V

CC

GND Negative Power Supply These pins are the negative supply for the chip and are normally all connected to

* When left Open, these inputs will default LOW. ** When left Open, these inputs will default HIGH.

Crystal Inputs These pins form an oscillator when connected to an external series-resonant

(Internal Pulldown Resistor)

(Internal Pullup Resistor)

Inputs (Internal Pullup Resistor)

(Internal Pullup Resistor)

PECL Differential Outputs These differential, positive-referenced ECL signals (PECL) are the outputs of the

Positive Supply for the Logic The positive supply for the internal logic and output buffer of the chip, and is con-

Positive Supply for the PLL This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.

crystal. This pin loads the configuration latches with the contents of the shift registers. The

latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation.

This pin acts as the data input to the serial configuration shift registers.

This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.

This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this signal is LOW; therefore, the parallel data must be stable on the LOW-to-HIGH transition of P_LOAD tion.

These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.

These pins are used to configure the output divider modulus. They are sampled on the LOW-to-HIGH transition of P_LOAD

Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output.

synthesizer.

nected to +3.3 V or +5.0 V.

ground.

.

for proper opera-

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NBC12429

ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 37.5 k ESD Protection Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity (Note 1) PLCC

Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in Transistor Count 2035 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

MAXIMUM RATINGS (Note 2)

Symbol

V

CC

V

I

out

Positive Supply GND = 0 V - 6 V Input Voltage GND = 0 V VI  V Output Current Continuous

TA Operating Temperature Range - - 0 to +70 °C T

stg



JA



JC



JA



JC

T

sol

Storage Temperature Range - - -65 to +150 °C Thermal Resistance (Junction-to-Ambient) 0 LFPM

Thermal Resistance (Junction-to-Case) std bd 28 PLCC 22 to 26 °C/W Thermal Resistance (Junction-to-Ambient) 0 LFPM

Thermal Resistance (Junction-to-Case) std bd 32 LQFP 12 to 17 °C/W Wave Solder < 2 to 3 sec @ 248°C - 265 °C

2. Maximum Ratings are those values beyond which device damage may occur.

Parameter Condition 1 Condition 2 Rating Unit

CC

-

Surge

-

28 PLCC

500 LFPM

28 PLCC

32 LQFP

500 LFPM

32 LQFP

LQFP

> 2 kV

> 150 V

> 1 kV

Level 1 Level 2

6 V

50

100

63.5

43.5

80 55

mA mA

°C/W °C/W

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NBC12429

DC CHARACTERISTICS (V

= 3.3 V ± 5%)

CC

Symbol Characteristic Condition

V

IH

LVCMOS/

Input HIGH Voltage VCC = 3.3 V 2.0 - - 2.0 - - 2.0 - - V

LVTTL V

IL

LVCMOS/

Input LOW Voltage VCC = 3.3 V - - 0.8 - - 0.8 - - 0.8 V

LVTTL I

IN

V

V PECL

I

CC

3. F

4. F

OH

OL

OH

OL

OUT/FOUT OUT/FOUT

Input Current - - 1.0 - - 1.0 - - 1.0 mA Output HIGH Voltage

IOH = -0.8 mA 2.5 - - 2.5 - - 2.5 - - V

TEST

Output LOW Voltage

IOL = 0.8 mA - - 0.4 - - 0.4 - - 0.4 V

TEST

Output HIGH Voltage F

Output LOW Voltage F

Power Supply Current V

PLL_V

F

OUT OUT

VCC = 3.3 V (Notes 3, 4)

CC CC

output levels will vary 1:1 with VCC variation. outputs are terminated through a 50  resistor to VCC - 2.0 V.

0°C 25°C 70°C

Min Typ Max Min Typ Max Min Typ Max

Unit

2.155 - 2.405 2.155 - 2.405 2.155 - 2.405 V

1.355 - 1.605 1.355 - 1.605 1.355 - 1.605 V

481856227026481858227026481861227026mA

mA

DC CHARACTERISTICS (V

= 5.0 V ± 5%)

CC

Symbol Characteristic Condition

V

IH

CMOS/

Input HIGH Voltage VCC = 5.0 V 2.0 - - 2.0 - - 2.0 - - V

TTL V

IL

CMOS/

Input LOW Voltage VCC = 5.0 V - - 0.8 - - 0.8 - - 0.8 V

TTL I

IN

V V V

PECL V

PECL I

CC

5. F

6. F

OH OL OH

OL

Input Current - - 1.0 - - 1.0 - - 1.0 mA Output HIGH Voltage TEST IOH = -0.8 mA 2.5 - - 2.5 - - 2.5 - - V Output LOW Voltage TEST IOL = 0.8 mA - - 0.4 - - 0.4 - - 0.4 V Output HIGH Voltage F

Output LOW Voltage F

Power Supply Current V

OUT/FOUT OUT/FOUT

output levels will vary 1:1 with VCC variation. outputs are terminated through a 50  resistor to VCC - 2.0 volts.

PLL_V

F

OUT OUT

VCC = 5.0 V (Notes 5, 6)

CC CC

0°C 25°C 70°C

Min Typ Max Min Typ Max Min Typ Max

Unit

3.855 - 4.105 3.855 - 4.105 3.855 - 4.105 V

3.055 - 3.305 3.055 - 3.305 3.055 - 3.305 V

501958237527501960237527501965237527mA

mA

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NBC12429

AC CHARACTERISTICS (V

Symbol

F

MAXI

F

MAXO

t

LOCK

t

jitter

t

s

t

h

t

pwMIN

Maximum Input Frequency S_CLOCK

Maximum Output Frequency VCO (Internal)

Maximum PLL Lock Time - 10 ms Cycle-to-Cycle Jitter (1 ) See Applications Section - 20 ps Setup Time S_DATA to S_CLOCK

Hold Time S_DATA to S_CLOCK

Minimum Pulse Width S_LOAD

= 3.125 V to 5.25 V ± 5%; TA = 0° to 70°C) (Note 8)

CC

Characteristic Condition Min Max Unit

Xtal Oscillator

F

OUT

S_CLOCK to S_LOAD

M, N to P_LOAD

P_LOAD

(Note 7) -

10

200

25

20 20 20

20 20

50 50

10 20

400 400

-

MHz

ns

DCO Output Duty Cycle 47.5 52.5 % tr, t

f

Output Rise/Fall F

20%-80% 175 425 ps

OUT

7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as

a test clock in TEST_MODE 6.

8. F

OUT/FOUT

outputs are terminated through a 50  resistor to VCC - 2.0 V.

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