ON Semiconductor NB7V33MMNG, NB6N11SMNG User Manual

NB7V33MMNGEVB

NB7V33MMNG
Evaluation Board
User's Manual

Introduction

ON Semiconductor has developed the QFN16EVB
evaluation board for its high-performance devices packaged
in the 16-pin QFN. This evaluation board was designed to
provide a flexible and convenient platform to quickly
evaluate, characterize and verify the operation of various
ON Semiconductor products. Many QFN16EVBs are
dedicated with a device already installed, and can be ordered
from www.onsemi.com at the specific device web page.

This evaluation board manual contains:

 Information on 16-lead QFN Evaluation Board
 Assembly Instructions
 Appropriate Lab Setup
 Bill of Materials

This user’s manual provides detailed information on
board contents, layout and its use. It should be used in
conjunction with an appropriate ON Semiconductor device
datasheet located at www.onsemi.com. The datasheet
contains the technical device specifications.

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EVAL BOARD USER’S MANUAL

Board Layout

The QFN16 Evaluation Board provides a high bandwidth,

50 W controlled impedance environment and is
implemented in four layers. The first layer or primary trace
layer is 0.008 thick Rogers RO4003 material, and is
designed to have equal electrical length on all signal traces
from the device under test (DUT) pins to the SMA
connectors. The second layer is the 1.0 oz copper ground
plane and is primarily dedicated for the SMA connector
ground plane. FR4 dielectric material is placed between the
second and third layers and between third and fourth layers.
The third layer is also 1.0 oz copper plane. A portion of this
layer is designated for the device V
planes. The fourth layer is the secondary trace layer.

and DUTGND power

CC

Top View Bottom View

Figure 1. Top and Bottom View of the 16 QFN Evaluation Board

 Semiconductor Components Industries, LLC, 2013

May, 2013 − Rev. 0

1 Publication Order Number:

EVBUM2187/D

NB7V33MMNGEVB

Figure 2. Enlarged Bottom View

Pin 13

Pin 14

Pin 15

Pin 16

VEE/DUTGND

VCC

SMA_GND

Pin 12

Pin 11

Pin 10

Pin 9

DUT_GND

Pin 8

Pin 7

Pin 6

Pin 5

Figure 3. Enlarged Bottom View of the Evaluation Board

SILKSCREEN (TOP SIDE)

LAYER 1 (TOP SIDE) 1 OZ

ROGERS 4003 0.008 in

LAYER 2 (GROUND PLANE P1) 1 OZ

LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ

LAYER 4 (BOTTOM SIDE) 1 OZ

FR−4 0.020 in

FR−4 0.025 in

Pin 1

Pin 2

Pin 3

SMA_GND

Pin 4

0.062  0.007

Figure 4. Evaluation Board Layout, 4 Layer

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NB7V33MMNGEVB

Figure 5. Evaluation Board Layout

Bottom ViewTop View

Evaluation Board Assembly Instructions

The QFN−16 evaluation board is designed for
characterizing devices in a 50 W laboratory environment
using high bandwidth equipment. Each signal trace on the
board has a via at the DUT pin, which provides an option of
placing a termination resistor on the board bottom,
depending on the input/output configuration (see Table 1,
Configuration for Device: NB7V33M). Table 4 contains the
Bill of Materials for this evaluation board.

The QFN16EVB was designed to accommodate a custom
QFN−16 socket. Therefore, some external components are
installed on the bottom side of the board.

Solder the Device on the Evaluation Board

The soldering of a device to the evaluation board can be
accomplished by hand soldering or solder reflow techniques
using solder paste. Make sure pin 1 of the device is located
properly and all the pins are aligned to the footprint pads.
Solder the QFN−16 device to the evaluation board. As
mentioned earlier, many QFN16EVBs are dedicated with a
device already installed, and can be ordered from
onsemi.com at the specific device web page.

Connecting Power and Ground

On the top side of the evaluation board, solder the four
surface mount test point clips (anvils) to the pads labeled
V

, VEE/DUTGND, SMAGND, and ExPad. ExPad is

CC

connected to the exposed flag of the QFN package. For
proper operation, the exposed flag is typically
recommended to be tied to V

/DUTGND, the negative

EE

supply of the device.

The positive power supply connector is labeled V

CC

Depending on the device, the negative power supply
nomenclature is labeled either GND or V

. To help avoid

EE

confusion with the use of this board, the negative supply
connector is labeled V

/DUTGND. SMAGND is the

EE

ground for the SMA connectors and is not to be confused
with the device ground, V

/DUTGND. SMAGND and

EE

DUTGND can be connected in single-supply applications.
The power pin layout and typical connection of the
evaluation board is shown in Figure 6.

It is recommended to add bypass capacitors to reduce

unwanted noise from the power supplies. Connect 0.1 mF
capacitors from V

Output Loading/Termination

ECL/PECL/LVPECL

and VEE/DUTGND to SMA_GND.

CC

Outputs

Most ECL outputs are open emitter and need to be DC

loaded and AC terminated to V

− 2.0 V via a 50 W resistor.

CC

If no internal resistors are provided on the device, 0402 chip
resistor pads are provided on the bottom side of the
evaluation board to terminate the ECL driver. Solder the
chip resistors to the bottom side of the board between the
appropriate input device pads and the ground pads. If
internal resistors are provided, the VT pins should be wired
to SMAGND. (More information on termination is provided
in AND8020).

For standard ECL lab setup and test, a split (dual) power

supply is recommended enabling the 50 W internal
impedance in the oscilloscope, or other measuring
instrument, to be used as an ECL output load/termination.
By offsetting V
(SMAGND is the system ground, 0V); V
V

/DUTGND is −3.0 V, −1.3 V or −0.5 V; see Table 2,

.

EE

Power Supply Levels).

= +2.0 V, SMAGND = VCC − 2.0 V,

CC

CC

is 2.0 V, and

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