ON Semiconductor NB6N11S Technical data

NB6N11S

3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator

Description

The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical copies of Cloc k o r D a t a will be distributed, operating up to 2.0 GHz or

2.5 Gb/s, respectively. As such, the NB6N11S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications.

The NB6N11S has a wide input common mode range from GND + 50 mV to V termination resistors at the inputs, the NB6N11S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels.

The NB6N11S is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices and is offered in a small, 3 mm X 3 mm, 16−QFN package. Application notes, models, and support documentation are available at www.onsemi.com

The NB6N11S is a member of the ECLinPS MAX™ family of high performance products.

Features

• Maximum Input Clock Frequency > 2.0 GHz

• Maximum Input Data Rate > 2.5 Gb/s

• 1 ps Maximum of RMS Clock Jitter

• Typically 10 ps of Data Dependent Jitter

• 380 ps Typical Propagation Delay

• 120 ps Typical Rise and Fall Times

• Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and

SG Devices

• These are Pb−Free Devices

− 50 mV. Combined with the 50 W internal

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MARKING

DIAGRAM*

QFN−16 MN SUFFIX CASE 485G

A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

D D

NB6N

11S

ALYWG

Q0 Q0

Device DDJ = 10 ps

VOLTAGE (130 mV/div)

TIME (58 ps/div)

Figure 2. Typical Output Waveform at 2.488 Gb/s with

PRBS 2

April, 2007 − Rev. 1

23−1

= 400 mV; Input Signal DDJ = 14 ps)

INPP

Figure 1. Logic Diagram

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.

1 Publication Order Number:

Q1 Q1

NB6N11S/D

NB6N11S

Exposed Pad (EP)

VCCVCCV

16 15 14 13

NB6N11S

5678

NC VEEV

Figure 3. NB6N11S Pinout, 16−pin QFN (Top View)

Table 1. PIN DESCRIPTION

Pin Name I/O Description

1 Q0 LVDS Output

2 Q0 LVDS Output

3 Q1 LVDS Output

4 Q1 LVDS Output

5 V

− Positive Supply Voltage 6 NC No Connect 7 V 8 V 9 V

EE EE TD

−

10 D LVPECL, CML, LVDS,

LVCMOS, LVTTL

11 D LVPECL, CML, LVDS,

LVCMOS, LVTTL 12 V 13 V 14 V 15 V 16 V

TD CC CC CC CC

−

− Positive Supply Voltage

EP Exposed pad. The exposed pad (EP) on the package bottom must be

1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage or left open, and if no signal is applied on D0/D0

, D1/D1 input, then the device will be susceptible to self−oscillation.

Non−inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair.

Inverted D output. Typically loaded with 10 W receiver termination resistor across differential pair.

Non−inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair.

Inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair.

Negative Supply Voltage Negative Supply Voltage Internal 50 W termination pin for D Inverted Differential Clock/Data Input (Note 1)

Non−inverted Differential Clock/Data Input (Note 1)

Internal 50 W termination pin for D

attached to a heat−sinking conduit. The exposed pad may only be electrically connected to V

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NB6N11S

Table 2. ATTRIBUTES

Characteristics Value

ESD Protection Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Pb Pkg Pb−Free Pkg

QFN−16 − 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 225 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

2. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

OSC

stg

sol

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Opera t i n g Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.

Positive Power Supply GND = 0 V 3.8 V Positive Input GND = 0 V VIN ≤ V Input Current Through R

(50 W Resistor)

Static Surge

Output Short Circuit Current Line−to−Line (Q to Q Line−to−End (Q or Q to GND)

)

Q or Q to GND

Q to Q Operating Temperature Range QFN−16 −40 to +85 °C Storage Temperature Range −65 to +150 °C Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm

500 lfpm Thermal Resistance (Junction−to−Case) 1S2P (Note 3) QFN−16 4.0 °C/W

Wave Solder Pb

Pb−Free

> 2 kV

> 200 V

> 1 kV

Continuous Continuous

QFN−16 QFN−16

3.8 V 35

12 24

41.6

35.2

265 265

mA mA

°C/W °C/W

°C

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